CN111798555A

CN111798555A - Apparatus and method for reduced precision bounding volume hierarchy

Info

Publication number: CN111798555A
Application number: CN202010157897.4A
Authority: CN
Inventors: M.多伊尔; K.维亚纳桑
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2019-04-04
Filing date: 2020-03-09
Publication date: 2020-10-20

Abstract

The subject of the invention is "an apparatus and method for bounding volume hierarchy for reduced precision". Apparatus and methods for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene, the graphics data containing a plurality of primitives in the scene at a first precision; a geometric quantizer to read vertices of the primitive at a first precision and adaptively quantize the vertices of the primitive to a second precision associated with a first local coordinate grid of a first BVH node located within the global coordinate grid, the second precision being lower than the first precision; a BVH builder to determine coordinates for children of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, the BVH builder to determine final coordinates for the children based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the children.

Description

Apparatus and method for reduced precision bounding volume hierarchy

Cross reference to related applications

This application claims the benefits of co-pending U.S. patent application No.62/829,523, filed 2019, 4/4, the entire contents of which are incorporated herein by reference.

Technical Field

The present invention relates generally to the field of graphics processors. More particularly, the present invention relates to an apparatus and method for bounding volume hierarchy (bounding volume hierarchy) construction with reduced precision.

Background

Ray tracing is a technique in which light transmission is simulated by physics-based rendering. It is widely used in movie rendering, until just a few years ago it was considered too resource intensive for real-time performance. One of the key operations in ray tracing is to process a visibility query for ray-scene intersections, called "ray traversal", which computes ray-scene intersections by traversing and intersecting nodes in the bounding volume level (BVH).

Drawings

A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

FIG. 1 is a block diagram of an embodiment of a computer system with a processor having one or more processor cores and a graphics processor;

2A-D are block diagrams of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor;

3A-C are block diagrams of one embodiment of a graphics processor, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores;

FIG. 4 is a block diagram of an embodiment of a graphics processing engine for a graphics processor;

5A-B are block diagrams of another embodiment of a graphics processor.

FIG. 6 illustrates an example of execution circuitry and logic;

FIG. 7 illustrates a graphics processor execution unit instruction format, according to an embodiment;

FIG. 8 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline;

FIG. 9A is a block diagram illustrating a graphics processor command format according to an embodiment;

FIG. 9B is a block diagram illustrating a graphics processor command sequence, according to an embodiment;

FIG. 10 illustrates an exemplary graphics software architecture for a data processing system, according to an embodiment;

11A-D illustrate an exemplary IP core development system that may be used to fabricate integrated circuits and exemplary package assemblies;

FIG. 12 illustrates an exemplary system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment;

FIG. 13 illustrates an exemplary graphics processor of a system-on-a-chip integrated circuit that may be fabricated using one or more IP cores;

FIG. 14 illustrates an exemplary graphics processor architecture;

FIG. 15 illustrates one embodiment of an architecture for performing initial training of a machine learning architecture;

FIG. 16 illustrates one embodiment in which the machine learning engine is continually trained and updated during runtime;

FIG. 17 illustrates another embodiment in which the machine learning engine is continually trained and updated during runtime;

18A-B illustrate embodiments in which machine learning data is shared over a network; and

FIG. 19 illustrates one embodiment of a method for training a machine learning engine;

FIG. 20 illustrates one embodiment in which nodes exchange ghost region (ghost region) data to perform a distributed denoising operation;

FIG. 21 illustrates one embodiment of an architecture in which image rendering and denoising operations are distributed across multiple nodes;

FIG. 22 illustrates additional details of an architecture for distributed rendering and denoising;

FIG. 23 illustrates a method according to an embodiment of the invention;

FIG. 24 illustrates one embodiment of a machine learning method;

FIG. 25 illustrates a plurality of interconnected general purpose graphics processors;

FIG. 26 illustrates a set of convolutional layers and fully-connected layers for a machine-learning implementation;

FIG. 27 illustrates one embodiment of a convolutional layer;

FIG. 28 illustrates an example of a set of interconnected nodes in a machine learning implementation;

FIG. 29 illustrates an embodiment of a training framework within which a neural network learns using a training data set;

FIG. 30A illustrates examples of model parallelism (model parallelism) and data parallelism (data parallelism);

FIG. 30B illustrates an example of a system on a chip (SoC);

FIG. 31 illustrates an example of a processing architecture including a ray tracing core and a tensor core;

FIG. 32A illustrates an example Bounding Volume Hierarchy (BVH) structure;

FIG. 32B illustrates a 2D representation of a BVH parent node and one of its children nodes;

FIG. 33 illustrates the relationship between floating point space and a global grid;

34A-D illustrate features associated with axis-aligned bounding boxes within a local grid and/or scene;

FIG. 35 illustrates an example of left and right child nodes within a parent node;

36A-B illustrate features associated with spatial segmentation and object segmentation; and

FIG. 37 illustrates one embodiment of a ray tracing architecture.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of embodiments of the present invention.

Exemplary graphics processor architecture and data types

Overview of the System

Fig. 1 is a block diagram of a processing system 100 according to an embodiment. The system 100 may be used in a single processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, the system 100 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device, such as within an internet of things (IoT) device with wired or wireless connectivity to a local or wide area network.

In one embodiment, the system 100 can contain, be coupled with, or be integrated within: a server-based game platform; a game console, including a game and media console, a mobile game console, a handheld game console, or an online game console. In some embodiments, system 100 is part of: a mobile phone, a smart phone, a tablet computing device or a mobile internet connected device such as a laptop with low internal storage capacity. The processing system 100 can also contain, be coupled with or be integrated within: wearable devices, such as smart watch wearable devices; smart glasses (smart eyewear) or apparel augmented with Augmented Reality (AR) or Virtual Reality (VR) features to provide visual, audio, or haptic output to supplement a real visual, audio, or haptic experience or otherwise provide text, audio, graphics, video, holographic images or video, or haptic feedback; other Augmented Reality (AR) devices; or other Virtual Reality (VR) device. In some embodiments, the processing system 100 comprises or is part of a television or set-top box device. In one embodiment, the system 100 can contain, be coupled with, or be integrated within: an autonomous vehicle such as a bus, a tractor-trailer, a car, a motorcycle or an electric bicycle, an airplane or a glider (or any combination thereof). Autonomous vehicles may use the system 100 to process the environment sensed around the vehicle.

In some embodiments, the one or more processors 102 each include one or more processor cores 107 to process instructions that, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). One or more processor cores 107 may process different instruction sets 109, which instruction sets 109 may contain instructions to facilitate emulation of other instruction sets. Processor core 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. The register file 106 can additionally be included in the processor 102 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

In some embodiments, one or more processors 102 are coupled with one or more interface buses 110 to transmit communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. Interface bus 110 can be a processor bus in one embodiment, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus, and may include one or more peripheral component interconnect buses (e.g., PCI express), memory buses, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and platform controller hub 130. The memory controller 116 facilitates communication between the memory devices and other components of the system 100, while the Platform Controller Hub (PCH)130 provides a connection to I/O devices via a local I/O bus.

Memory device 120 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. In one embodiment, memory device 120 is capable of operating as system memory for system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute an application or process. The memory controller 116 is also coupled with an optional external graphics processor 118, which external graphics processor 118 may communicate with one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, graphics, media, and/or computing operations may be assisted by an accelerator 112, which accelerator 112 is a co-processor that can be configured to perform a specialized set of graphics, media, or computing operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or computational operations. In one embodiment, the accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in conjunction with the graphics processor 108. In one embodiment, an external accelerator 119 may be used in place of accelerator 112 or in conjunction with accelerator 112.

In some embodiments, a display device 111 can be connected to the processor(s) 102. The display device 111 can be one or more of an internal display device as in a mobile electronic device or laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, display device 111 can be a Head Mounted Display (HMD), such as a stereoscopic display device for use in Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In some embodiments, the platform controller hub 130 enables peripherals to be connected to the memory devices 120 and the processor 102 via a high speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, a data storage 124 (e.g., non-volatile memory, hard drive, flash memory, NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long Term Evolution (LTE) transceiver. The firmware interface 128 enables communication with system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 134 can enable a network connection to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to interface bus 110. The audio controller 146 in one embodiment is a multi-channel high definition audio controller. In one embodiment, the system 100 includes an optional legacy I/O controller 140 for coupling legacy (e.g., personal System 2(PS/2)) devices to the system. The platform controller hub 130 can also be connected to one or more Universal Serial Bus (USB) controllers 142 to connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

It will be appreciated that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, the instances of the memory controller 116 and the platform controller hub 130 may be integrated into a separate external graphics processor, such as the external graphics processor 118. In one embodiment, the platform controller hub 130 and/or the memory controller 116 may be external to the one or more processors 102. For example, the system 100 can include an external memory controller 116 and a platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset in communication with the processor(s) 102.

For example, a circuit board ("sled") can be used on which components such as CPUs, memory and other components can be placed, which is designed for increased thermal performance. In some embodiments, a processing component, such as a processor, is located on the top side of the sled, while a near memory, such as a DIMM, is located on the bottom side of the sled. As a result of the enhanced air flow provided by this design, the assembly may operate at higher frequencies and power levels than in typical systems, thereby increasing performance. Further, the skillets are configured to blindly mate with the power and data communication cables in the racks, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, various components located on the sled (such as processors, accelerators, memory, and data storage drives) are configured to be easily upgraded due to their increased spacing from one another. In an illustrative embodiment, the component additionally includes hardware attestation features to prove its authenticity.

A data center can utilize a single network architecture ("fabric") that supports multiple other network architectures including ethernet and full Path (Omni-Path). The sled can be coupled to the switch via optical fibers that provide higher bandwidth and lower time delay than typical twisted pair cables (e.g., category 5e, category 6, etc.). Due to the high bandwidth, low latency interconnect and network architecture, the data center may use physically disaggregated pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural networks, and/or artificial intelligence accelerators, etc.), and data storage drives, and provide them to computing resources (e.g., processors) on an as-needed basis, so that the computing resources can access the pooled resources as if the pooled resources were local.

The power supply or power source can provide voltage and/or current to the system 100 or any component or system described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC to DC converter. In one example, a power source or power supply includes wireless charging hardware to charge via a proximity charging field. In one example, the power source can comprise an internal battery, an alternating current supply, a motion-based power supply, a solar power supply, or a fuel cell source.

2A-2D illustrate a computing system and graphics processor provided by embodiments described herein. The elements of fig. 2A-2D having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

FIG. 2A is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 can include additional cores up to and including additional core 202N, represented by a dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core may also access one or more shared cache units 206. Internal cache units 204A-204N and shared cache unit 206 represent cache memory levels within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, as well as one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, with the highest level of cache preceding external memory being classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or more bus controller units 216 and a system agent core 210. One or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI express buses. The system agent core 210 provides management functionality for various processor components. In some embodiments, the system proxy core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system proxy core 210 includes components for coordinating and operating the cores 202A-202N during processing of multiple threads. The system proxy core 210 may additionally include a Power Control Unit (PCU) that includes logic and components to regulate the power states of the processor cores 202A-202N and the graphics processor 208.

In some embodiments, the processor 200 additionally includes a graphics processor 208 to perform graphics processing operations. In some embodiments, the graphics processor 208 is coupled to a set of shared cache units 206 and a system proxy core 210 that includes one or more integrated memory controllers 214. In some embodiments, the system proxy core 210 also includes a display controller 211 to drive graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 208.

In some embodiments, ring-based interconnect unit 212 is used to couple internal components of processor 200. However, alternative interconnect elements may be used, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques known in the art. In some embodiments, the graphics processor 208 is coupled with the ring interconnect 212 via an I/O link 213.

Exemplary I/O link 213 represents at least one of a plurality of kinds of I/O interconnects, including on-package I/O interconnects that facilitate communication between various processor components and a high performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 can use the embedded memory module 218 as a shared last level cache.

In some embodiments, processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in Instruction Set Architecture (ISA), wherein one or more of the processor cores 202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in micro-architecture, with one or more cores having relatively higher power consumption coupled with one or more power cores having lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous in computing power. Additionally, processor 200 can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, among other components.

Fig. 2B is a block diagram of hardware logic of graphics processor core 219 according to some embodiments described herein. Elements of fig. 2B having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Graphics processor core 219, sometimes referred to as a core slice, can be one or more graphics cores within a modular graphics processor. Graphics processor core 219 is an example of one graphics core slice, and a graphics processor as described herein may contain multiple graphics core slices based on a target power and performance envelope. Each graphics processor core 219 can include a fixed function block 230 coupled to a plurality of sub-cores 221A-221F, also referred to as sub-slices, the plurality of sub-cores 221A-221F including modular blocks of general purpose and fixed function logic.

In some embodiments, the fixed function block 230 includes a geometry/fixed function pipeline 231, the geometry/fixed function pipeline 231 capable of being shared by all sub-slices in the graphics processor core 219, for example, in lower performance/or lower power graphics processor implementations. In various embodiments, geometry/fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 in fig. 3 and 4, described below), a video front end unit, a thread spawner (thread spawner), and a thread dispatcher (thread dispatcher), and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418 in fig. 4, described below).

In one embodiment, fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. Graphics SoC interface 232 provides an interface between graphics processor core 219 and other processor cores within the system-on-a-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that may be configured to manage various functions of the graphics processor core 219, including thread dispatch, scheduling, and preemption (pre-preemption). Media pipeline 234 (e.g., media pipeline 316 of fig. 3 and 4) includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data including image and video data. Media pipeline 234 implements media operations via requests to computational or sampling logic within sub-core 221-221F.

In one embodiment, SoC interface 232 enables graphics processor core 219 to communicate with a general-purpose application processor core (e.g., CPU) and/or other components within the SoC including memory hierarchy elements such as shared last level cache, system RAM, and/or embedded on-chip or on-package DRAM. SoC interface 232 may also enable communication with fixed function devices within the SoC (such as camera imaging pipelines), and enable use of and/or implementation of global memory atoms that may be shared between graphics processor core 219 and CPUs within the SoC. SoC interface 232 may also enable power management control for graphics processor core 219 and enable an interface between the clock domain of graphics core 219 and other clock domains within the SoC. In one embodiment, SoC interface 232 enables receiving command buffers (command buffers) from a command streamer (global thread dispatcher) and a global thread dispatcher, the command buffers configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. Commands and instructions can be dispatched to the media pipeline 234 when media operations are to be performed or to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 231, geometry and fixed function pipeline 237) when graphics processing operations are to be performed.

The graphics microcontroller 233 can be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment, the graphics microcontroller 233 is capable of performing graphics and/or computational workload scheduling on various graphics parallel engines within the Execution Unit (EU) arrays 222A-222F, 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC that contains graphics processor core 219 is able to submit a workload to one of a plurality of graphics processor doorbells (graphics processor doorbells), which invokes a scheduling operation on the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to the command streamer, preempting an existing workload running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, graphics microcontroller 233 can also facilitate a low power or idle state for graphics processor core 219, providing graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 across low power state transitions independent of the operating system and/or graphics driver software on the system.

Graphics processor core 219 may have more or fewer than the illustrated sub-cores 221A-221F, up to N modular sub-cores. Graphics processor core 219 can also include, for each set of N sub-cores, shared function logic 235, shared and/or cache memory 236, geometry/fixed function pipelines 237, and additional fixed function logic 238 to accelerate various graphics and computing processing operations. Shared function logic 235 can include logic units (e.g., samplers, math and/or inter-thread communication logic) associated with shared function logic 420 of fig. 4 that can be shared by every N subcores within graphics processor core 219. The shared and/or cache memory 236 can be a last level cache for a set of N sub-cores 221A-221F within the graphics processor core 219, and can also act as a shared memory accessible by multiple sub-cores. The geometry/fixed function pipeline 237 can be included within the fixed function block 230 in place of the geometry/fixed function pipeline 231 and can include the same or similar logic units.

In one embodiment, graphics processor core 219 includes additional fixed function logic 238, which can include various fixed function acceleration logic for use by graphics processor core 219. In one embodiment, the additional fixed function logic 238 contains additional geometry pipelines for use in position-only shading. In position-only shading, there are two geometric pipelines: a full geometry pipeline within the geometry/fixed function pipelines 238, 221; and a culling pipeline (cullpipeline), which is another geometric pipeline that may be included within the other fixed function logic 238. In one embodiment, the sort-out pipeline is a truncated version of the full geometry pipeline. The full pipeline and the culling pipeline are capable of executing different instances of the same application, each instance having a separate context. Location-only shading can hide long pick runs of discarded triangles so that shading can be done earlier in some instances. For example and in one embodiment, the culling pipeline logic within the additional fixed function logic 238 is capable of executing position shaders in parallel with the host application and generally generates critical results faster than a full pipeline because the culling pipeline only takes and colors position attributes of vertices without performing rasterization (rasterization) and rendering of pixels to a frame buffer. The culling pipeline can use the generated key results to calculate visibility information for all triangles regardless of whether those triangles were culled. The full pipeline (which may be referred to as a replay pipeline in this example) can consume visibility information to skip culled triangles to color only the visible triangles that are eventually passed to the rasterization stage.

In one embodiment, the additional fixed function logic 238 can also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementation that includes optimization for machine learning training or reasoning.

Within each graphics sub-core 221A-221F is a set of execution resources that may be used to perform graphics, media, and computational operations in response to requests by a graphics pipeline, media pipeline, or shader program. Graphics sub-cores 221A-221F include a plurality of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD/IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and Shared Local Memories (SLMs) 228A-228F. The EU arrays 222A-222F, 224A-224F each include a plurality of execution units, which are general purpose graphics processing units capable of performing floating point and integer/fixed point logical operations for servicing graphics, media, or computational operations, including graphics, media, or compute shader programs. The TD/IC logic 223A-223F performs local thread dispatch and thread control operations for execution units within the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. 3-D samplers 225A-225F can read texture or other 3-D graphics related data into memory. The 3D sampler can read texture data in different ways based on the configured sample states and the texture format associated with a given texture. Media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F can alternately contain unified 3D and media samplers. Threads executing on execution units within each of the sub-cores 221A-221F can utilize the shared local memory 228A-228F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

FIG. 2C illustrates a Graphics Processing Unit (GPU)239 that includes a dedicated set of graphics processing resources arranged into multi-core groups 240A-240N. While details are provided for only a single multi-core group 240A, it will be appreciated that the other multi-core groups 240B-240N may be equipped with the same or similar set of graphics processing resources.

As illustrated, multi-core group 240A may include a set of graph cores 243, a set of tensor cores 244, and a set of ray trace cores 245. Scheduler/dispatcher 241 schedules and dispatches graphics threads for execution on the

various cores

243, 244, 245. The set of register files 242 stores operand values used by the

cores

243, 244, 245 in executing the graphics threads. These registers may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements), and tile registers (tile registers) for storing tensor/matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

One or more combined level 1 (L1) cache and shared memory units 247 locally store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, and the like, within each multi-core group 240A. One or more texture units 247 can also be used to perform texture operations, such as texture mapping and sampling. A level 2 (L2) cache 253 shared by all or a subset of the multi-core groups 240A-240N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across multiple multi-core groups 240A-240N. The one or more memory controllers 248 couple the GPU 239 to memory 249, which memory 249 may be system memory (e.g., DRAM) and/or dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuitry 250 couples the GPU 239 to one or more I/O devices 252, such as Digital Signal Processors (DSPs), network controllers, or user input devices. On-chip interconnects may be used to couple the I/O devices 252 to the GPU 239 and memory 249. One or more I/O memory management units (IOMMU)251 of the I/O circuitry 250 directly couple the I/O devices 252 to the system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, the I/O device 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

In one implementation, IOMMU 251 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 249). The base of each of the first and second sets of page tables may be stored in a control register and swapped out on a context switch (e.g., so that access to the relevant set of page tables is provided for the new context). Although not illustrated in FIG. 2C, each of the

cores

243, 244, 245 and/or multi-core groups 240A-240N may include a Translation Lookaside Buffer (TLB) to cache guest virtual-to-guest physical translations, guest physical-to-host physical translations, and guest virtual-to-host physical translations.

In one embodiment, the CPU 246, GPU 239, and I/O devices 252 are integrated on a single semiconductor chip and/or chip package. The illustrated memory 249 may be integrated on the same chip or may be coupled to the memory controller 248 via an off-chip interface. In one implementation, memory 249 comprises GDDR6 memory, which GDDR6 memory shares the same virtual address space with other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

In one embodiment, the tensor core 244 includes a plurality of execution units specifically designed to perform matrix operations, which are the basic computation operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and reasoning. The tensor core 244 may perform matrix processing using various operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and nibble (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high quality final image.

In a deep learning implementation, the parallel matrix multiplication work may be scheduled for execution on the tensor core 244. Training of neural networks requires, in particular, a large number of matrix dot-product operations. To process the inner product formulation of the nx N matrix multiplication, the tensor kernel 244 may contain at least N dot product processing elements. Before the start of matrix multiplication, a complete matrix is loaded into the tile register, and at least one column of the second matrix is loaded in each of the N cycles. At each cycle, there are N dot products processed.

Depending on the particular implementation, the matrix elements may be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT 4). Different precision modes can be specified for the tensor core 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads that can tolerate quantization to bytes and nibbles).

In one embodiment, ray tracing core 245 speeds up ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traversal/intersection circuitry to perform ray traversal using a Bounding Volume Hierarchy (BVH) and identify intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 245 may also contain circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar arrangement). In one implementation, ray tracing kernel 245 performs traversal and intersection operations in cooperation with the image denoising techniques described herein, at least a portion of which may be performed on tensor kernel 244. For example, in one embodiment, the tensor kernel 244 implements a deep learning neural network to perform denoising of frames generated by the ray tracing kernel 245. However, CPU(s) 246, graphics kernel 243 and/or ray tracing kernel 245 may also implement all or a portion of a denoising and/or deep learning algorithm.

Additionally, as described above, a distributed approach to denoising may be employed where the GPU 239 is in a computing device coupled to other computing devices through a network or high speed interconnect. In this embodiment, interconnected computing devices share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, ray tracing core 245 handles all BVH traversals and ray-primitive intersections, thereby avoiding overloading the graphics core 243 with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, in one embodiment, the multi-core group 240A can simply launch the ray probe, and the ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. While the ray tracing core 245 performs traversal and intersection operations, the

other cores

243, 244 are released to perform other graphics or computational work.

In one embodiment, each ray tracing core 245 includes a traversal unit to perform BVH test operations and an intersection unit to perform ray-primitive intersection tests. The crossbar unit generates a "hit", "no-hit", or "multiple-hit" response, and the crossbar unit provides the response to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between graphics core 243 and ray tracing core 245.

In one embodiment, the ray tracing core 245 (and/or other cores 243, 244) includes hardware support for a ray tracing instruction set such as Microsoft's DirectX ray tracing (DXR), which includes the DispatchRays command along with ray generation, closest hits, arbitrary hits, and miss shaders, which enable each object to be assigned a unique set of textures and shaders. Another ray tracing platform that may be supported by ray tracing core 245, graph core 243, and tensor core 244 is Vulkan 1.1.85. Note, however, that the underlying principles of the invention are not limited to any particular ray tracing ISA.

In general, the

various cores

245, 244, 243 may support a ray trace instruction set that includes instructions/functions for ray generation, closest hits, any hits, ray-primitive intersections, per-primitive and hierarchical bounding box constructions, misses, accesses, and exceptions (exceptions). More specifically, one embodiment includes ray tracing instructions to perform the following functions:

ray generation-ray generation instructions may be executed for each pixel, sample, or other user-defined job assignment.

Closest hit-the closest hit instruction may be executed to locate the closest intersection of rays with primitives within the scene.

Any hit-any hit instruction identifies multiple intersections between primitives and rays within the scene, potentially identifying a new closest intersection.

The cross-cross instruction performs a ray-primitive cross test and outputs a result.

Per-primitive bounding box construction-this instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

Miss-indicating a ray misses all geometric shapes within a scene or a specified region of a scene.

Visit-child (child volume) that indicates the ray will traverse.

Exceptions-include various types of exception handlers (e.g., invoked for various error conditions).

Fig. 2D is a block diagram of a General Purpose Graphics Processing Unit (GPGPU)270 that can be configured as a graphics processor and/or compute accelerator according to embodiments described herein. The GPGPU270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and/or memory buses. In one embodiment, memory 271 is a system memory that may be shared with one or more CPUs 246, while memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU270 and device memory 272 may be mapped to memory addresses accessible to one or more CPUs 246. Access to the memories 271 and 272 may be facilitated via the memory controller 268. In one embodiment, memory controller 268 includes an internal Direct Memory Access (DMA) controller 269 or can include logic to perform operations that would otherwise be performed by a DMA controller.

The GPGPU270 includes a plurality of caches including an L2 cache 253, an L1 cache 254, an instruction cache 255, and a shared memory 256, at least a portion of which shared memory 256 may also be partitioned into caches. GPGPU270 also includes a plurality of compute units 260A-260N. Each compute unit 260A-260N contains a set of vector registers 261, scalar registers 262, vector logic 263, and scalar logic 264. The compute units 260A-260N can also contain a local shared memory 265 and a program counter 266. The compute units 260A-260N can be coupled with a constant cache 267, which constant cache 267 can be used to store constant data, which is data that will not change during the execution of kernel or shader programs executing on the GPGPU 270. In one embodiment, the constant cache 267 is a scalar data cache, and cached data can be fetched directly into the scalar registers 262.

During operation, one or more CPUs 246 can write commands to registers or memory in GPGPU 270 that have been mapped into addressable address space. The command processor 257 is able to read commands from registers or memory and determine how those commands will be processed within the GPGPU 270. Thread dispatcher 258 can then be used to dispatch threads to compute units 260A-260N to execute those commands. Each compute unit 260A-260N is capable of executing threads independently of the other compute units. In addition, each of the computation units 260A-260N can be independently configured for conditional computations and can conditionally output the results of the computations to memory. The command processor 257 is able to interrupt one or more CPUs 246 when the submitted command is complete.

3A-3C illustrate block diagrams of additional graphics processor and compute accelerator architectures provided by embodiments described herein. The elements of fig. 3A-3C having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

Fig. 3A is a block diagram of a graphics processor 300, which graphics processor 300 may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates with registers on the graphics processor via a memory mapped I/O interface and communicates with commands placed into processor memory. In some embodiments, graphics processor 300 includes a memory interface 314 to access memory. Memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a display controller 302 to drive display output data to a display device 318. The display controller 302 contains hardware for one or more overlay planes for displaying and combining multiple layers of user interface elements or video. The display device 318 can be an internal or external display device. In one embodiment, display device 318 is a head mounted display device, such as a Virtual Reality (VR) display device or an Augmented Reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 to encode, decode, or transcode media into, encode, decode, or transcode media from, or between one or more media encoding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as h.264/MPEG-4AVC, h.265/HEVC, open media alliance (AOMedia) VP8, VP9, and Society of Motion Picture and Television Engineers (SMPTE)421M/VC-1 and Joint Photographic Experts Group (JPEG) formats such as JPEG, and motion JPEG (mjpeg) formats.

In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a Graphics Processing Engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 312 contains programmable and fixed function elements that perform various tasks and/or spawn (spawn) execution threads within the elements to the 3D/media subsystem 315. While the 3D pipeline 312 can be used to perform media operations, embodiments of the GPE 310 also include a media pipeline 316 that is particularly used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline 316 contains fixed-function or programmable logic units to perform one or more dedicated media operations, such as video decoding acceleration, video de-interleaving, and video encoding acceleration, in place of or on behalf of video codec engine 306. In some embodiments, media pipeline 316 additionally includes a thread spawning unit to spawn threads for execution on 3D/media subsystem 315. The spawned threads perform computations for media operations on one or more graphics execution units contained in 3D/media subsystem 315.

In some embodiments, 3D/media subsystem 315 contains logic for executing threads spawned by 3D pipeline 312 and media pipeline 316. In one embodiment, the pipeline sends thread execution requests to the 3D/media subsystem 315, the 3D/media subsystem 315 including thread dispatch logic for arbitrating and dispatching various requests (arbitrates) to the available thread execution resources. The execution resources include an array of graphics execution units to process 3D and media threads. In some embodiments, 3D/media subsystem 315 contains one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes a shared memory including registers and addressable memory to share data between the threads and to store output data.

FIG. 3B illustrates a graphics processor 320 having a tiled (tiled) architecture, according to embodiments described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322, the graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A within the graphics engine tiles 310A-310D. Each graphics engine tile 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each graphics engine tile 310A-310D can also be connected to a memory module or memory device 326A-326D via a memory interconnect 325A-325D. Memory devices 326A-326D can use any graphics memory technology. For example, memory devices 326A-326D may be Graphics Double Data Rate (GDDR) memories. Memory devices 326A-326D are, in one embodiment, High Bandwidth Memory (HBM) modules that can be on-die with their respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stacked memory devices that can be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, as described in further detail in FIGS. 11B-11D, each graphics engine tile 310A-310D and associated memory 326A-326D reside on a separate chiplet (chiplet) that is bonded to a base die or base substrate.

Graphics processing engine cluster 322 can be connected with on-chip or on-package fabric interconnect 324. The fabric interconnect 324 can enable communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more replication engines 304. The replication engine 304 can be used to move data out of, in, and between: memory devices 326A-326D and memory external to graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 may optionally contain a display controller 302 to enable connection with an external display device 318. The graphics processor may also be configured as a graphics or compute accelerator. In an accelerator configuration, the display controller 302 and the display device 318 may be omitted.

The graphics processor 320 is capable of connecting to a host system via a host interface 328. The host interface 328 can enable communication between the graphics processor 320, system memory, and/or other system components. The host interface 328 can be, for example, a PCI express bus or another type of host system interface.

FIG. 3C illustrates a computation accelerator 330 according to embodiments described herein. The compute accelerator 330 can contain architectural similarities to the graphics processor 320 of fig. 3B and is optimized for compute acceleration. The compute engine cluster 332 can include a set of compute engine tiles 340A-340D that include execution logic optimized for parallel or vector-based general purpose compute operations. In some embodiments, the compute engine tiles 340A-340D do not include fixed function graphics processing logic, although in one embodiment, one or more of the compute engine tiles 340A-340D can include logic to perform media acceleration. The compute engine tiles 340A-340D can be connected to the memories 326A-326D via the memory interconnects 325A-325D. The memories 326A-326D and the memory interconnects 325A-325D may be of similar technology as in the graphics processor 320, or can be different. The graphics compute engine tiles 340A-340D can also be interconnected via a set of tile interconnects 323A-323F, and may be connected with the fabric 324 and/or interconnected by the fabric interconnect 324. In one embodiment, the compute accelerator 330 contains a large L3 cache 336 that can be configured as a device-wide cache. The compute accelerator 330 can also be connected to a host processor and memory via a host interface 328 in a similar manner as the graphics processor 320 of FIG. 3B.

Graphics processing engine

FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor, according to some embodiments. In one embodiment, the Graphics Processing Engine (GPE)410 is a version of the GPE 310 shown in FIG. 3A, and may also represent the graphics engine tiles 310A-310D of FIG. 3B. The elements of fig. 4 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and the media pipeline 316 of fig. 3A are illustrated. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly contained within the GPE 410. For example and in at least one embodiment, a separate media and/or image processor is coupled to GPE 410.

In some embodiments, GPE 410 is coupled with or includes command streamer 403 that provides a command stream to 3D pipeline 312 and/or media pipeline 316. In some embodiments, command streamer 403 is coupled with a memory, which can be a system memory, or one or more of an internal cache and a shared cache. In some embodiments, command streamer 403 receives commands from memory and sends the commands to 3D pipeline 312 and/or media pipeline 316. The command is an indication (direct) obtained from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer can additionally contain a batch command buffer that stores a batch of multiple commands. Commands for 3D pipeline 312 can also contain references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 312 and/or image data and memory objects for media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, graphics core array 414 contains one or more blocks of graphics cores (e.g., graphics core(s) 415A, graphics core(s) 415B), each block containing one or more graphics cores. Each graphics core includes: a set of graphics execution resources containing general purpose and graphics specific execution logic to perform graphics and computational operations; and fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments, 3D pipeline 312 can include fixed functionality and programmable logic to process one or more shader programs (such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs) by processing instructions and dispatching threads of execution to graphics core array 414. Graphics core array 414 provides a uniform block of execution resources for use in processing these shader programs. Multipurpose execution logic (e.g., execution units) within graphics core(s) 415A-415B of graphics core array 414 include support for various 3D API shader languages and are capable of executing multiple simultaneous execution threads associated with multiple shaders.

In some embodiments, graphics core array 414 contains execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution unit contains general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic is capable of performing processing operations in parallel or in conjunction with the general purpose logic within the processor core(s) 107 of fig. 1 or cores 202A-202N as in fig. 2A.

Output data generated by threads executing on graphics core array 414 can output the data to memory in Unified Return Buffer (URB) 418. The URB418 is capable of storing data for multiple threads. In some embodiments, the URB418 may be used to send data between different threads executing on the graphics core array 414. In some embodiments, the URB418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic 420.

In some embodiments, the graphics core array 414 is scalable such that the array contains a variable number of graphics cores each having a variable number of execution units based on the target power and performance level of the GPE 410. In one embodiment, the execution resources are dynamically scalable such that the execution resources may be enabled or disabled as needed.

Graphics core array 414 is coupled to shared function logic 420, where shared function logic 420 comprises a plurality of resources shared between graphics cores in the graphics core array. The shared function within shared function logic 420 is a hardware logic unit that provides dedicated supplemental functionality to graphics core array 414. In various embodiments, shared function logic 420 includes, but is not limited to, sampler logic 421, math logic 422, and inter-thread communication (ITC) logic 423. Additionally, some embodiments implement one or more caches 425 within shared function logic 420.

Shared functionality is implemented, at least in cases where the demand for a given dedicated function is not sufficient for inclusion within graphics core array 414. Rather, the individual instantiations of the specialized function are implemented as separate entities within shared function logic 420 and are shared among the execution resources within graphics core array 414. The exact set of functions shared within graphics core array 414 and contained within graphics core array 414 varies across embodiments. In some embodiments, certain shared functions within shared function logic 420 that are widely used by graphics core array 414 may be included within shared function logic 416 within graphics core array 414. In various embodiments, shared function logic 416 within graphics core array 414 can include some or all of the logic within shared function logic 420. In one embodiment, all logic elements within shared function logic 420 may be duplicated within shared function logic 416 of graphics core array 414. In one embodiment, shared function logic 420 is eliminated in favor of shared function logic 416 within graphics core array 414.

Execution unit

5A-5B illustrate thread execution logic 500 including an array of processing elements employed in a graphics processor core according to embodiments described herein. The elements of fig. 5A-5B having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. 5A-5B illustrate an overview of thread execution logic 500, which thread execution logic 500 may represent hardware logic illustrated with each of the sub-cores 221A-221F of FIG. 2B. FIG. 5A represents an execution unit within a general purpose graphics processor, while FIG. 5B represents an execution unit that may be used within a compute accelerator.

As illustrated in fig. 5A, in some embodiments, thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including a plurality of execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable array of execution units is capable of being dynamically scaled by enabling or disabling one or more execution units (e.g., any of

execution units

508A, 508B, 508C, 508D through 508N-1 and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnection fabric linked to each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to memory (such as system memory or cache memory) through one or more of the instruction cache 506, data port 514, sampler 510, and execution unit arrays 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a separately programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

In some embodiments, the EUs 508A-508N are primarily used to execute shader programs. Shader processor 502 is capable of processing various shader programs and dispatching threads of execution associated with the shader programs via thread dispatcher 504. In one embodiment, the thread dispatcher contains logic to arbitrate initiation requests from threads of the graphics and media pipeline and to instantiate the requested threads on one or more of the execution units 508A-508N. For example, the geometry pipeline can dispatch vertices, tessellations (tessellation), or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 504 is also capable of processing runtime thread-derived requests from shader programs that are executing.

In some embodiments, execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single-instruction multiple-data (SIMD) execution, and multi-threading enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. Execution is a multiple issue per clock for pipelines that can perform integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from one of the memory or shared functions, dependency logic within the execution units 508A-508N causes the waiting threads to sleep until the requested data has been returned. While the waiting thread is sleeping, the hardware resources may be dedicated to processing other threads. For example, during a delay associated with vertex shader operations, the execution unit is able to perform operations for a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader). Various embodiments can be applied to: execution is used by using Single Instruction Multiple Threads (SIMT) as an alternative to or in addition to using SIMD. References to SIMD cores or operations can also be applied to SIMT or to SIMD combined with SIMT.

Each of the execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for the instruction. An execution channel is a logical unit for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 508A-508N support both integer and floating point data types.

The execution unit instruction set includes SIMD instructions. Various data elements can be stored as packed data types in registers, and execution units will process the various elements based on their data sizes. For example, in operating on a 256-bit wide vector, 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 54-bit packed data elements (four word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

In one embodiment, one or more execution units can be combined into a fused execution unit 509A-509N having thread control logic (507A-507N) that is common to the fused EU. Multiple EUs can be fused into EU groups. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group can vary according to the embodiment. In addition, various SIMD widths can be performed per EU, including but not limited to SIMD8, SIMD16, and SIMD 32. Each fused graphics execution unit 509A-509N contains at least two execution units. For example, the converged execution unit 509A includes a first EU 508A, a second EU 508B and thread control logic 507A, the thread control logic 507A being common to the first EU 508A and the second EU 508B. Thread control logic 507A controls the threads executing on the fused graphics execution unit 509A, allowing each EU within the fused execution units 509A-509N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executing on the execution logic 500 are also capable of storing explicitly managed data in the shared local memory 511. In some embodiments, sampler 510 is included to provide texture samples for 3D operations and media samples for media operations. In some embodiments, sampler 510 contains dedicated texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 500 via thread spawn and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 502 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader computes values for various vertex attributes to be interpolated across rasterized objects. In some embodiments, pixel processor logic within shader processor 502 then executes an Application Programming Interface (API) supplied pixel or fragment shader program. To execute shader programs, shader processor 502 dispatches threads to execution units (e.g., 508A) via thread dispatcher 504. In some embodiments, shader processor 502 uses texture sampling logic in sampler 510 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric segment, or discard one or more pixels without further processing.

In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

In one embodiment, the execution logic 500 can also include a ray tracker 505, the ray tracker 505 being capable of providing ray tracing acceleration functionality. The ray tracker 505 is capable of supporting a ray tracing instruction set containing instructions/functions for ray generation. The ray trace instruction set can be similar to or different from the ray trace instruction set supported by the ray trace core 245 in fig. 2C.

Fig. 5B illustrates exemplary internal details of the execution unit 508 according to an embodiment. The graphics execution unit 508 can include an instruction fetch unit 537, a general register file array (GRF)524, an architectural register file Array (ARF)526, a thread arbiter 522, a send unit 530, a branch unit 532, a set of SIMD Floating Point Units (FPUs) 534, and in one embodiment, a set of dedicated integer SIMD ALUs 535. The GRF 524 and ARF526 contain a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that may be active in the graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in the ARF526, while data used during thread execution is stored in the GRF 524. The execution state of each thread (containing the instruction pointer for each thread) can be maintained in thread specific registers in the ARF 526.

In one embodiment, the graphics execution unit 508 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the number of registers per execution unit and the target number of simultaneous threads, where execution unit resources are partitioned across logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

In one embodiment, the graphics execution unit 508 is capable of collectively issuing multiple instructions, which may each be different instructions. The thread arbiter 522 of the graphics execution unit thread 508 is capable of dispatching instructions to one of the issue unit 530, branch unit 532, or SIMD FPU(s) 534 for execution. Each execution thread can access 128 general purpose registers within the GRF524, where each register can store 32 bytes, which 32 bytes are accessible as a SIMD 8 element vector of 32-bit data elements. In one embodiment, each execution unit thread may access 4 kilobytes within GRF524, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In one embodiment, the graphics execution unit 508 is partitioned into seven hardware threads that are capable of independently performing computational operations, although the number of threads per execution unit can also vary depending on the embodiment. For example, up to 16 hardware threads are supported in one embodiment. In an embodiment where seven threads have access to 4 kilobytes, the GRF524 is capable of storing a total of 28 kilobytes. In the case where 16 threads have access to 4 kilobytes, the GRF524 is able to store a total of 64 kilobytes. The flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or to represent a strided rectangular block data structure.

In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via a "send" instruction executed by the messaging transmit unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

In one embodiment, graphics execution unit 508 includes one or more SIMD floating-point units ((one or more) FPUs) 534 to perform floating-point operations. In one embodiment, FPU(s) 534 also support integer computations. In one embodiment, FPU(s) 534 are capable of performing up to M32-bit floating point (or integer) operations on SIMD's, or up to 2M 16-bit integer or 16-bit floating point operations on SIMD's. In one embodiment, at least one of the FPU(s) provides extended mathematical capabilities to support high throughput transcendental mathematical functions and double precision 54-bit floating point. In some embodiments, there is also a set of 8-bit integer SIMD ALUs 535, and the set of 8-bit integer SIMD ALUs 535 may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, an array of multiple instances of graphics execution unit 508 can be instantiated in a graphics sub-core grouping (e.g., a subslice). For scalability, the product architect can select the exact number of execution units per sub-core grouping. In one embodiment, execution unit 508 is capable of executing instructions across multiple execution lanes. In further embodiments, each thread executing on the graphics execution unit 508 is executed on a different channel.

Fig. 6 illustrates a further execution unit 600 according to an embodiment. Execution unit 600 may be a compute optimized execution unit for use, for example, in compute engine tiles 340A-340D as in fig. 3C, but is not so limited. Variations of the execution unit 600 may also be used in the graphics engine tiles 310A-310D as in fig. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch/pre-fetch unit 603, and an instruction decode unit 604. The execution unit 600 additionally includes a register file 606, the register file 606 storing registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally comprises a dispatch unit 607 and a branch unit 608. In one embodiment, the dispatch unit 607 and branch unit 608 can operate similarly to the dispatch unit 530 and branch unit 532 of the graphics execution unit 508 of FIG. 5B.

The execution unit 600 also comprises a calculation unit 610, said calculation unit 610 comprising a plurality of different types of functional units. In one embodiment, compute unit 610 includes an ALU unit 611, the ALU unit 611 including an array of arithmetic logic units. ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. Integer and floating point operations may be performed simultaneously. The computing unit 610 can also include a systolic array 612 and a math unit 613. Systolic array 612 contains a network of width W and depth D of data processing elements that can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, systolic array 612 supports 16-bit floating point operations and 8-bit and 4-bit integer operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, systolic array 612 can be configured with support for the bfoat 16 bit floating point format. In one embodiment, math unit 613 can be included to perform a particular subset of math operations in an efficient and less powerful manner than ALU unit 611. Math unit 613 can contain variations of math logic that can be found in the shared function logic of graphics processing engines provided by other embodiments (e.g., math logic 422 of shared function logic 420 of FIG. 4). In one embodiment, the math unit 613 can be configured to perform 32-bit and 64-bit floating point operations.

Thread control unit 601 contains logic to control the execution of threads within execution units. Thread control unit 601 can contain thread arbitration logic to start, stop, and preempt execution of threads within execution unit 600. The thread state unit 602 can be used to store thread states for threads assigned to execute on the execution unit 600. Storing thread states within execution unit 600 enables fast preemption of threads when those threads become blocked or idle. The instruction fetch/pre-fetch unit 603 is capable of fetching instructions from an instruction cache of higher level execution logic (e.g., as instruction cache 506 in fig. 5A). The instruction fetch/prefetch unit 603 is also capable of issuing a prefetch request for instructions to be loaded into the instruction cache based on an analysis of the currently executing threads. Instruction decode unit 604 can be used to decode instructions to be executed by a compute unit. In one embodiment, the instruction decode unit 604 can be used as a secondary decoder to decode complex instructions into constituent micro-operations.

The execution unit 600 additionally contains a register file 606 that can be used by hardware threads executing on the execution unit 600. The registers in register file 606 can be partitioned across logic used to execute multiple simultaneous threads within compute unit 610 of execution unit 600. The number of logical threads that can be executed by the graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 606 can vary across embodiments based on the number of hardware threads supported. In one embodiment, register renaming may be used to dynamically allocate registers to hardware threads.

Fig. 7 is a block diagram illustrating a graphics processor instruction format 700, according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set with instructions in multiple formats. The solid box illustrates components that are typically contained in execution unit instructions, while the dashed box contains components that are optional or contained only in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated is a macro-instruction because they are instructions supplied to the execution units, as opposed to micro-operations that result from instruction decoding once the instruction is processed.

In some embodiments, the graphics processor execution unit natively supports instructions in the 128-bit instruction format 710. Based on the selected instruction, instruction options, and number of operands, a 64-bit compact instruction format 730 may be used for some instructions. The native 128-bit instruction format 710 provides access to all instruction options, while in the 64-bit format 730 some options and operations are restricted. The available native instructions in the 64-bit format 730 vary from embodiment to embodiment. In some embodiments, the instructions are compressed in part using a set of index values in the index field 713. The execution unit hardware references a set of compression tables based on the index values and uses the compression table outputs to reconstruct native instructions in the 128-bit instruction format 710. Other sizes and formats of instructions can be used.

For each format, instruction opcode 712 defines the operation to be performed by the execution unit. An execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data lanes of operands. In some embodiments, instruction control field 714 enables control of certain execution options such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions that employ the 128-bit instruction format 710, the execution size field 716 limits the number of data lanes to be executed in parallel. In some embodiments, the execution size field 716 is not available for use in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands, including two source operands, src0720, src 1722, and one destination 718. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. The data manipulation instruction can have a third source operand (e.g., SRC 2724), where the instruction opcode 712 determines the number of source operands. The last source operand of the instruction can be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, 128-bit instruction format 710 contains an access/address mode field 726, the access/address mode field 726 specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When using the direct register addressing mode, the register address of one or more operands is provided directly by bits in the instruction.

In some embodiments, 128-bit instruction format 710 contains an access/address mode field 726, the access/address mode field 726 specifying an address mode and/or an access mode of the instruction. In one embodiment, an access pattern is used to define the data access alignment of an instruction. Some embodiments support access patterns that include 16 byte aligned access patterns and 1 byte aligned access patterns, where the byte alignment of the access patterns determines the access alignment of the instruction operands. For example, when in the first mode, the instruction may use byte aligned addressing for the source operand and the destination operand, and when in the second mode, the instruction may use 16 byte aligned addressing for all of the source operand and the destination operand.

In one embodiment, the address mode portion of the access/address mode field 726 determines whether the instruction will use direct addressing or indirect addressing. When using the direct register addressing mode, bits in the instruction directly provide the register address of one or more operands. When using the indirect register addressing mode, register addresses for one or more operands may be calculated based on an address register value and an address immediate field in the instruction.

In some embodiments, instructions are grouped based on opcode 712 bit fields to simplify opcode decoding 740. For an 8-bit opcode,

bits

4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode groupings shown are examples only. In some embodiments, the move and logical opcode group 742 includes data move and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logical group 742 share five Most Significant Bits (MSBs), with a move (mov) instruction taking the form 0000 xxxxxxb and a logical instruction taking the form 0001 xxxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions in the form of 0010 xxxxxxb (e.g., 0x 20). The miscellaneous instruction group 746 includes a mix of instructions, including synchronous instructions (e.g., wait, send) in the form of 0011 xxxxxxb (e.g., 0x 30). The parallel mathematical instruction group 748 includes per-component arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100 xxxxxxb (e.g., 0x 40). The parallel math group 748 performs arithmetic operations in parallel across the data channels. Vector math group 750 includes arithmetic instructions (e.g., dp4) in the form 0101xxxxb (e.g., 0x 50). Vector math groups perform arithmetic such as dot product calculations on vector operands. The illustrated opcode decoding 740 can be used in one embodiment to determine which portion of the execution unit will be used to execute the decoded instruction. For example, some instructions may be designated as systolic instructions to be executed by the systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to ray tracing cores or ray tracing logic within a slice or partition of execution logic.

Graphics pipeline

Fig. 8 is a block diagram of another embodiment of a graphics processor 800. The elements of fig. 8 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 800 includes geometry pipeline 820, media pipeline 830, display engine 840, thread execution logic 850, and render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 800 over the ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general purpose processors. Commands from the ring interconnect 802 are interpreted by a command streamer 803, which command streamer 803 supplies instructions to the various components of the geometry pipeline 820 or media pipeline 830.

In some embodiments, the command streamer 803 directs the operation of a vertex fetcher 805, which vertex fetcher 805 reads the vertex data from memory and executes the vertex processing commands provided by the command streamer 803. In some embodiments, vertex fetcher 805 provides vertex data to vertex shader 807, which vertex shader 807 performs coordinate space transformations and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

In some embodiments, execution units 852A-852B are an array of vector processors having sets of instructions for performing graphics and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851, the L1 cache 851 being specific to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 820 includes a tessellation component to perform hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader (programmable hull shader)811 configures the tessellation operations. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellator 813 operates under the direction of the hull shader 811 and contains dedicated logic to generate a detailed set of geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, tessellation components (e.g., hull shader 811, tessellator 813, and domain shader 817) can be bypassed if tessellation is not used.

In some embodiments, a full geometry object can be processed by the geometry shader 819 via one or more threads assigned to the execution units 852A-852B, or can travel directly to a clipper 829. In some embodiments, the geometry shader operates on the entire geometry object, rather than on vertices or patches of vertices (patches) as in previous stages of the graphics pipeline. If tessellation is disabled, geometry shader 819 receives input from vertex shader 807. In some embodiments, the geometry shader 819 may be programmed by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

Before rasterization, the clipper 829 processes the vertex data. The clipper 829 may be a programmable clipper or a fixed function clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert the geometric objects into a pixel-by-pixel representation. In some embodiments, pixel shader logic is included in thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the un-rasterized vertex data via the stream output unit 823.

Graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between the main components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data ports 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, sampler 854,

caches

851, 858 and execution units 852A-852B each have separate memory access paths. In one embodiment, the texture cache 858 can also be configured as a sampler cache.

In some embodiments, the rendering output pipeline 870 contains a rasterizer and depth test component 873 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower (window)/masker unit to perform fixed function triangle and line rasterization. An associated render cache 878 and depth cache 879 may also be available in some embodiments. The pixel operations component 877 performs pixel-based operations on the data, although in some examples, pixel operations associated with 2D operations (e.g., bitmap transfer with blending) are performed by the 2D engine 841 or replaced by the display controller 843 when displaying with an overlay display plane. In some embodiments, shared L3 cache 875 is available to all graphics components, allowing data to be shared without using main system memory.

In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, video front end 834 receives pipeline commands from command streamer 803. In some embodiments, media pipeline 830 contains a separate command streamer. In some embodiments, the video front end 834 processes media commands before sending the commands to the media engine 837. In some embodiments, media engine 837 includes thread spawning functionality to spawn threads for dispatch to thread execution logic 850 via thread dispatcher 831.

In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and is coupled with the graphics processor via ring interconnect 802 or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 contains dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled with a display device (not shown), which may be a system-integrated display device (as in a laptop computer) or may be an external display device attached via a display device connector.

In some embodiments, geometry pipeline 820 and media pipeline 830 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one Application Programming Interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for an open graphics library (OpenGL), open computing language (OpenCL), and/or Vulkan graphics and computing APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from microsoft corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for an open source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping from the pipeline of the future API to the pipeline of the graphics processor can be made.

Graphics pipeline programming

FIG. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence 910, according to an embodiment. The solid line block diagram in FIG. 9A illustrates components that are typically included in graphics commands, while the dashed line includes components that are optional or included only in a subset of graphics commands. The exemplary graphics processor command format 900 of FIG. 9A contains data fields to identify the client 902, command operation code (opcode) 904, and data 906 of the command. Some commands also include a sub-opcode 905 and a command size 908.

In some embodiments, the client 902 specifies a client unit of the graphics device that processes command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes commands. Once the client unit receives the command, the client unit reads the operation code 904 and the sub-operation code 905 (if the sub-operation code 905 is present) to determine the operation to perform. The client unit uses the information in data field 906 to execute the command. For some commands, an explicit command size 908 is contemplated to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands based on the command opcode. In some embodiments, the commands are aligned via multiples of a doubleword. Other command formats can be used.

The flowchart in FIG. 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, the software or firmware of the data processing system that features embodiments of the graphics processor uses the version of the command sequence shown to set, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for purposes of example only, as embodiments are not limited to these particular commands or this sequence of commands. Additionally, the commands may be issued as batch commands in a command sequence such that the graphics processor will process the sequence of commands at least partially concurrently.

In some embodiments, graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipeline to complete the current pending commands of the pipeline. In some embodiments, 3D pipeline 922 and media pipeline 924 do not operate concurrently. The execution pipeline flushes to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active drawing engine completes pending operations and the associated read cache fails. Alternatively, any data in the render cache marked as dirty can be flushed to memory. In some embodiments, the pipeline flush command 912 can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some embodiments, the pipeline select command 913 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is required only once within the execution context before issuing the pipeline command unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is required immediately prior to a pipeline switch via a pipeline select command 913.

In some embodiments, pipeline control commands 914 configure the graphics pipeline for operation and are used to program 3D pipeline 922 and media pipeline 924. In some embodiments, the pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, the pipeline control command 914 is used for pipeline synchronization and to flush data from one or more caches within the active pipeline before processing a batch of commands.

In some embodiments, the return buffer status command 916 is used to configure a set of return buffers for the respective pipeline to write data. Some pipelining operations require allocation, selection, or configuration of one or more return buffers to which these operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communications. In some embodiments, return buffer status 916 includes selecting the size and number of return buffers to be used for a set of pipelining operations.

The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on the pipeline determination 920, the command sequence is customized to either the 3D pipeline 922, which starts in a 3D pipeline state 930, or the media pipeline 924, which starts in a media pipeline state 940.

The commands used to configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured before processing the 3D primitive commands. The values of these commands are determined based at least in part on the particular 3D API in use. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those elements are not to be used.

In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. Commands and associated parameters passed to the graphics processor via the 3D primitive 932 commands are forwarded to vertex fetch functions in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate the vertex data structure. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive 932 commands are used to perform vertex operations on 3D primitives via a vertex shader. To process the vertex shader, 3D pipeline 922 dispatches shader execution threads to the graphics processor execution unit.

In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, the register write triggers the command execution. In some embodiments, execution is triggered via a "go" or "kick" command in the command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a sequence of commands through a graphics pipeline. The 3D pipeline will perform geometric processing for the 3D primitives. Once the operation is complete, the resulting geometric object is rasterized and the pixel engine colors the resulting pixels. For those operations, additional commands to control pixel shading and pixel back-end operations may also be included.

In some embodiments, graphics processor command sequence 910 follows the path of media pipeline 924 when performing media operations. In general, the particular use and programming approach for media pipeline 924 depends on the media or computing operation to be performed. Certain media decoding operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline can also be bypassed and media decoding can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for General Purpose Graphics Processor Unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similar manner as 3D pipeline 922. A set of commands to configure the media pipeline state 940 is dispatched or placed into a command queue prior to the media object command 942. In some embodiments, the commands for the media pipeline state 940 contain data to configure the media pipeline elements that will be used to process the media object. This contains data, such as encoding and decoding formats, used to configure the video decoding and video encoding logic within the media pipeline. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements containing a collection of state settings.

In some embodiments, media object command 942 supplies a pointer to a media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all of the media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or equivalent execute event (e.g., a register write). The output from media pipeline 924 may then be post-processed by operations provided by 3D pipeline 922 or media pipeline 924. In some embodiments, GPGPU operations are configured and performed in a similar manner as media operations.

Graphics software architecture

FIG. 10 illustrates an exemplary graphics software architecture for data processing system 1000 in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes a graphics processor 1032 and one or more general purpose processor cores 1034. Graphics application 1010 and operating system 1020 each execute in system memory 1050 of the data processing system.

In some embodiments, 3D graphics application 1010 contains one or more shader programs, including shader instructions 1012. The shader language instructions may be in a high level shader language, such as High Level Shader Language (HLSL) or OpenGL shader language (GLSL) of Direct3D, and so forth. The application also includes executable instructions 1014 in a machine language suitable for execution by the general purpose processor core 1034. The application also contains a graphical object 1016 defined by the vertex data.

In some embodiments, operating system 1020 is from Microsoft corporation

An operating system, a proprietary UNIX-like operating system, or an open source UNIX-like operating system that uses a variant of the Linux kernel. The operating system 1020 can support a graphics API1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system 1020 will employ H using the front-end shader compiler 1024 Any shader instructions 1012 of the LSL are compiled into a lower-level shader language. The compilation may be just-in-time (JIT) compilation or the application may be able to perform shader precompilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-end shader compiler 1027 to convert shader instructions 1012 into a hardware-specific representation. The OpenGL API, when in use, passes shader instructions 1012 in the GLSL high-level language to user-mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with the kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions.

IP check cash

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may contain instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic to perform the techniques described herein. Such a representation, referred to as an "IP core," is a reusable unit of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model on fabrication machines that manufacture integrated circuits. An integrated circuit may be fabricated such that the circuit performs the operations described in association with any of the embodiments described herein.

Fig. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate integrated circuits to perform operations, according to an embodiment. The IP core development system 1100 may be used to generate a modular, reusable design that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). Design facility 1130 is capable of generating software simulations 1110 of IP core designs in a high-level programming language (e.g., C/C + +). Software simulation 1110 can be used to design, test, and verify the behavior of an IP core using simulation model 1112. Simulation model 1112 may contain functional, behavioral, and/or timing simulations. Register Transfer Level (RTL) design 1115 can then be created or synthesized from simulation model 1112. RTL design 1115 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to RTL design 1115, lower level designs at the logic level or transistor level may be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may differ.

The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120, which hardware model 1120 may employ a Hardware Description Language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. Non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to third party fabrication facility 1165. Alternatively, the IP core design may be communicated over a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). Fabrication facility 1165 may then fabricate an integrated circuit based at least in part on the IP core design. The integrated circuit fabricated can be configured to perform operations according to at least one embodiment described herein.

Fig. 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 1170 includes a plurality of

hardware logic units

1172, 1174 connected to a substrate 1180. The

logic

1172, 1174 may be implemented at least partially in configurable logic or fixed functionality logic hardware, and can contain one or more portions of any of the processor core(s), graphics processor(s), or other accelerator device described herein. Each

logic unit

1172, 1174 can be implemented within a semiconductor die and coupled with a substrate 1180 via an interconnect 1173. Interconnect structure 1173 may be configured to route electrical signals between

logic

1172, 1174 and substrate 1180, and can include interconnects such as, but not limited to, bumps or posts. In some embodiments, the interconnect fabric 1173 may be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the

logic

1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may comprise other suitable types of substrates. The package assembly 1170 can be connected to other electrical devices via a package interconnect 1183. Package interconnect 1183 may be coupled to a surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or a multi-chip module.

In some embodiments, the

logic units

1172, 1174 are electrically coupled with a bridge 1182, the bridge 1182 configured to route electrical signals between the

logics

1172, 1174. The bridge 1182 may be a dense interconnect structure that provides routing (route) for electrical signals. The bridge 1182 may comprise a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the

logics

1172, 1174.

Although two

logic units

1172, 1174 and a bridge 1182 are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. Since the bridge 1182 may be excluded when logic is contained on a single die, one or more dies may be connected through zero or more bridges. Alternatively, multiple dies or logic units can be connected by one or more bridges. Additionally, multiple logic cells, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

Fig. 11C illustrates a package assembly 1190 including a plurality of hardware logic chiplet units connected to a substrate 1180 (e.g., base die). A graphics processing unit, parallel processor, and/or compute accelerator as described herein can be constructed from a multiplicity of silicon chiplets that are individually fabricated. In this context, a chiplet is an at least partially packaged integrated circuit containing different logic units that can be assembled into a larger package than other chiplets. A diverse set of chiplets with different IP core logic can be assembled into a single device. In addition, the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. Different process technologies can be used to manufacture and build the IP core during manufacturing, which avoids the complexity of converging multiple IPs (especially on large socs with several feature (colors) IPs) to the same manufacturing process. Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to create multiple product SKUs. In addition, disaggregated IP is easier to power gate independently, and components that are not in use on a given workload can be powered down, thereby reducing overall power consumption.

The hardware logic chiplets can include dedicated hardware logic chiplets 1172, logic or I/O chiplets 1174, and/or memory chiplets 1175. Hardware logic chiplet 1172 and logic or I/O chiplets 1174 can be implemented at least in part in configurable logic or fixed functionality logic hardware and can contain one or more portions of any of the processor core(s), graphics processor(s), parallel processor(s), or other accelerator devices described herein. The memory chiplets 1175 can be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

Each chiplet can be fabricated as a separate semiconductor die and coupled to the substrate 1180 via interconnect structures 1173. Interconnect structure 1173 can be configured to route electrical signals between the various chiplets and logic within substrate 1180. Interconnect structure 1173 can include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect fabric 1173 may be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of logic, I/O, and memory chiplets.

In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may comprise other suitable types of substrates. The package assembly 1190 can be connected to other electrical devices via a package interconnect 1183. Package interconnect 1183 may be coupled to a surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or a multi-chip module.

In some embodiments, logic or I/O chiplet 1174 and memory chiplet 1175 can be electrically coupled via a bridge 1187, the bridge 1187 configured to route electrical signals between logic or I/O chiplet 1174 and memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides routing for electrical signals. The bridge 1187 may comprise a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide chip-to-chip connections between the logic or I/O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, in some embodiments, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB). In some embodiments, bridge 1187 may simply be a direct connection from one chiplet to another chiplet.

The substrate 1180 can include hardware components for the I/O1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 can be embedded in substrate 1180 to enable communication between various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I/O1191, fabric 1185, cache, bridges, and other hardware logic 1193 can be integrated into a base die that is stacked on top of substrate 1180.

In various embodiments, package assembly 1190 can contain a fewer or greater number of components and chiplets interconnected by fabric 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 can be arranged in a 3D or 2.5D arrangement. In general, bridge structure 1187 may be used to facilitate point-to-point interconnections between, for example, logic or I/O chiplets and memory chiplets. Fabric 1185 can be used to interconnect various logic and/or I/O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and/or I/O chiplets. In one embodiment, the in-substrate cache 1192 can act as a global cache for the package assembly 1190, part of a distributed global cache, or as a private cache for the fabric 1185.

FIG. 11D illustrates a packaged assembly 1194 including interchangeable chiplets 1195 according to an embodiment. The interchangeable chiplets 1195 can be assembled into standardized slots on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which bridge 1197 interconnect can be similar to other bridge interconnects described herein and can be, for example, an EMIB. The memory chiplets can also be connected to logic or I/O chiplets via bridge interconnects. The I/O and logic chiplets are capable of communicating via the interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I/O or memory/cache.

In one embodiment, the SRAM and power delivery circuitry can be fabricated into one or more of the

base chiplets

1196, 1198, which base chiplets 1196, 1198 can be fabricated using a different process technology relative to the interchangeable chiplets 1195 stacked on top of the base chiplets. For example, the

base chiplets

1196, 1198 can be made using larger process technologies, while the interchangeable chiplets can be made using smaller process technologies. One or more of the interchangeable chiplets 1195 can be memory (e.g., DRAM) chiplets. Different memory densities can be selected for the packaged assembly 1194 based on the power and/or performance that is the target of the product in which the packaged assembly 1194 is used. In addition, logic chiplets with different numbers of types of functional units can be selected at assembly based on the power and/or performance targeted for the product. In addition, chiplets containing different types of IP logic cores can be inserted into interchangeable chiplet slots, enabling hybrid processor designs that can mix and match different technology IP blocks.

Exemplary System-on-chip Integrated Circuit

Fig. 12-13 illustrate an example integrated circuit and associated graphics processor that may be fabricated using one or more IP cores according to various embodiments described herein. Other logic and circuitry may be included in addition to those illustrated, including additional graphics processor/cores, peripheral interface controllers, or general purpose processor cores.

Fig. 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and/or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. Integrated circuit 1200 includes peripheral or bus logic including USB controller 1225, UART controller 1230, SPI/SDIO controller 1235, and I2S/I2C controller 1240. Additionally, the integrated circuit can include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industrial Processor Interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. A memory interface may be provided via the memory controller 1265 to access SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

Fig. 13-14 are block diagrams illustrating an exemplary graphics processor for use within a SoC, according to embodiments described herein. FIG. 13 illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 14 illustrates a further exemplary graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor 1310 of FIG. 13 is an example of a low power graphics processor core. Graphics processor 1340 of fig. 14 is an example of a higher performance graphics processor core. Each of the graphics processors 1310, 1340 can be a variation of the graphics processor 1210 of fig. 12.

As shown in FIG. 13, graphics processor 1310 contains a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D through 1315N-1 and 1315N). Graphics processor 1310 is capable of executing different shader programs via separate logic, such that vertex processor 1305 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. Vertex processor 1305 executes the vertex processing stages of the 3D graphics pipeline and generates primitive and vertex data. The fragment processor(s) 1315A-1315N use the primitives and vertex data generated by the vertex processor 1305 to produce a frame buffer for display on a display device. In one embodiment, fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

Graphics processor 1310 additionally includes one or more Memory Management Units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual address to physical address mapping for the graphics processor 1310 (including for the vertex processor 1305 and/or the fragment processor(s) 1315A-1315N), which may reference vertex or image/texture data stored in memory in addition to vertex or image/texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more of application processor 1205, image processor 1215, and/or video processor 1220 of FIG. 12, enabling each processor 1205-1220 to participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

As shown in FIG. 14, graphics processor 1340 includes one or more MMUs 1320A-1320B, cache(s) 1325A-1325B and circuit interconnect(s) 1330A-1330B of graphics processor 1310 of FIG. 13. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F through 1355N-1 and 1355N) that provide a unified shader core architecture in which a single core or type of core is capable of executing all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary between embodiments and implementations. In addition, the graphics processor 1340 includes: an inter-core task manager 1345, the inter-core task manager 1345 acting as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N; and a tiling unit (tilngunit) 1358 to accelerate tiling operations (tiling operation) for tile-based rendering in which rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage.

Ray tracing with machine learning

As mentioned above, ray tracing is a graphics processing technique in which light transmission is simulated by physics-based rendering. One of the key operations in ray tracing is to process visibility queries that require traversal and cross-testing of nodes in the bounding volume level (BVH).

Ray tracing and path tracing based techniques compute images by tracing rays and paths through each pixel and using random sampling to compute advanced effects such as shading, gloss, indirect lighting, etc. Using only a few samples is fast but produces noisy images, while using many samples produces high quality images but is cost prohibitive.

Over the past several years, a breakthrough solution for ray/path tracing for real-time use has emerged in the form of "denoising," which is a process of producing high-quality, filtered/denoised images from noisy, low-sample count inputs using image processing techniques. The most effective denoising techniques rely on machine learning techniques, where a machine learning engine learns how a noisy image would likely look if it had been computed with more samples. In one particular implementation, machine learning is performed by a Convolutional Neural Network (CNN); however, the underlying principles of the invention are not limited to CNN implementations. In such an implementation, the training data is generated with a low sample count input and true value data (ground-route). The CNN is trained to predict the converged pixel from a neighborhood of noisy pixel inputs around the pixel in question.

Although not perfect, this AI-based denoising technique has proven to be unexpectedly effective. However, note that good training data is required, since otherwise the network may predict erroneous results. For example, if an animated film studio trained a denoising CNN on a past film with a scene on land, and then attempted to denoise frames from a new film set on water using the trained CNN, the denoising operation would perform sub-optimally.

To address this issue, one embodiment of the present invention dynamically collects learning data while rendering and continuously trains a machine learning engine, such as a CNN, based on the data on which the machine learning engine is currently running, thereby continuously improving the machine learning engine for the task at hand. This embodiment may still perform the training phase before runtime, but continue to adjust the machine learning weights as needed during runtime. In addition, this embodiment avoids the high cost of computing the reference data required for training by limiting the generation of learning data to image sub-regions of each frame or every N frames. In particular, a noisy input of the frame is generated for denoising the full frame with the current network. In addition, as described below, small regions of reference pixels are generated and used for continuous training.

While CNN implementations are described with respect to certain embodiments, any form of machine learning engine may be used, including but not limited to systems that perform the following operations: supervised learning (e.g., building a mathematical model of a dataset containing both inputs and desired outputs), unsupervised learning (e.g., which evaluates input data for certain types of structures), and/or a combination of supervised and unsupervised learning.

Existing denoising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined that receives a region of N × N pixels with various per-pixel data channels such as pixel color, depth, normal deviation, primitive ID, and albedo, and generates a final pixel color. A "representative" training data set is generated using a low sample count input equivalent to one frame, and with reference to the "expected" pixel color calculated with a very high sample count. The network is trained towards these inputs, generating a set of "ideal" weights for the network. In these implementations, the reference data is used to train the weights of the network to most closely match the output of the network to the desired result.

At run time, a given pre-computed ideal network weight is loaded and the network is initialized. For each frame, a low-sample count image of the denoised input is generated (i.e., the same as used for training). For each pixel, a given neighborhood of the input of the pixel is run through the network to predict the "denoised" pixel color, thereby generating a denoised frame.

FIG. 15 illustrates one embodiment of an initial training implementation. The machine learning engine 1500 (e.g., CNN) receives a region of N × N pixels as high sample count image data 1702 with various per-pixel data channels such as pixel color, depth, normal bias, primitive ID, and albedo, and generates a final pixel color. Representative training data is generated using a low sample count input 1501 equivalent to one frame. The network is trained towards these inputs, generating a set of "ideal" weights 1505, and the machine learning engine 1500 then denoises the low-sample count image at runtime using the set of "ideal" weights 1505.

To improve the above technique, one embodiment of the present invention adds a de-noising stage to generate new training data per frame or a subset of frames (e.g., every N frames, where N ═ 2, 3, 4, 10, 25, etc.). In particular, as shown in fig. 16, this embodiment selects one or more regions in each frame (referred to herein as "new reference regions" 1602), which new reference regions 1602 are rendered into a separate high sample count buffer 1604 at a high sample count. The low-sample-count buffer area 1603 stores the low-sample-count input frame 1601 (including the low-sample area 1604 corresponding to the new reference area 1602).

In one embodiment, the location of the new reference region 1602 is randomly selected. Alternatively, the location of the new reference region 1602 may be adjusted in a pre-specified manner for each new frame (e.g., using predefined movement of regions between frames, limited to a specified region in the center of a frame, etc.).

Regardless of how the new reference region is selected, it is used by the machine learning engine 1600 to continually refine and update the trained weights 1605 for denoising. In particular, the reference pixel color from each new reference region 1602 and the noisy reference pixel input from the corresponding low sample count region 1607 are rendered. Then, supplemental training is performed on the machine learning engine 1600 using the high sample count reference region 1602 and the corresponding low sample count region 1607. This training is performed continuously for each new reference region 1602 during runtime, as opposed to initial training, thereby ensuring that the machine learning engine 1600 is accurately trained. For example, a per-pixel data channel (e.g., pixel color, depth, normal bias, etc.) may be evaluated, and the machine learning engine 1600 adjusts the trained weights 1605 using the per-pixel data channel. As in the training case (fig. 15), the machine learning engine 1600 is trained towards a set of ideal weights 1605 for removing noise from the low sample count input frame 1601 to generate denoised frames 1620. However, in this embodiment, the trained weights 1605 are continually updated based on new image characteristics of the new type of low sample count input frame 1601.

In one embodiment, the retraining operations performed by machine learning engine 1600 are performed concurrently in a background process on a Graphics Processor Unit (GPU) or host processor. The rendering loop, which may be implemented as a driver component and/or a GPU hardware component, continuously generates new training data (e.g., in the form of new reference regions 1602), which the rendering loop places in a queue. The background training process executing on the GPU or host processor continuously reads new training data from the queue, retrains the machine learning engine 1600, and updates it with new weights 1605 at appropriate intervals.

Fig. 17 illustrates an example of one such implementation, where the background training process 1700 is implemented by the host CPU 1710. In particular, in this embodiment, the background training process 1700 uses the high sample count new reference region 1602 and the corresponding low sample region 1604 to continually update the trained weights 1605, thereby updating the machine learning engine 1600.

As shown in FIG. 18A, in one implementation, such as in a multiplayer online game, different host machines 1820 and 1822 individually generate reference regions that background training processes 1700A-C transmit to a server 1800 (such as a game server, for example). The server 1800 then performs training on the machine learning engine 1810 using the new reference regions received from each of the hosts 1821-1822, updating the weights 1805 as previously described. It communicates these weights 1805 to the host machine 1820 that stores the weights 1605A-C, thereby updating each individual machine learning engine (not shown). Because the server 1800 can be provided with a large number of reference areas in a short period of time, it is able to efficiently and accurately update the weights of any given application (e.g., online games) being executed by the user.

As shown in fig. 18B, a different host machine may generate new trained weights (e.g., based on the training/reference area 1602 as previously described) and share the new trained weights with a server 1800 (e.g., such as a game server), or alternatively use a peer-to-peer sharing protocol. A machine learning management component 1811 on the server generates a set of combining weights 1805 using the new weights received from each of the host machines. Combining weights 1805 may be, for example, averages generated from new weights and are continuously updated as described herein. Once generated, a copy of the combined weights 1605A-C can be transferred and stored on each of the host machines 1820-1821, which host machines 1820-1821 can then perform denoising operations using the combined weights as described herein.

In one embodiment, the semi-closed loop update mechanism can be used by a hardware manufacturer. For example, the reference network may be included as part of a driver distributed by a hardware manufacturer. When the driver generates new training data using the techniques described herein and continuously submits these new training data back to the hardware manufacturer, the hardware manufacturer uses this information to continue to improve its machine learning implementation for the next driver update.

In one implementation (e.g., in a batch movie rendered on a render farm), the renderer transmits the newly generated training area to a dedicated server or database (in the studio's render farm) that aggregates the data from multiple render nodes over time. Separate processes on separate machines continuously improve the studio's specialized denoising network, and new rendering jobs always use the latest trained network.

A method according to one embodiment of the invention is illustrated in fig. 19. The method may be implemented on the architecture described herein, but is not limited to any particular system or graphics processing architecture.

At 1901, low sample count image data and high sample count image data are generated for a plurality of image frames as part of an initial training phase. At 1902, a machine learning denoising engine is trained using high/low sample count image data. In one embodiment, for example, the set of convolutional neural network weights associated with the pixel features may be updated according to training. However, any machine learning architecture may be used.

At 1903, at run time, a low sample count image frame and at least one reference region having a high sample count are generated. At 1904, the high sample count reference region is used by the machine learning engine and/or separate training logic (e.g., background training module 1700) to continually improve training of the machine learning engine. For example, in one embodiment, a high sample count reference region is used in combination with a corresponding portion of a low sample count image to continue to teach the machine learning engine 1904 how to most efficiently perform denoising. In a CNN implementation, for example, this may involve updating the weights associated with the CNN.

Many variations of the above embodiments may be implemented, such as the manner in which feedback loops to the machine learning engine are configured; an entity that generates training data; feeding back the training data to the mode employed by the training engine; and how to provide the improved network to the rendering engine. In addition, although the above embodiments described above use a single reference region to perform continuous training, any number of reference regions may be used. Furthermore, as previously mentioned, the reference regions may have different sizes, may be used over different numbers of image frames, and may be positioned in different locations within the image frames using different techniques (e.g., randomly, according to a predetermined pattern, etc.).

Additionally, although a Convolutional Neural Network (CNN) is described as one example of machine learning engine 1600, the underlying principles of the invention may be implemented using any form of machine learning engine that is capable of continuously improving its results using new training data. By way of example and not limitation, other machine learning implementations include data processing Grouping Methods (GMDH), long short-term memory, deep pool computing (deepReservoir computing), deep belief networks, tensor deep Stacking networks, and deep predictive coding networks, to name a few.

Distributed denoising

As mentioned above, denoising has become a key feature for real-time ray tracing with smooth, noiseless images. Rendering can be done across a distributed system on multiple devices, but the denoising frameworks existing so far all operate on a single instance on a single machine. If rendering is performed across multiple devices, the devices may not have all of the rendered pixels accessible for use in computing the denoised portion of the image.

One embodiment of the present invention includes a distributed denoising algorithm that works with Artificial Intelligence (AI) -based and non-AI-based denoising techniques. Regions of the image have been distributed across nodes from distributed rendering operations, or partitioned and distributed from a single frame buffer. Ghost regions of the neighboring region required for computing sufficient denoising are collected from neighboring nodes as needed, and the resulting patches are composed into a final image.

Distributed processing

FIG. 20 illustrates an example of the present invention in which a plurality of nodes 2021 and 2023 perform rendering. Although only three nodes are illustrated for simplicity, the underlying principles of the invention are not limited to any particular number of nodes. Indeed, a single node may be used to implement some embodiments of the invention.

Nodes 2021 and 2023 each render a portion of the image, resulting in region 2011 and 2013 in this example. Although rectangular regions 2011 and 2013 are shown in fig. 20, any shape of region may be used and any device may be capable of handling any number of regions. The region required for the node to perform a sufficiently smooth denoising operation is referred to as ghost region 2001-2003. In other words, the ghost region 2001-2003 represents all the data required to perform denoising at a specified quality level. Reducing the quality level reduces the size of the required ghost regions and thus the amount of data required, and increasing the quality level increases the required ghost regions and corresponding data.

In one embodiment, if a node, such as node 2021, does have a local copy of a portion of the ghost region 2001 required to de-noise its region 2011 at a specified quality level, the node will retrieve the required data from one or more "neighboring" nodes, such as node 2022, which has a portion of the ghost region 2001 as illustrated. Similarly, if node 2022 does have a local copy of a portion of the ghost region 2002 required to de-noise its region 2012 at a specified quality level, node 2022 will retrieve the required ghost region data 2032 from node 2021. The fetching may be performed over a bus, an interconnect, a high-speed memory fabric, a network (e.g., high-speed ethernet), or may even be an on-chip interconnect in a multi-core chip that can distribute rendering work among multiple cores (e.g., for rendering large images at extreme resolutions or time varying). In one embodiment, each node 2021-2023 comprises a separate execution unit or a designated set of execution units within the graphics processor.

The particular amount of data to be transmitted depends on the denoising technique being used. Furthermore, the data from ghost regions may contain any data needed to improve denoising of each respective region. In one embodiment, for example, ghost region data includes image color/wavelength, intensity/alpha data, and/or normals. However, the underlying principles of the invention are not limited to any particular set of ghost region data.

Additional details of one embodiment

For slower networks or interconnects, the compression of this data can be exploited using existing general lossless or lossy compression. Examples include, but are not limited to, zlib, gzip, and Lempel-Ziv-Markov chain algorithms (LZMA). By noting that the delta of ray hit information between frames (delta) can be very sparse, further content specific compression can be used and only samples contributing to the delta need be sent when a node already has a collected delta from a previous frame. These can be selectively pushed to node i, which collects those samples, or node i can request samples from other nodes. In one embodiment, lossless compression is used for certain types of data and program code, while lossy data is used for other types of data.

FIG. 21 illustrates additional details of the interaction between nodes 2021 and 2022 according to one embodiment of the invention. Each node 2021-2022 includes ray trace rendering circuitry 2081-2082 for rendering a corresponding image region 2011-2012 and a ghosting region 2001-2002. The denoiser 2100 + 2111 performs denoising operations on the rendering and denoising regions 2011 + 2012 of each node 2021 + 2022, respectively. The denoiser 2021-2022 may comprise, for example, circuitry, software, or any combination thereof to generate the denoised regions 2121-2122, respectively. As mentioned, the denoiser 2021-2022 may need to rely on data within ghost regions owned by different nodes when generating denoised regions (e.g., the denoiser 2100 may need data from the ghost region 2002 owned by the node 2022).

Thus, in one embodiment, denoiser 2100-2111 uses data from regions 2011-2012 and ghosting region 2001-2002, respectively, to generate denoised region 2121-2122, at least a portion of which may be received from another node. As described herein, the area data manager 2101-2102 manages data transfer from the ghosting area 2001-2002. In one embodiment, the compressor/decompressor unit 2131-2132 performs compression and decompression, respectively, of the ghost region data exchanged between the nodes 2021-2022.

For example, the region data manager 2101 of the node 2021 may send data from the ghosted region 2001 upon request from the node 2022 to the compressor/decompressor 2131, which compressor/decompressor 2131 compresses the data to generate compressed data 2106 that it transmits to the node 2022, thereby reducing bandwidth over the interconnect, network, bus, or other data communication link. The compressor/decompressor 2132 of node 2022 then decompresses the compressed data 2106 and the denoiser 2111 uses the decompressed ghost data to generate a higher quality denoised region 2122 than would be possible with data from region 2012 only. The region data manager 2102 may store the decompressed data from shadow region 2001 in a cache, memory, register file, or other storage device to make it available to the de-noiser 2111 when generating de-noised region 2122. A similar set of operations may be performed to provide data from the ghost region 2002 to a denoiser 2100 on node 2021, which denoiser 2100 uses this data in combination with data from region 2011 to generate a higher quality denoised region 2121.

Grabbing data or rendering

If the connection between devices such as nodes 2021-2022 is slow (i.e., below a threshold latency and/or threshold bandwidth), then the ghosted region may be rendered locally faster than requesting results from other devices. This can be determined at run-time by tracking the rendering time for the network transaction speed and linear extrapolation of ghost region sizes. In such cases where rendering the entire ghost region is faster, multiple devices may eventually render the same portion of the image. The resolution of the rendered portion of the ghost region may be adjusted based on the variance of the base region and the determined degree of blur.

Load balancing

In one embodiment, static and/or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2021 and 2023. For dynamic load balancing, the variance determined by the denoising filter may require more time in denoising, but drives the amount of samples used to render a particular region of the scene, where low variance and blurred regions of the image require fewer samples. The particular region assigned to a particular node may be dynamically adjusted based on data from previous frames or dynamically passed across devices while they are rendering, so that all devices will have the same amount of work.

FIG. 22 illustrates an embodiment in which the monitor 2201- > 2202 running on each respective node 2021- > 2022 collects performance metric data including, but not limited to, the time consumed in transmitting data through the network interface 2211- > 2212, the time consumed in de-noising regions (with and without ghost region data), and the time consumed in rendering each region/ghost region. The monitor 2201-. Manager node 2201 then distributes the new workload for the new zone to nodes 2021 and 2022 based on the detected load. For example, manager node 2201 may communicate more work to those nodes that are not heavily loaded and/or redistribute work from those nodes that are overloaded. Additionally, the load balancer node 2201 may transmit reconfiguration commands to adjust the particular manner in which each of the nodes performs rendering and/or denoising (some examples of which are described above).

Determining ghost regions

In one embodiment, the size and shape of the ghost region 2001-2002 is determined based on a denoising algorithm implemented by denoiser 2100-2111. Their respective sizes can then be dynamically modified based on the detected variance of the samples being denoised. The learning algorithm for AI denoising itself can be used to determine the appropriate region size, or in other cases such as bi-directional blurring, the predetermined filter width will determine the size of the ghost region 2001-2002. In implementations using learning algorithms, the machine learning engine can be executed on the manager node 2201 and/or portions of the machine learning can be executed on each of the respective nodes 2021-2023 (see, e.g., fig. 18A-B and associated text above).

Aggregating the final image

In one embodiment, the final image is generated by aggregating the rendered and denoised regions from each of the nodes 2021-2023 without ghost regions or normals. In fig. 22, for example, the denoised regions 2121-2122 are communicated to the region processor 2280 of the manager node 2201, which region processor 2280 combines the regions to generate a final denoised image 2290, which final denoised image 2290 is then displayed on the display 2290. The region processor 2280 may combine the regions using various 2D synthesis techniques. Although illustrated as separate components, the region processor 2280 and denoised image 2290 may be integral with the display 2290. In this embodiment, the various nodes 2021-2022 may use direct-send techniques to transmit the denoised regions 2121-2122 and potentially use various lossy or lossless compression of the region data.

AI denoising remains a costly operation and moves into the cloud as the game progresses. In this way, it may become desirable to distribute the processing of denoising across multiple nodes 2021-2022 to achieve a real-time frame rate for traditional games or Virtual Reality (VR) that require higher frame rates. Movie studios also often render in large rendering fields that can be used for faster denoising.

One embodiment of a method for performing distributed rendering and denoising is illustrated in FIG. 23. The method may be implemented within the context of the system architecture described above, but is not limited to any particular system architecture.

At 2301, a graphics job is dispatched to a plurality of nodes that perform ray tracing operations to render regions of an image frame. In one embodiment, each node may already have the data in memory required to perform the operation. For example, two or more of the nodes may share a common memory, or a local memory of the node may already store data from a previous ray tracing operation. Alternatively or additionally, some data may be transmitted to each node.

At 2302, the "ghost regions" required for a given level of denoising (i.e., at an acceptable level of performance) are determined. The ghost region includes any data required to perform a specified level of denoising, including data owned by one or more other nodes.

At 2303, data relating to the ghost region (or portions thereof) is exchanged between nodes. At 2304, each node performs denoising (e.g., using the exchanged data) on its respective region, and at 2305, the results are combined to generate a final denoised image frame.

In one embodiment, a manager node or master node, such as that shown in fig. 22, dispatches work to the nodes and then combines the work performed by the nodes to generate a final image frame. In another embodiment, a peer-based architecture (peer-based architecture) is used, where nodes are peers that exchange data to render and de-noise the final image frame.

The nodes described herein (e.g., nodes 2021-2023) may be graphics processing computing systems interconnected via a high-speed network. Alternatively, the nodes may be individual processing elements coupled to a high-speed memory fabric. In this embodiment, all nodes may share a common virtual memory space and/or a common physical memory. In another embodiment, the node may be a combination of a CPU and a GPU. For example, the manager node 2201 may be a CPU and/or software executing on a CPU, and the node 2021 and 2022 may be a GPU and/or software executing on a GPU. Various different types of nodes may be used while still complying with the underlying principles of the invention.

Example neural network implementation

There are many types of neural networks; a simple type of neural network is a feed-forward network. The feed-forward network may be implemented as an acyclic graph in which nodes are arranged in layers. Typically, a feed-forward network topology comprises an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at a node of an input layer of a feed-forward network is propagated (i.e., "fed-forward") to a node of an output layer via an activation function that computes the state of the nodes of each successive layer in the network based on coefficients ("weights") associated with each of the edges connecting the layers, respectively. The output from the neural network algorithm can take various forms depending on the particular model represented by the algorithm being executed.

Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training data set. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting weights until the network model executes with minimal error for all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an input representing an instance in a training dataset is compared to a "correct" annotated output for the instance, an error signal representing the difference between the output and the annotated output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is propagated back through the layers of the network. The network is considered "trained" when the error of each of the outputs generated from the instances of the training data set is minimized.

The accuracy of machine learning algorithms can be significantly affected by the quality of the data set used to train the algorithm. The training process can be computationally intensive and can require a significant amount of time on a conventional general purpose processor. Thus, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for training of optimized neural networks, since the computations performed in adjusting the coefficients in the neural network are naturally applicable to parallel implementations. In particular, many machine learning algorithms and software applications have been adapted to take advantage of parallel processing hardware within a general purpose graphics processing device.

Fig. 24 is a general diagram of a machine learning software stack 2400. The machine learning application 2402 can be configured to train a neural network using a training data set or implement machine intelligence using a trained deep neural network. The machine learning application 2402 can contain training and reasoning functionality for the neural network and/or specialized software that can be used to train the neural network prior to deployment. The machine learning application 2402 can implement any type of machine intelligence including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 2402 can be enabled via the machine learning framework 2404. The machine learning framework 2404 can provide a library of machine learning primitives. Machine learning primitives are the basic operations typically performed by machine learning algorithms. Without the machine learning framework 2404, developers of machine learning algorithms would be required to create and optimize the primary computational logic associated with the machine learning algorithms, and then re-optimize the computational logic as new parallel processors are developed. Rather, the machine learning application can be configured to perform the necessary computations using the primitives provided by the machine learning framework 2404. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed in training a Convolutional Neural Network (CNN). The machine learning framework 2404 can also provide primitives to implement basic linear algebraic subroutines performed by many machine learning algorithms, such as matrix and vector operations.

The machine learning framework 2404 can process input data received from the machine learning application 2402 and generate appropriate inputs to the computing framework 2406. The compute framework 2406 can abstract out the underlying instructions provided to the GPGPU driver 2408 to enable the machine learning framework 2404 to leverage hardware acceleration via the GPGPU hardware 2410 without requiring the machine learning framework 2404 to have intimate knowledge of the architecture of the GPGPU hardware 2410. Additionally, the computing framework 2406 can implement hardware acceleration of the machine learning framework 2404 across various types and generations of GPGPU hardware 2410.

GPGPU machine learning acceleration

Fig. 25 illustrates a multi-GPU computing system 2500, according to an embodiment. The multi-GPU computing system 2500 can include a processor 2502 coupled to a plurality of GPGPUs 2506A-D via a host interface switch 2504. In one embodiment, the host interface switch 2504 is a PCI express switch device that couples the processor 2502 to a PCI express bus through which the processor 2502 can communicate with the set of gpgpgpu 2506A-D. Each GPGPU of the plurality of GPGPGPGPUs 2506A-D can be an example of a GPGPU as described above. GPGPGPUs 2506A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2516. The high-speed GPU-to-GPU link can be connected to each of the GPGPUs 2506A-D via dedicated GPU links. The P2P GPU link 2516 enables direct communication between each of the GPGPGPUs 2506A-D without requiring communication through a host interface bus to which the processor 2502 is connected. Where GPU-to-GPU traffic is directed to the P2P GPU link, the host interface bus remains available for system memory access or communications with other instances of the multi-GPU computing system 2500, e.g., via one or more network devices. Although the GPGPU2506A-D is connected to the processor 2502 via the host interface switch 2504 in the illustrated embodiment, in one embodiment, the processor 2502 includes direct support for the P2P GPU link 2516 and is capable of connecting directly to the GPGPGPUs 2506A-D.

Machine learning neural network implementation

The computing architecture provided by the embodiments described herein can be configured to perform those types of parallel processing that are particularly suited to training and deploying neural networks for machine learning. Neural networks can be generalized as networks having functions of graph relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. One exemplary type of neural network is a feed forward network as previously described.

A second exemplary type of neural network is a Convolutional Neural Network (CNN). CNN is a specialized feed-forward neural network for processing data with a known grid-like topology, such as image data. CNNs are therefore commonly used in computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized as a set of "filters" (feature detectors inspired by the receptive field found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The calculation for CNN involves applying a convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized type of mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to convolution can be referred to as the input, while the second function can be referred to as the convolution kernel. The output may be referred to as a feature map. For example, the input to the convolutional layer can be a multi-dimensional array of data defining various color components of the input image. The convolution kernel can be a multidimensional array of parameters, wherein the parameters are adapted by a training process for the neural network.

A Recurrent Neural Network (RNN) is a series of feed-forward neural networks that contain feedback connections between layers. RNNs enable modeling of sequence data by sharing parameter data across different parts of a neural network. The architecture for RNNs includes loops. The loop represents the effect of the current value of the variable on its own value at a future time, since at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature in which linguistic data can be constructed.

The diagrams described below present exemplary feed-forward, CNN, and RNN networks, and describe general procedures for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are exemplary and non-limiting for any particular embodiment described herein, and that the illustrated concepts are generally applicable to deep neural networks and machine learning techniques in general.

The exemplary neural networks described above can be used to perform deep learning. Deep learning is machine learning using a deep neural network. A deep neural network used in deep learning is an artificial neural network composed of a plurality of hidden layers, as opposed to a shallow neural network including only a single hidden layer. Deeper neural networks are generally more computationally intensive to train. However, the additional hidden layer of the network enables multi-step pattern recognition that produces reduced output errors relative to shallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-end network used to perform feature recognition, coupled to a back-end network that represents a mathematical model capable of performing operations (e.g., object classification, speech recognition, etc.) based on a feature representation provided to the model. Deep learning enables machine learning to be performed without requiring manual designed (hand warped) feature engineering to be performed for the model. Instead, deep neural networks are able to learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model that can map the detected features to an output. The mathematical models used by the network are generally specific to the particular task to be performed, and different models will be used to perform different tasks.

Once the neural network is structured, a learning model can be applied to the network to train the network to perform a particular task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Back propagation of errors is a common method used to train neural networks. The input vectors are presented to the network for processing. The output of the network is compared to the expected output using a loss function and an error value is calculated for each of the neurons in the output layer. These error values are then propagated back until each neuron has an associated error value that approximately represents the neuron's contribution to the original output. The network can then learn from those errors using an algorithm, such as a random gradient descent algorithm, to update the weights of the neural network.

26-27 illustrate exemplary convolutional neural networks. Fig. 26 illustrates various layers within a CNN. As shown in fig. 26, an exemplary CNN used to model image processing can receive input 2602 describing red, green, and blue (RGB) components of an input image. Input 2602 can be processed by multiple convolutional layers (e.g., convolutional layers 2604, 2606). Output from multiple convolutional layers may optionally be processed by a set of fully-connected layers 2608. Neurons in the fully connected layer have full connections to all activations in the previous layer, as described above for the feed forward network. Output from the fully connected layer 2608 can be used to generate output results from the network. Activation within fully connected layer 2608 can be computed using matrix multiplication rather than convolution. Not all CNN implementations utilize a fully connected layer. For example, in some implementations, convolutional layer 2606 can generate an output of CNN.

Convolutional layers are sparsely connected, unlike traditional neural network configurations found in fully connected layers 2608. The traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, as illustrated, the convolutional layers are sparsely connected, and the output due to the convolution of the domain (rather than the respective state values of each of the nodes in the domain) is input to the nodes of the subsequent layers. The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolution layer is one aspect that enables the CNN to be scaled to handle large images.

Fig. 27 illustrates exemplary computation stages within the convolution layer of the CNN. Input 2712 to the convolutional layer of CNN can be processed in three stages of convolutional layer 2714. These three stages can include a convolution stage 2716, a detector stage 2718, and a pooling stage 2720. Convolutional layer 2714 is then able to output data to the continuous convolutional layer. The last convolutional layer of the network can generate output profile data or provide input to the fully-connected layer, e.g., to generate classification values for input to the CNN.

Several convolutions are performed in parallel with generating the set of linear activations in convolution stage 2716. Convolution stage 2716 can include an affine transformation (affine transformation), which is any transformation that can be specified as a linear transformation plus a translation (transformation). Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a particular region in the input, which can be determined to be a local region associated with the neuron. The neuron calculates a dot product between the weight of the neuron and a region in the local input to which the neuron is connected. The output from convolution stage 2716 defines the set of linear activations processed by successive stages of convolution layer 2714.

The linear activation can be processed by the detector stage 2718. In the detector stage 2718, each linear activation is processed by a nonlinear activation function. The nonlinear activation function adds to the nonlinear properties of the overall network without affecting the receptive field of the convolutional layer. Several types of non-linear activation may be used. One particular type is a modified linear unit (ReLU) that uses an activation function defined as f (x) max (0, x) such that the threshold for activation is at zero.

The pooling stage 2720 uses a pooling function that replaces the output of the convolutional layer 2706 with summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network so that small translations to the input do not alter the pooled output. Invariance of local translation can be useful in situations where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions can be used during the pooling stage 2720, including maximum pooling, average pooling, and l2 norm pooling. Additionally, some CNN implementations do not include a pooling stage. Such an implementation is instead an additional convolution stage with an increased step size (stride) relative to the previous convolution stage.

The output from convolutional layer 2714 can then be processed by the next layer 2722. The next layer 2722 can be one of the other convolutional layers or fully connected layers 2708. For example, the first convolutional layer 2704 of fig. 27 can output to the second convolutional layer 2706, and the second convolutional layer can output to the first layer of the fully connected layer 2808.

Fig. 28 illustrates an exemplary recurrent neural network 2800. In a Recurrent Neural Network (RNN), a previous state of the network affects the output of the current state of the network. The RNN can be constructed in various ways using various functions. The use of RNNs generally involves a rounding to the use of mathematical models to predict the future based on previous sequences of inputs. For example, RNNs may be used to perform statistical language modeling to predict upcoming words given a previous sequence of words. The illustrated RNN2800 can be described as having an input layer 2802 that receives input vectors, an implication layer 2804 that implements a looping function, a feedback mechanism 2805 that implements "memory" of previous states, and an output layer 2806 to output results. The RNN2800 operates on a time step basis. The state of the RNN at a given time step is affected based on the previous time step via feedback mechanism 2805. For a given time step, the state of the hidden layer 2804 is defined by the previous state and the input at the current time step. The initial input at the first time step (x1) can be processed by the hidden layer 2804. The second input (x2) can be processed by the implication layer 2804 using state information determined during processing of the initial input (x 1). A given state can be calculated as s _ t ═ f (Ux _ t + Ws _ (t-1)), where U and W are parameter matrices. The function f is typically non-linear, such as a hyperbolic tangent function (Tanh) or a variant of the modification function f (x) max (0, x). However, the particular mathematical function used in the hidden layer 2804 can vary depending on the particular implementation details of the RNN 2800.

In addition to the basic CNN and RNN networks described, variations on those networks may be implemented. One example RNN variant is a Long Short Term Memory (LSTM) RNN. LSTM RNNs are able to learn long-term dependencies, which may be necessary for processing longer sequences of languages. A variant on CNN is a convolutional deep belief network, which has a similar structure to CNN and is trained in a similar way to deep belief networks. A Deep Belief Network (DBN) is a generative neural network, which is composed of layers of probabilistic (random) variables. The DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

Fig. 29 illustrates training and deployment of a deep neural network. Once a given network has been structured for a task, the neural network is trained using the training data set 2902. Various training frameworks 2904 have been developed to enable hardware acceleration of the training process. For example, the machine learning framework described above may be configured as a training framework. A training framework 2904 can be hooked into the untrained neural network 2906 and enable the untrained neural network to be trained using parallel processing resources described herein to generate a trained neural network 2908.

To begin the training process, initial weights may be selected randomly or through pre-training using a deep belief network. The training cycle is then executed in a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performed as a mediated operation (mediated operation), such as when the training data set 2902 contains inputs paired with desired outputs for the inputs, or where the training data set contains inputs with known outputs and outputs of a neural network are manually ranked. The network processes the input and compares the resulting output to a set of expected or expected outputs. The error is then propagated backwards through the system. The training framework 2904 is capable of adjusting the weights that control the untrained neural network 2906. The training framework 2904 can provide tools to monitor how well the untrained neural network 2906 converges towards a model suitable for generating a correct response based on known input data. The training process is repeated as the weights of the network are adjusted to improve the output generated by the neural network. The training process can continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 2908. The trained neural network 2908 can then be deployed to implement any number of machine learning operations.

Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 2902 will contain input data without any associated output data. The untrained neural network 2906 is able to learn the groupings within the unlabeled inputs and is able to determine how the individual inputs relate to the overall data set. Unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network 2907 that can perform operations useful in reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection that allows for identification of data points in the input data set that deviate from the normal pattern of data.

Variations on supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 2902 contains a mixture of labeled and unlabeled data of the same distribution. Incremental learning (supervised learning) is a variant of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 2908 to adapt to new data 2912 without forgetting the knowledge instilled within the network during initial training.

The training process, particularly for deep neural networks, whether supervised or unsupervised, may be too computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of compute nodes can be used to accelerate the training process.

Fig. 30A is a block diagram illustrating distributed learning. Distributed learning is a training model that performs supervised or unsupervised training of a neural network using a plurality of distributed computing nodes, such as the nodes described above. The distributed computing nodes can each contain one or more host processors and one or more of the general purpose processing nodes, such as highly parallel general purpose graphics processing units. As illustrated, the distributed learning can be model parallel 3002, data parallel 3004, or a combination of model and data parallel performed.

In model parallel 3002, different compute nodes in a distributed system are able to perform training computations for different parts of a single network. For example, each layer of the neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Segmenting the computations associated with different layers of the neural network enables the training of very large neural networks in which the weights of all layers would not fit into the memory of a single compute node. In some instances, model parallelism may be particularly useful in performing unsupervised training of large neural networks.

In data parallelism 3004, different nodes of the distributed network have complete instances of the model and each node receives a different portion of the data. The results from the different nodes are then combined. Although different approaches to data parallelism are possible, data parallelism training approaches all require techniques to synchronize model parameters and combine results between each node. Exemplary methods for combining data include parametric averaging and data parallelism based updating. Parameter averaging each node is trained on a subset of the training data and global parameters (e.g., weights, biases) are set to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains parameter data. Update-based data parallelism is similar to parameter averaging, except that instead of transmitting parameters from nodes to parameter servers, updates to the model are transmitted. Additionally, update-based data parallelism can be performed in a decentralized manner, where updates are compressed and transferred between nodes.

The combined model and data parallelism 3006 can be implemented, for example, in a distributed system where each compute node contains multiple GPUs. Each node can have a complete instance of the model, with a separate GPU within each node being used to train different portions of the model.

Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and gpgpgpu described herein are each capable of implementing various techniques to reduce the overhead of distributed training, including techniques to achieve high bandwidth GPU-to-GPU data transfer and accelerated remote data synchronization.

Exemplary machine learning application

Machine learning can be applied to solve a variety of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from rendering human visual capabilities (such as recognizing faces) to creating new classes of visual capabilities. For example, a computer vision application can be configured to recognize sound waves from vibrations induced in objects visible in a video. Parallel processor accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously possible and enables inference systems to be deployed using low power parallel processors.

Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to particular training inputs. The parallel processors described herein can enable rapid training of increasingly complex neural networks for autonomous driving solutions, and enable deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks have enabled machine learning approaches to Automatic Speech Recognition (ASR). ASR involves the creation of a function that computes the most likely language sequence given an input sound sequence. Accelerated machine learning using deep neural networks has enabled the replacement of Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) previously used for ASR.

Parallel processor accelerated machine learning can also be used to accelerate natural language processing. The automatic learning process can utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. An exemplary natural language processor application involves automatic machine translation between human languages.

Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. The training platform is generally highly parallel and includes optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include highly parallel general purpose graphics processing units and/or multiple GPU computing systems described herein. In contrast, deployed machine learning platforms generally contain lower power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

FIG. 30B illustrates an exemplary inference System on a chip (SOC)3100 suitable for performing inference using a trained model. SOC3100 can integrate processing components, including media processors 3102, vision processors 3104, GPGPU3106, and multi-core processor 3108. The SOC3100 can additionally include on-chip memory 3105, which can implement a shared on-chip data pool accessible to each of the processing components 3105. The processing components can be optimized for low power operation to enable deployment to various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC3100 can be used as part of a master control system for an autonomous vehicle. Where SOC3100 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with relevant functional safety standards of the deployment jurisdiction.

During operation, the media processor 3102 and the vision processor 3104 can work in concert to accelerate computer vision operations. The media processor 3102 is capable of low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in the on-chip memory 3105. The vision processor 3104 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using the trained image recognition model. For example, the vision processor 3104 can perform CNN-accelerated convolution operations for image recognition on high-resolution video data, while back-end model calculations are performed by the GPGPU 3106.

The multi-core processor 3108 can include control logic to assist in the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 3102 and the visual processor 3104. The multi-core processor 3108 can also act as an application processor to execute software applications that can take advantage of the speculative computing capabilities of the GPGPU 3106. For example, at least a portion of the navigation and driving logic can be implemented in software executing on the multicore processor 3108. Such software can issue computational workloads directly to the GPGPU3106 or computational workloads can be issued to the multi-core processor 3108, which multi-core processor 3108 can offload at least a portion of those operations to the GPGPU 1306.

The GPGPU3106 can include a low power configuration of compute clusters, such as compute clusters DPLAB06A-DPLAB06H, within a highly parallel general purpose graphics processing unit DPLAB 00. The compute clusters within GPGPU3106 can support instructions that are specifically optimized to perform inference computations on a trained neural network. For example, the GPGPU3106 can support instructions to perform low precision computations such as 8-bit and 4-bit integer vector operations.

Example ray tracing architecture

In one implementation, a graphics processor includes circuitry and/or program code to perform real-time ray tracing. In some embodiments, a dedicated set of ray tracing cores are included in a graphics processor to perform the various ray tracing operations described herein, including ray traversal and/or ray intersection operations. In addition to the ray tracing core, one embodiment includes multiple sets of graphics processing cores to perform programmable shading operations and multiple sets of tensor cores to perform matrix operations on tensor data.

FIG. 31 illustrates an exemplary portion of one such Graphics Processing Unit (GPU)3105, which GPU 3105 contains a set of dedicated graphics processing resources arranged into multi-core groups 3100A-N. While details are provided of only a single multi-core group 3100A, it will be appreciated that other multi-core groups 3100B-N may be equipped with the same or similar set of graphics processing resources.

As illustrated, the multi-core group 3100A may include a set of graphics cores 3130, a set of tensor cores 3140, and a set of ray trace cores 3150. Scheduler/dispatcher 3110 schedules and dispatches graphics threads for execution on

various cores

3130, 3140, 3150. The set of register files 3120 store operand values used by the

cores

3130, 3140, 3150 in executing the graphics threads. These registers may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements), and patch registers for storing tensor/matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

One or more level 1 (L1) caches and texture units 3160 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, and the like, locally within each multi-core group 3100A. A level 2 (L2) cache 3180 shared by all or a subset of the multi-core groups 3100A-N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 3180 may be shared across multiple multi-core groups 3100A-N. One or more memory controllers 3170 couple the GPU 3105 to memory 3198, which memory 3198 may be system memory (e.g., DRAM) and/or dedicated graphics memory (e.g., GDDR6 memory).

Input/output (IO) circuitry 3195 couples GPU 3105 to one or more IO devices 3195, such as a Digital Signal Processor (DSP), network controller, or user input device. On-chip interconnects may be used to couple I/O devices 3190 to GPU 3105 and memory 3198. One or more IO memory management units (IOMMUs) 3170 of IO circuitry 3195 couple IO device 3190 directly to system memory 3198. In one embodiment, IOMMU3170 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 3198. In this embodiment, IO device 3190, CPU(s) 3199, and GPU(s) 3105 may share the same virtual address space.

In one implementation, IOMMU3170 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 3198). The base of each of the first and second sets of page tables may be stored in a control register and swapped out upon a context switch (e.g., so that access to the relevant set of page tables is provided for the new context). Although not illustrated in FIG. 31, each of the

cores

3130, 3140, 3150 and/or the multi-core groups 3100A-N may include a Translation Lookaside Buffer (TLB) to cache guest virtual-to-guest physical translations, guest physical-to-host physical translations, and guest virtual-to-host physical translations.

In one embodiment, CPU 3199, GPU 3105, and IO device 3190 are integrated on a single semiconductor chip and/or chip package. The illustrated memory 3198 may be integrated on the same chip or may be coupled to the memory controller 3170 via an off-chip interface. In one implementation, memory 3198 includes GDDR6 memory, which GDDR6 memory shares the same virtual address space with other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

In one embodiment, the tensor core 3140 includes multiple execution units specifically designed to perform matrix operations, which are the basic computation operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and reasoning. The tensor core 3140 may perform matrix processing using various operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and nibble (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high quality final image.

In a deep learning implementation, parallel matrix multiplication work may be scheduled for execution on the tensor core 3140. Training of neural networks requires, in particular, a large number of matrix dot-product operations. To handle the inner product formulation of the nx N matrix multiplication, the tensor kernel 3140 may contain at least N dot product processing elements. Before the start of matrix multiplication, one complete matrix is loaded into the tile register and for each of the N cycles, at least one column of the second matrix is loaded. At each cycle, there are N dot products processed.

Depending on the particular implementation, the matrix elements may be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT 4). Different precision modes can be specified for the tensor core 3140 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads that can tolerate quantization to bytes and nibbles).

In one embodiment, ray trace core 3150 speeds up ray trace operations for both real-time ray trace and non-real-time ray trace implementations. In particular, the ray tracing core 3150 includes ray traversal/intersection circuitry to perform ray traversal using a Bounding Volume Hierarchy (BVH) and identify intersections between primitives and rays that are enclosed within the BVH volume. Ray tracing core 3150 may also contain circuitry for performing depth testing and culling (e.g., using a Z-buffer or similar arrangement). In one implementation, the ray tracing kernel 3150 performs traversal and intersection operations in conjunction with the image denoising techniques described herein, at least a portion of which may be performed on the tensor kernel 3140. For example, in one embodiment, tensor kernel 3140 implements a deep learning neural network to perform denoising of frames generated by ray tracing kernel 3150. However, the CPU(s) 3199, graphics kernel 3130, and/or ray tracing kernel 3150 may also implement all or a portion of a denoising and/or deep learning algorithm.

Additionally, as described above, a distributed approach to denoising may be employed in which the GPU3105 is in a computing device coupled to other computing devices through a network or high speed interconnect. In this embodiment, interconnected computing devices share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, ray tracing core 3150 handles all BVH traversals and ray-primitive intersections, avoiding overloading graphics core 3130 with thousands of instructions per ray. In one embodiment, each ray tracing core 3150 contains a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, in one embodiment, the multi-core group 3100A can simply launch the ray probe, and the ray tracing core 3150 independently performs ray traversal and intersection and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. While the ray tracing core 3150 performs traversal and intersection operations, the

other cores

3130, 3140 are released to perform other graphics or computational work.

In one embodiment, each ray tracing core 3150 includes a traversal unit to perform BVH test operations and an intersection unit to perform ray-primitive intersection tests. The crossbar unit generates a "hit", "no-hit", or "multiple-hit" response, and the crossbar unit provides the response to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 3130 and tensor core 3140) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between graphics kernel 3130 and ray tracing kernel 3150.

In one embodiment, the ray trace core 3150 (and/or other cores 3130, 3140) includes hardware support for a ray trace instruction set, such as Microsoft's DirectX ray trace (DXR), which includes a DispatchRays command along with ray generation, nearest hits, arbitrary hits, and miss shaders, which enable each object to be assigned a unique set of textures and shaders. Another ray tracing platform that may be supported by ray tracing kernel 3150, graphics kernel 3130 and tensor kernel 3140 is Vulkan 1.1.85. Note, however, that the underlying principles of the invention are not limited to any particular ray tracing ISA.

In general, the

various cores

3150, 3140, 3130 may support a ray trace instruction set that includes instructions/functions for ray generation, closest hits, any hits, ray-primitive intersections, per-primitive and hierarchical bounding box constructions, misses, accesses, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

light generationThe ray generation instructions may be executed for each pixel, sample or other user-defined job assignment.

Closest hitThe closest hit instruction may be executed to locate the closest intersection point of the ray with a primitive within the scene.

Hit arbitrarilyAny hit instruction identifies a number of intersections between primitives and rays within the scene, potentially identifying a new closest intersection point.

Crossing-the intersection instruction performs a ray-primitive intersection test and outputs a result.

Per-primitive bounding box structureThis instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

MissIndicating that the ray missed all geometric shapes within the scene or a specified region of the scene.

Access Sub-volumes indicating the ray will traverse.

Abnormality (S)Including various types of exception handlers (e.g., invoked for various error conditions).

Reduced precision Bounding Volume Hierarchy (BVH) structure

Embodiments of the present invention enable high quality BVH constructions with reduced precision of spatial partitioning and direct incremental hierarchical output. These embodiments are suitable for custom fixed-function hardware implementations, but may also be useful in the context of programmable platforms such as GPUs. Some embodiments operate in a compact integer space, greatly reducing hardware implementation costs. One implementation is closely tied to the recently proposed incremental BVH format and allows for direct output of the recently proposed incremental BVH format to enable fast ray tracing of highly dynamic complex scenes. Systems that utilize caching schemes and lossless compression to reduce memory and storage bandwidth are also disclosed.

High quality BVH for ray tracing

Real-time performance of ray tracing is typically achieved using an auxiliary acceleration data structure. The ray trace community (community) appears to have decided BVH as the acceleration structure of choice in most cases.

The Bounding Volume Hierarchy (BVH) is a tree data structure that serves as a spatial index into the scene. This spatial index greatly speeds the ray-traced kernel operation: the finding of the intersection between a ray and a geometric primitive. BVHs surround the geometry in a hierarchical manner. Each node of the BVH typically stores an Axis Aligned Bounding Box (AABB) that represents the spatial extent of the subset of the geometry that the node references. The root node of the BVH stores the full spatial extent of the geometry of interest. Each node containing a root stores references to its children nodes that cover smaller and smaller portions of the scene. Leaf nodes of the hierarchy store references to primitives that can then be tested for ray intersections. The number of triangles referenced by a leaf node is not fixed and can vary between leaves.

Fig. 32A shows the general structure of a BVH hierarchy, which includes a root node 3200, a first set of child nodes 3201A-B under the root node, and a set of leaf nodes 3202A-D under the first set of child nodes. A different set of primitives 3203 are shown within each of the leaf nodes 3202A-D. Note that fig. 32A is merely an example of one particular hierarchy. BVHs are general tree structures that can have many levels (e.g., 20 levels for many real-world scenes). Therefore, the underlying principles of the invention are not limited to the example shown in fig. 32A.

FIG. 32B illustrates a 2D representation of a parent node 3210 and one of its child nodes 3211. In this example, the left offset value L_xIndicates a distance along the X-axis from the left side of parent 3210 to the left side of child 3211, and a right offset value R_xIndicating the distance along the X-axis from the right side of parent 3210 to the right side of child 3211. The minimum and maximum values of these types along a particular axis (the X-axis in this example) are often used to determine which primitives are contained within each bounding box.

BVHs can be formed with arbitrary branching factors, but most modern implementations use trees that are between two and eight wide. BVHs are normally constructed so that they tightly enclose their underlying geometry. This ensures correct traversal results and optimal performance. In a dynamic scenario, the BVH structure must be updated or reconstructed often, in case geometric changes may be observed every frame. Research communities have therefore placed considerable attention on the goal of improving BVH construction speed while maintaining good traversal performance.

For this reason, a large number of various BVH constructing methods have appeared in recent years. Such methods can be broadly classified as top-down (top-down), LBVH (LBVH-style), refinement-based (refining-based), clustering-based (clustering-based), and incremental (incremental). Details associated with these methods can be found in the list of references cited at the end of this detailed description. A factor common in many of these builders is that they use Surface Area Heuristic (SAH). SAH can be used to guide the construction of BVHs by providing an objective way to estimate the ray tracing cost of splitting a node into multiple children when building a BVH.

Top-down BVH structure

Among the highest quality BVH construction algorithms is the so-called "top-down" BVH constructor. Since certain embodiments of the present invention use a top-down approach to BVH construction, various top-down construction techniques will now be described.

The code sequences set forth below illustrate the general flow of such a builder. The construction starts with a single root node representing the entire scene. For each node during construction, a termination condition is checked. Termination conditions are selected to control the depth of the hierarchy and are often selected based on variables such as the number of primitives remaining in the node, the depth of the node in the tree, or based on heuristics such as SAH. If the condition is satisfied, the node is only marked as a leaf and construction continues with the incomplete node.

Generic pseudo-code for top-down BVH construction:

for nodes that do not meet the termination criteria, a top-down construction process attempts to segment the node to form a plurality of child nodes. The above pseudo-code assumes that two child nodes will be generated, which is a common configuration. Splitting the nodes amounts to determining to divide the underlying geometry into two subsets, computing the AABBs for the two subsets, and adding these new nodes as children of the original node. Several candidate partitions may be evaluated as part of the partitioning strategy. The segmentation cost (the efficiency of the prediction of tracing the ray through the newly created node) is used to select between candidate segmentations. Once the segmentation is selected, the geometry is partitioned accordingly and the algorithm recurses with child nodes that can be segmented in the same way.

Binned node partition

In general, a high quality top-down BVH builder follows the general flow outlined above. The main difference in how these algorithms operate is by employing different algorithms for the evaluateplacation () function (line 9). The most commonly deployed algorithms are those that target minimizing the SAH cost of a partition, which is given by:

where P is the parent node, L and R are the left and right child nodes, SA () is the surface area, and NL and NR are the number of primitives assigned to the left and right child nodes, respectively. KI and KT are implementation-defined constants that capture the cost of traversing the node and cross-primitive, respectively. The general strategy that is commonly employed to minimize SAH is to attempt to find an axis-aligned split plane within a node and assign primitives to the left and right child nodes according to this plane. By calculating the value of equation 1 for a plurality of candidate partition planes, a good partition can be found.

However, to maintain reasonable construction speed, it is not possible to examine a large number of planes along any given axis when searching for candidate segmentations. Therefore, it is common to employ binning approximation for segmentation. A small number of planes (typically 8-32) are placed uniformly along the length of the bounding box of the node. Triangles are "binned" into the regions between the planes, allowing the SAH to be evaluated at the edges of the bins (bins). When this strategy is employed, some top-down builders select the longest axis of the node AABB to search for candidate partitions, while other builders search for all three axes.

Comparison of object segmentation and spatial segmentation

BVHs are flexible data structures that allow for two partitions when partitioning nodes. Object segmentation is the segmentation that groups the triangles themselves, and object segmentation computes bounding volumes independently. Any grouping is allowed, so it is common that the resulting AABBs of the child nodes may overlap to some extent. This is in contrast to kd-trees, which always require a strict partitioning of the space.

A drawback of object segmentation is that if there is a lot of overlap between sibling nodes, this can have a detrimental effect on traversal performance, since a ray will more likely need to access both subtrees. A common characteristic of high quality BVH builders is that a second partition, called spatial partition, is considered. Similar to kd-trees, spatial partitioning allows for strict partitioning of space into two disjoint regions. With spatial partitioning, it is therefore possible to refer to primitives in two nodes if the two nodes overlap the partition plane. However, this can be very beneficial for large triangles, as the overlap is eliminated. BVH construction enables to freely mix the two types of partitions during construction. The spatial segmentation of the primitives can be performed in advance or during construction itself as a pre-processing of the culled large triangle references.

Compact BVH representation

In a typical ray tracker, a data structure such as a BVH can consume a large portion of the total memory footprint (total memory print) and working set of the rendering process. This is a problem for larger scenes, as the cache and local buffer size may not be sufficient to maintain scene data on-chip, especially for incoherent light distributions.

By reducing the storage requirements of the node bounding planes, often via quantization, a more compact representation of BVHs can be achieved. In addition, a reduction in the size of the child pointers can be produced using depth-first ordering of nodes, implicit indexing, or treelet-like clustering.

Recently, a variety of compressed BVH formats have emerged, which are built on a variety of the above mentioned compression techniques to reduce the size of BVH nodes. One embodiment of the present invention utilizes a slightly modified version of the format of Vaidyanathan et al [29], an overview of which will now be provided. The version used by the embodiments of the present invention is almost identical but is handled in a very slightly different way due to the use of a global grid (see e.g. fig. 33, element 3302) that is not used by the format of Vaidyanathan.

FIG. 32B shows the parent plane in the scheme relative to Vaidyanathan (e.g., using offset value L)_xAnd R_x) How to encode bounding planes. The scheme employs integer plane quantization, plane reuse between parent and sibling nodes, and techniques to reduce pointer overhead. The structure stores pairs of nodes and contains the following elements: 1)1A bit-leaf flag, 2) six NB bit-plane offsets, 3) two 3-bit parent-plane reuse masks, and 4) an NP-bit pointer to the right child pair. Any BVH node pair is guaranteed to share at least six bounding planes with its parent, and thus the reuse mask indicates which children share which plane of the parent. By storing six new planes along with the reuse mask, all twelve planes can be inferred. This sharing of planes occurs incrementally down the tree at each node. The choice of NB determines the level of quantization of the bounding planes and hence the compactness of the bounding box. During quantization and again during traversal, a node index (2 for the x-axis) is inferred for each node in each axis^eX). This exponent is essentially the scaling factor of the node along a given axis and is the lowest power of two that is just large enough in that axis to accommodate the node. Together with the parent node range, the exponent allows the computation of the exact floating point value for the quantized plane, and as such, the node structure encodes the floating point bounding box.

Embodiments of reduced precision Up-Down BVH builder

To produce a top-down BVH builder with reduced accuracy, one embodiment of the present invention uses the general control flow described above. The reduced precision implementation is used to generate and evaluate candidate planes (lines 8-14 in the code sequence above) and compatible implementations of partitionnodes (line 17 in the code sequence above). In one embodiment, the framework for quantizing primitives is used to work from a full-precision mesh. To accomplish this, one embodiment of the present invention relies on geometric quantization, heuristic evaluation (heuristic evaluation) and node output.

Briefly, for geometric quantization, the input is a regular full precision grid in memory at each point in time. During construction, primitives are read in and adaptively quantized depending on the range of the current node. A consistently conservative quantization scheme is used (i.e., quantization consistently provides completely rigorous results and there is no possibility of missed intersections in the final BVH). Quantization essentially provides a regular integer space of parameterable precision over the underlying floating point data within which BVH construction operations can be performed at low cost.

For heuristic evaluation, when a full-precision primitive is read from memory, its vertices are quantized to integer space, resulting in a conservative AABB. This vertex and AABB information can be used to perform triangle binning, centroid (centroid) computation, spatial segmentation, and SAH evaluation in integer space. With such a tool kit, a full SBVH-like hierarchy (both object segmentation and spatial segmentation) is generated with minimal quality degradation.

For the node output, once a determination is made by heuristic evaluation as to how to partition the current BVH node, a small footprint, incrementally encoded BVH hierarchy is produced in the fashion of Vaidyanathan et al [29] without requiring any kind of post-processing.

Geometric quantization

To enable direct construction of BVHs of reduced precision without any kind of post-processing step for the output hierarchy, the underlying quantization scheme used for the BVH construction operation is itself closely tied to the proposed delta tree output format. The quantization scheme provides the bottom layer "competing environment" (the "playing field"), over which everything else occurs.

Quantization begins with a full precision floating point input vertex. For purposes of illustration, a single precision IEEE 754 floating point number is used. It is not important to extend these concepts to double precision and possibly even to other floating point schemes. Each single degree of precision in an IEEE floating point consists of a sign bit S, an 8-bit exponent E, and a 23-bit mantissa M. The value encoded by a floating point number is given by:

(-1)^S×1.M×2^E-127(2)

The IEEE format always assumes an extra leading 1 bit in the mantissa, as shown. The exponent E is encoded as an unsigned number in the form of an offset.

Unlike integers, floating point numbers do not encode a rule space. Since the mantissa is a fixed number of bits, the distance between successive floating-point values increases as the exponent becomes larger. However, all floating point values with the same exponent (and same sign) encode a subset of the regularly spaced (similar to the uniform spacing of integers) floating point space that makes up the number. One embodiment of the present invention uses this fact as the basis for the quantization scheme.

Vaidyanathan's format [29] uses a fixed number of bits NB to store quantized planes. This value is similar to the mantissa value of a floating point, and the format derives the minimum exponent for each pixel such that the local reference frame of the node is only sufficient to accommodate the full range of the node (see fig. 32B). This defines the accuracy with which any child node bounding plane can be encoded. Lower nodes in the tree will have more precision to represent the child node bounding planes because the exponent can be reduced due to their smaller size. This mantissa-exponential representation can of course result in a coordinate space that is larger than a node, but results in a very compact structure.

Just as incremental traversal derives a local coordinate space for each node it encounters by deriving an index for each node, this space is derived for each node during construction. This space is then used not only for storage of the final tree, but also for construction itself. By doing so, a reduced-precision operation can be used that is aligned with and at the same precision as the incremental output hierarchy. This allows out-of-hierarchy writing during build.

Summary of the quantification

One embodiment of the input is a regular 32-bit single precision floating point grid, and for each node, an unsigned integer space is derived for each node to carry out node partitioning in the reduced precision space. The move to integer space may be performed by "binning" the vertices to a regular grid using a sequence of regular floating point operations. However, the underlying principles of the invention do not require binning of the vertices. Considering that the goal is to reduce full precision operations as much as possible, one embodiment employs a technique that does not require full floating point operations for this process.

In particular, a coordinate space is derived for each BVH node, similar to that derived by Vaidyanathan [29] during tree traversal (FIG. 32B). These per-node coordinate spaces are referred to herein as local grids. All node partitioning is performed within the local grid of nodes, meaning that the resulting bounding boxes correspond exactly to those written in the incremental output hierarchy.

In Vaidyanathan [29], a local grid is positioned anywhere within the irregular space of floating point numbers. One embodiment of the invention uses a different approach in which the local grid is arbitrarily positioned in a high precision regular grid called the global grid. Although the global grid is regular, each location in the global grid corresponds exactly to a floating point value.

FIG. 33 shows the relationship between the underlying floating point space and the global grid. As shown, higher exponentials in floating point space yield lower precision. Regularity in the global grid is achieved by fixing the exponent used to represent the value within the grid, rather than allowing the exponent to vary. The global grid linearizes the underlying floating point space by discarding the lower bits of the more precise values. Values further from the origin can often still be represented without error (indicated by large triangles), but values closer to the origin are more likely to have quantization error (smaller triangles).

For each axis, a global index is selected that is greater than or equal to the highest index found in that axis in the entire input grid. The level of precision is therefore normalized across the grid to the lowest level of precision that exists in the range of values. This allows all values to be represented, albeit at the expense of accuracy in values with smaller exponentials. During construction, full floating point vertices are re-read from memory during partitioning for each node. This means that quantization is re-performed each time a vertex is visited. By re-quantizing, the quantized vertices need not be stored in memory. In the presence of a memory cache (described below), partially quantized values can be cached instead of full precision values, allowing for scaling up the performance of the cache and reducing the overall cost of quantization. Currently, it is assumed that vertices are quantized at each node.

The final operation is to quantize the vertices to the current local grid (i.e., the current node for the partitioned). In one embodiment, quantization is a two-step process: quantized to a global grid and quantized from the global grid to a current local grid.

Constant of precision

Prior to construction, precision constants defining the precision of the global grid and the local grid are determined. The elements of one embodiment of this data structure (i.e., the "precision constants" structure) are provided below. The following suffixes are used to indicate the type of vector variable: f (full precision floating point), u (unsigned integer), i (signed integer). For unsigned and signed integers, the bit width will vary due to the particular use of the variables and the choice of parameters.

The first set of constants is the number of global bits per axis (globalbitspaxais). This value encodes the number of bits for each axis of the global grid. These values need not be equal and may be assigned, for example, in proportion to the length of the scene bounding box in each axis. In a given axis, the length of the scene bounding box and the number of bits assigned to that axis imply a global index that defines the precision of the global grid. Smaller box lengths and more allocated bits produce higher precision global boxes, and vice versa. The total number of bits allocated to represent vertices in the global grid, referred to herein as NV, is equal to the sum of the elements of globalbitspraxis.

The second constant is the Bits Per Plane (BPP). This constant corresponds exactly to the bits per plane of Vaidyanathan [29], and together with the local grid's exponent defines the local grid's precision. The total number of bits allocated to represent vertices in the local grid is called NL, which is equal to BPP 3.

The precision constant defined above specifies the number of bits per axis of the global grid and the local grid.

Constructing a global grid

At the beginning of the construction, the global grid and the local grid of the root node of the BVH are determined. In fact, much of this work is in constructing the global grid, and the root local grid can be generically inferred from the global grid. The following code sequence is used in one embodiment to specify a global raster data structure.

One embodiment of a sequence of operations for constructing a global grid is illustrated in FIGS. 34A-D. Root AABB alignment is illustrated in fig. 34A. The purpose of this stage is to conservatively align the minimum and maximum coordinates of the scene AABB to global grid accuracy, as global grid accuracy may be lower than their current accuracy. The globalsrid exponents, selected earlier as part of the precision constant, imply a regular signed grid centered at the origin of the original floating point space, with the same precision as the floating point values that process the exponent. Root AABB alignment involves conservatively enlarging the full-precision root bounding box to align to this global grid.

The inputAABB and alignedAABB members of the globalprid structure are initialized to the full precision AABB of the mesh. alignedAABB is aligned to the global grid. However, note that alignedAABB remains a floating point AABB after alignment.

The following sequence of program code specifies these operations and others as follows:

in the above code, lines 2-64 define operations for performing alignment for one axis. The axes are independent in this respect, so the procedure is simply invoked for each axis in turn. Since for each axis a global exponent has been selected that is at least as large as the largest exponent encountered in the input trellis in that axis, a global exponent reduction is determined for each axis, which encodes how many units (units) the exponent is increased from the maximum value encountered in the input trellis (i.e., to accommodate the number of selected bits for that axis (line 2 in the code above)). Depending on the sign of the floating-point value of alignedAABB and also depending on whether it is the minimum coordinate or the maximum coordinate, a determination is also made as to whether to round the floating-point value of alignedAABB up or down (lines 10-13) in order to round it conservatively.

To complete the root AABB alignment, the difference between the global exponent and the exponent of the floating point box coordinate is determined (lines 17-19). After this operation, the mantissa of the floating-point value is rounded to the number of bits corresponding to the difference in exponents (lines 21-24). This ensures that the coordinates are aligned with the accuracy of the selected index. The operation roundtobnbitsfloat rounds the mantissa of the floating point value to N bits in the least significant digit and can round up or down depending on the value of roundUp.

The node index determination is shown in fig. 34B and in lines 26-30 of the code sequence above. The local grid is always aligned to the global grid. In one embodiment, the local grid defines bits per plane and a set of node indices, which means that the extent of the local grid is always a power of two units in all axes. In addition, since the precision of grids differs only by a power of two, each cell (cell) of any local grid will always have a power of two unit in the global grid. Thus, the full extent of the root local grid is a unit of the global grid that is greater than the smallest two power of the length of the current box after the root AABB alignment phase.

The next stage of alignment, rounding the maximum to the node grid, is shown in FIG. 34C and is performed in lines 32-65 of the code above. Since the number of units in the global grid is known for each cell in the root local grid, the remainder is determined and the maximum coordinates of the box are aligned to the local grid.

One note to round the maximum coordinate up is that if the same global index is selected as the index of the maximum coordinate, then increasing the maximum coordinate will likely increase its index. If this new exponent is larger, the root AABB alignment may be rerun. This behavior is implemented with the continue and break statements in lines 57 and 64, respectively, of the code above.

Finally, an origin transformation is determined, which is shown in FIG. 34D and lines 67-68 of the code sequence above. The origin transform provides a transform for converting any quantized vertices in the global grid to an unsigned space anchored at the original floating point origin. This concludes the initialization of the global grid structure.

Root local grid

Since the properties of the root local grid are inferred while aligning the AABBs of the global grid, the initialization of the root local grid can be done in a simple manner. The elements of the local grid are described with respect to LocalGrid struct below and FIG. 35. As previously noted, we can infer gridExponents for local grids by examining the pow2length glglobaldits member variables for global grids. In addition, we quantize the full-precision maximum coordinates of alignedAABB to the local grid using the routine we will describe later. This gives us the gridMax of the local grid. gridExponents and gridMax correspond exactly to the node index and maximum coordinates of the node bounding box in Vaidyanathan's format (the minimum coordinate is always zero and need not be stored). The following example code specifies a local raster data structure:

This process is explained again with reference to fig. 34B. Upon initialization of the global grid, the number of units in the global grid spanned by the box (shown in the figure as dgx and dgy) and the smallest power of two (2 in the figure) greater than this value are determined in each axis^exAnd 2^ey)。

Once these values are determined, gridExponents and globalshiftOffsets are determined. globalShiftOffsets encodes the difference in exponent (precision) between a given local grid and a global grid. The complete process for generating a local grid is shown in the following program code:

the next element to be computed is the originTransform of the local grid, which takes the same units as the origin transform of the global grid and is applied in addition to the transform of the global grid. The origin transform of the global grid transforms the quantized vertex to an unsigned space anchored at the original floating point origin (FIG. 34D), while the other origin transform of the local grid transforms it from the coordinate system to an unsigned space anchored at the origin of the local grid, which is located within the unsigned global space.

Finally, the local grid also carries a centroid box, which is a conservatively quantized AABB within the local grid that encompasses the centroid of the primitive within the current node. To initialize this in the root local grid, we simply compute this value with full precision while computing the full precision scene AABB, and then quantize it to the root local grid using the quantization process detailed in the next section.

Quantization primitive

Throughout the build process, full-precision floating-point vertices are re-read from main memory and quantized to the current precision level as defined by the current local grid. By doing so, the mesh may remain unmodified in memory for other tasks such as ray-triangle intersection, and avoid writing intermediate data. A single kernel operation that quantizes the vertices is implemented first. From this kernel operation, it is not important to quantize the AABB and triangles.

For the quantized AABB and triangle to be conservative and tight, the following facts must be considered: the quantization of the vertices will introduce a degree of uncertainty in the "true" values of the vertices. To take this into account, the full precision vertices are not quantized into a single quantized vertex. Instead, quantization to a reduced precision AABB is performed on each vertex, which is guaranteed to contain the original full precision vertex. This AABB captures the range of uncertainty relative to the full-precision vertex.

The overall goal of vertex quantization is to start with a 32-bit floating point vertex and quantize it to AABB into the local grid defined by the current node. However, due to spatial partitioning, it may be the case that not all vertices referenced by triangles in the current node are located within the representable region defined by this local grid of nodes. However, to perform a correct top-down BVH construction for spatial partitioning involving a triangular AABB, only the overlap of this AABB with the current node is required. One embodiment of the present invention thus utilizes the following quantization process:

1. The vertices are quantized to the global grid, resulting in AABBi of uncertainty in the global grid (floating point → integer quantization).

2. The origin transformation of the global grid is applied to AABBi.

3. The origin transformation of the local grid is applied to AABBi.

4. The AABBi is quantized to the precision of the current local grid (integer → integer quantization).

5. Clamping (clamp) AABBi to the range of the current node in the local grid. It is guaranteed that the resulting AABBu requires only NL bits per vertex to represent.

Of course, since both transforms use the same units, they can be combined. However, as described below, it can be advantageous not to do so. All vertices or AABBs are now represented as AABBu in NL bit space. This means that all building operations such as centroid calculation, binning, spatial partitioning of AABB, SAH evaluation and primitive list partitioning are performed in NL bit space. The AABB of the triangle is commonly computed as the union of the results of this process for each vertex. This is also performed in the unsigned NL bit space.

The most complex part of this process is quantization to a global grid (step 1). In one embodiment, vertex quantization is implemented according to the following code sequence:

as indicated above, to quantize the vertices to NV bit signed space, the exponent for each vertex component is subtracted from the global exponent for that axis. The component values are then shifted down by the difference. This of course may discard some of the precision in the lower part of the component. To capture this loss, the AABB is generated by rounding the minimum value down and the maximum value up after this shift. To maintain simplicity, the vertices are quantized to the unit AABB even though there is no error during quantization.

The transition to the unsigned NV bit space is accomplished by applying the origin transformation to the AABB. The origin transformation of the local grid is applied first, followed by a transition from the grid resolution of the global grid to the resolution of the local grid. In one embodiment, this is specified by the following code sequence:

the minimum and maximum values of the NV bits AABB are shifted down the globalShiftOffset for that axis. This shifts the vertices to a grid that requires the largest NV bits to represent, at the granularity of the current local grid, but is extended across the entire scene. In the case of spatial partitioning, the vertex may be located outside the current node at this time.

If globalShiftOffset is greater than 0, this will of course discard the precision. As before, the minimum value of the box is rounded down and the maximum value is rounded up to produce an AABB in a coarser grid. Note that the NL bit AABB can also span multiple units in a node grid if the NV bit AABB before rounding to the NL bit overlaps more than one division (division) of the node grid in a given axis.

By quantizing the minimum and maximum vertices of the AABB in this manner, a quantized AABB can be generated. However, the vertices of the AABB may require as many NV bits to represent. However, as previously described, only the overlap of the AABB with the bounding box of the current node is required. The AABB can thus be clamped to this bounding box, which allows all remaining build phases to be performed with a completely reduced accuracy. This is detailed in the captizezotolocalgrid code above in the clamp pandandexpandbox. The cartridge may also be enlarged to ensure that it has at least one unit of width in all axes. This is required to ensure that the exponent is not lowered indefinitely in the following nodes.

The operation roundtonbistint rounds an integer to N bits in the least significant digit and can round up or down depending on the value of roundUp. One other note is that since the clamping to NV bits global space is performed via the global exponent, globalShiftOffset can become negative, meaning that the current incremental node can be encoded with higher precision than NV bits space. To correct for this, only the shift up is made in this case, not the shift down, and no rounding is performed. This has the effect of "skipping" certain plane values in space. However, in all cases, the AABB in node space must span at least one unit in each axis. In Vaidyanathan [29 ]]In case the limit of floating point exponent has not been reached, the bounding plane is by definition at least 2 from the origin of the node^NB-1+1 units (otherwise, the index will drop again). Global index pair can yield less than 2^NB-1The ability of the surrounding plane of +1 to degrade the index sets a hard limit. Aligning to the (snap to) NV bit unsigned space reduces the cost per vertex for quantization.

Deriving local grids for new children

The above techniques may be used to establish a root node and perform quantization of the vertex-to-NB bit space. One implementation of logic to evaluate segmentation decisions, such as SAH binning, is provided below. Now, a description is provided for creating child nodes, regardless of which heuristic is used to determine the segmentation.

When the partition has been determined, the resulting child nodes will be represented as two integer bounding boxes in NB bit space. In addition to this, the centroid box can also be propagated to child nodes, as some partitioning schemes benefit from this (e.g., SAH binning on the centroid box is beneficial for object segmentation). The propagation of centroid boxes accumulated during primitive binning is also described below.

The first step in deriving a new local grid for a child node is to determine which planes from which child node will be shared with the parent. This is simply accomplished by determining which child node contains the plane of minimum and maximum coordinates closest to the parent node. These planes are encoded into delta format in much the same way as Vaidyanathan [29 ].

Due to the impact that does not occur in the full precision BVH construction of the rule, it is important to first determine this before computing the local grid. It is common during construction that vertices contained in each child node are quantized with a higher level of precision than when they are quantized to determine the parent (since there is typically an exponential decrease moving from parent to child). This means that the plane of the child node AABB may not be exactly shared between the parent and child due to the lower degree of rounding. Due to the quantization differences, the parent node may "swell" slightly around the child node. This is shown for the left child item 3501 in fig. 35 offset from the left side of the parent bounding box 3500 (in contrast to the right child item 3502, which right child item 3502 shares a plane with the parent item in the X and Y axes). This is not directly compatible with the incremental format or derivation of the local grid.

This can be solved by replacing the planes in the child nodes that should be shared with values in the parent (in other words, clamping them up or down to the parent plane). Then, a new local grid is derived from these new updated sub-AABBs. This slightly expands the sub-box but produces a tight sub-item compatible with the delta format. Once the updated boundary is obtained, a new local grid can be computed according to the following code sequence:

heuristic evaluation

Embodiments of the invention described herein enable top-down, spatially-partitioned oriented builders. It is always observed that such builders provide the highest traversal performance of all known BVH construction algorithms. In particular, one embodiment includes a binning-based builder that compares the results of conventional non-split binning SAH-like node partitioning to spatially partition-oriented partitioning. There is some commonality between these partitioning strategies, so the non-spatial partitioning binning techniques are described first, followed by the extensions required for spatial partitioning.

Primitive binning

Primitive binning is very inexpensive once quantization has occurred. For SBVH-like construction, two slightly different methods of binning are required. For spatial segmentation, the minimum and maximum coordinates of the AABB of the triangle are binned in the segmentation axis along the entire range of the node. For object segmentation, the AABB centroids are binned only along the extent of the centroid box. Fig. 36A illustrates an example with spatial segmentation, and fig. 36B illustrates an example with object segmentation (two examples each with two triangles of an object).

A centroid box 3601 that encloses the

centroids

3602, 3603 of the two objects is shown in fig. 36B. The reason for binning the object segmentation only along the centroid box is that this results in a higher quality segmentation. Since the AABB centroid determines the bins for each primitive during object segmentation, the selected bins must reside within the centroid box. This prevents "obsolete bins" outside the possible range and also prevents invalid splits (zero primitives in one sub-entry).

Binning can occur inexpensively in NB bit space. The main thing to determine is how many units in the local grid each bin will span. To calculate this, the length of the (nodal or centroid box) binning range is determined in this axis. Like existing top-down builders, the goal is a constant number of bins per axis. However, since fractional values are not allowed, each bin must have at least one unit in the local grid. To correct for cases where the number of bins desired is greater than the accuracy of the local grid, one embodiment clamps to the number of units available in the local grid. Thus, the number of bins is determined dynamically to some extent based on the available accuracy. However, it is observed that the number of bins needs to be limited for nodes that are typically very close to the leaf and relatively few. Thereby, the number of local grid units per bin is determined with a reduced accuracy that can be used for binning. The following code sequence specifies the number of local grid units per bin and the calculation of the number of bins in the segmentation axis.

Using this information, the vertices can be binned for spatial segmentation (this uses the entire length of the box in this axis), simply by dividing the vertex coordinates by numunitsipinbin (fig. 36A). For object segmentation, the centroid of the AABB of the triangle is binned. To do this, the centroid is determined in the local grid space.

Binning the centroid requires another operation. Each node computes the NB bit centroid transform as the smallest vertex of the centroid box for the node. This takes the unit of a local grid. This transformation is subtracted from the vertices before binning, moving it into the local centroid space (fig. 36B). Binning is then performed simply by dividing by numunitsbin.

This binning scheme eliminates the need for expensive full-precision operations, including multiplication/division for binning.

Spatial partitioning requires maintaining a start counter and an end counter for each bin. However, only a single counter is required when performing object segmentation. However, to avoid the need for separate hardware for both methods, separate start and end counters are used to implement both object segmentation binning and spatial segmentation binning. Object segmentation is made compatible with this method simply by incrementing both the start counter and the end counter of the single bin in which the centroid of the triangle is located during object segmentation.

A limitation of the integer binning approach is that each bin requires an integer number of subdivisions in the local grid. This can result in an effective loss of binning when the number of divisions across the range is small. For example, if NB is 8 bits and the node box is 158 units wide in x and 16 bins are desired, then each bin 158/16 may be determined to be 9 units. This means that the last bin will cover 23 units, enlarging the last bin to some extent. However, this does not have a significant impact on tree quality.

In the event that node partitioning is not possible with either binning method, one embodiment defaults to a simple "list partitioning" strategy, where the primitive array of a node is divided into two (no sorting) and AABB is computed. This can of course result in many nodes overlapping. However, this strategy is only required in a very small number of cases and has no significant impact on tree quality. Such partitioning is also performed when partitioning nodes with only two primitives. A third case where this partitioning is applied is when sufficient precision exists for only a single bin, as indicated in getNumUnitsPerBin above.

A lucky property of binning in reduced-precision space is that in most cases its negative impact on tree quality is zero above and beyond the impact imposed by incremental node coding. This is because only sufficient precision is required so that each bin has a width of at least one unit in the quantized space to accurately determine the bin in which the centroid of the triangle is to be placed. In a full-precision builder, the extra precision within the binning is essentially ignored for binning purposes.

The AABB of the bin will be inflated by the incremental format, but this will happen anyway as a side effect of using such a format. If it is desired to store the hierarchy in quantized format, it is better to have the information of the dilated AABB during the build, since it results in a SAH estimate that is true for the final tree, as opposed to the case where quantization is applied as post-processing.

Propagation centroid box

Another problem that is sensitive to the level of precision that varies between parent and child items is the determination and propagation of the centroid box for object segmentation. In the construction process, the centroid box is maintained during binning so that it can be propagated to each new child node for binning operations in that new child. To avoid floating point arithmetic, the centroid is calculated based on the minimum and maximum coordinates of the quantized AABB. Depending on the relative distance of the full precision minimum and maximum coordinates to their quantized locations, the centroid may be "pulled" up or down when calculated. For example, even rounding down during midpoint calculation, the centroid can be rounded "up" if the minimum coordinate of the box is already close to its quantized position, and the full-precision maximum coordinate is much farther from its quantized position.

To solve the problem, the AABB point joint operation is plain

A build-up shaped heart box. Once the segmentation is selected and the centroid box to be propagated is determined, it can be expanded by one unit in each direction for each axis. This solves all the ambiguities inherent in the computation of the quantization. Once the segmentation plane is determined, the associated centroid box can be transformed to the local grid of sub-items as shown in the following program code sequence:

spatial segmentation

An important feature of the high quality BVH builder is spatial partitioning, which provides a way to eliminate overlap of siblings, which may otherwise be unavoidable. Such overlap can have an adverse impact on traversal performance.

However, spatial partitioning of triangles in a locally reduced-precision space presents a significant challenge that does not arise in a full-precision builder: triangles in the current node that have been previously segmented in the ancestor node may have vertices located outside the local grid. Therefore, we cannot represent these vertices in NB bit space at all.

Instead of full triangle segmentation, one embodiment implements a simple and inexpensive method that can yield acceptable results. To enable space partitioning, this embodiment first quantizes the AABB of the triangle in NV bit space, clips it to the node bounding box, and partitions the NB bit box bins into nodes. We bin the minimum and maximum coordinates of the AABB into nodes and can perform spatial segmentation by segmenting the AABB relative to the segmentation planes it overlaps.

Since an interactive builder is desirable, a hard limit on the number of new references that can be generated due to spatial partitioning can be introduced. Such features are common to multiple fast spatial segmentation builders. Each space partition is performed, which lowers the remaining quota of the space partition. The distribution of the remaining split quotas is determined when two new child nodes are generated. In one embodiment, the distribution is performed in proportion to the SAH cost of the child node. Higher cost child nodes will therefore receive more partitioned quotas.

Over the hard quota on new references generated during build, space partitioning attempts limited to nodes that handle certain attributes are bounded. In addition, one embodiment combines this with a hard-split quota. Observations reveal that with hard quotas for new references, many spatial splits in the tree that never end up are attempted. For example, if a large number of primitives are referenced at a node, but the residual budget for partitioning is very small relative to this large number, then it is likely that spatial partitioning will not be possible, since more than a small number of new references will likely be created. For efficiency purposes, segmentation attempts that are unlikely to be feasible may not be allowed.

Calculating SAH

Once binning is completed as object segmentation binning or spatial segmentation binning, SAH is determined for each potential segmentation plane. In one implementation, SAH can be determined entirely in unsigned integers by calculating the surface area of the bin along with the bin count. To calculate this, the same technique involving both start and end bins is used for both object segmentation and spatial segmentation. These may be efficiently unified with the hardware implementations described herein. Searching for candidate planes is inherently supported only on the longest axis of the box, and if desired, on all three axes.

As with the other stages, this step may be modified from a conventional full-precision builder. Wald et al [33] also reported the disposition of this situation in his reduced precision builder. Additional factors relate to calculating the surface area. The index for each of the coordinate axes in the local grid may have a different value. Thus, the units of measurement are potentially different across the axis. To calculate the surface area value, we must obtain each length in the same unit.

To address this, all values are expressed relative to the maximum unit (maximum exponent) across the three axes. An alternative approach would be to express the length of the box in minimum units (minimum exponent), but this would require a wider arithmetic operation. Furthermore, no quality degradation was observed from using the larger index. The value may be shifted down from the axis with a smaller index by the difference between the indices and at least one unit of length is forced for any length. Once the surface area is obtained, it is multiplied by the number of primitives within the AABB when calculating SAH. The following code sequence specifies how the surface area is calculated in one embodiment:

Node output

Since the local grid is aligned to the quantization scheme employed for traversal in Vaidyanathan [29], direct output of the level of incremental coding can be easily achieved. For example, in one embodiment, this is accomplished by defining a reuse mask by checking the shared planes as in FIG. 35, inferring the new quantized planes by directly using the quantized bounding boxes of the local grid, and by setting the leaf node flags and the correct child pointers appropriately.

Framework

Fig. 37 illustrates one embodiment of an architecture for implementing the reduced-precision BVH construction techniques described herein. In addition to reducing precision arithmetic, this embodiment includes a lossless memory compression circuit 3705 for achieving lossless memory bandwidth compression, similar to implementations often employed in GPUs for improving scalability and reducing power consumption. In one embodiment, the lossless memory compression logic 3705 compresses data being written to the main memory 3700 and decompresses data being read from the main memory 3700.

The illustrated architecture includes a BVH construction unit 0-n within BVH builder core 3030 requesting data from a memory/quantization front end 3715, which memory/quantization front end 3715 contains or is coupled to a large Last Level Cache (LLC) 3710. BVH construction units 0-n therefore only always work with quantized data generated by quantization front-end 3715. In addition, one embodiment includes an L1 index cache 3725 and an L1 vertex cache 3026 to cache triangle indices and vertices, respectively.

Vertex cache

Different techniques may be used to cache vertices in L1 vertex cache 3026 and LLC 3710. In one embodiment, full precision vertices are cached in both the last level cache 3710 and the L1 caches 3725 and 3726. In this implementation, quantization is performed after data is read from cache 3725-3726.

Alternatively or additionally, the separation of the quantizations into the global and local grids allows for a second caching scheme. Since globalbitspaxis of precision constants can be arbitrarily set, it is possible to limit the total size (NV) of the vertices to a small "record" comprising, for example, 64 bits. This record is used and if the local grid implies a higher level of precision, a higher degree of quantization occurs rather than allowing the globalbitsbertpersaxis to be exceeded. One advantage of generating such small records is the ability to cache these records for BVH constructs rather than the full precision floating point values, which may be much larger. This amounts to lossy compression of the vertices, but if the local grid exceeds precision, this will likely only have an adverse effect on the bottom of the tree. Since the algorithm is generalized to any value of globalbitspraxis, different levels of precision can be used to construct different parts of the tree. At the top of the tree, less precision is required, and thus small records may be sufficient at those levels. The larger record size can then be used to construct lower levels of the tree to prevent additional quantization errors at these levels.

One embodiment employs a combination of these two caching schemes, where quantization occurs between the last level cache 3710 and the L1 caches 3725-3726. In addition, in caching quantized vertices, vertices pre-transformed by originTransform of the global grid can be cached, giving unsigned values (e.g., as in fig. 34D). Then, only the originTransform of the local grid is applied before quantization of the vertices to the local grid, thereby reducing the overall quantization overhead.

Embodiments of the present invention provide a number of advantages over existing implementations. In particular, the described embodiments allow for constructing high quality spatially partitioned BVHs entirely within the reduced precision space, greatly reducing the hardware cost of fixed function implementation. The architecture described with respect to fig. 37 includes a first hardware-based BVH builder that supports spatial partitioning of triangles, and lossless compression and caching mechanisms to reduce memory bandwidth are novel bandwidth saving measures not found in any other BVH builder. In addition, unlike other implementations, certain embodiments described herein allow for the direct output of a hierarchy of delta codes.

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in embodiments described herein, the term "engine" or "module" or "logic" may refer to, be part of, or encompass the following: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. In embodiments, the engine, module, or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware, and software.

Embodiments of the invention may include various steps that have been described above. These steps may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

Examples of the invention

The following are example implementations of different embodiments of the present invention.

Example 1. an apparatus, comprising: a memory to store graphics data for a scene, the graphics data containing a plurality of primitives in the scene at a first precision; a geometric quantizer to read vertices of the primitive at the first precision and adaptively quantize the vertices of the primitive to a second precision associated with a first local coordinate grid of a first BVH node located within a global coordinate grid, the second precision being lower than the first precision; a BVH builder to determine coordinates for a child node of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, the BVH builder to determine final coordinates for the child node based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the child nodes.

Example 2. the apparatus of example 1, wherein the first precision comprises a 32-bit single precision floating point precision.

Example 3. the apparatus of example 1, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

Example 4. the apparatus of example 1, wherein the BVH builder is to construct the global coordinate grid by conservatively aligning the minimum and maximum coordinates of the bounding box for the scene to the first precision.

Example 5 the apparatus of example 1, wherein the child node comprises a first child node and a second child node, and wherein the geometry quantizer is to construct a second local coordinate grid and a third local coordinate grid for the first child node and the second child node, respectively, by identifying one or more planes from the first child node and/or the second child node to be shared with the first BVH node.

Example 6 the apparatus of example 5, wherein constructing the second local coordinate grid further comprises replacing values of one or more of the planes from the first child node and/or the second child node with corresponding values associated with corresponding ones of the first BVH nodes.

Example 7. the apparatus of example 1, wherein the BVH builder is to select between non-spatial segmentation binning or spatial segmentation binning based on a comparison of results generated by the non-spatial segmentation binning and spatial segmentation binning.

Example 8 the apparatus of example 7, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

Example 9. the apparatus of example 8, wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.

Example 10 the apparatus of example 1, further comprising: a lossless memory compression circuit coupled to the memory, the lossless memory compression circuit to perform lossless compression on uncompressed graphics data to generate the graphics data stored in the memory, and to perform lossless decompression on the graphics data in response to a memory request for the graphics data to generate uncompressed graphics data.

Example 11. the apparatus of example 10, further comprising: a first cache to store vertices of the primitives at the first precision, the geometry quantizer to read the vertices from the first cache to perform the adaptive quantization of the vertices to the second precision; and a second cache to store the vertex at the second precision, wherein the BVH builder is to read the vertex from the second cache to determine coordinates of child nodes of the first BVH node.

Example 12. a method, comprising: receiving graphics data for a scene, the graphics data containing a plurality of primitives in the scene at a first precision; reading vertices of the primitive at the first precision; adaptively quantizing the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node located within a global coordinate grid, the second precision being lower than the first precision; determining coordinates of a child node of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, wherein final coordinates are determined for the child node based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the child nodes.

Example 13. the method of example 12, wherein the first precision comprises a 32-bit single precision floating point precision.

Example 14. the method of example 12, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

Example 15 the method of example 12, further comprising: constructing the global coordinate grid by conservatively aligning minimum and maximum coordinates of bounding boxes for the scene to the first precision.

Example 16 the method of example 12, wherein the child node includes a first child node and a second child node, and wherein adaptively quantizing further comprises: constructing a second and third local coordinate grid for the first and second child nodes, respectively, by identifying one or more planes from the first and/or second child nodes to be shared with the first BVH node.

The method of example 16, wherein constructing the second local coordinate grid further comprises: replacing values of one or more of the planes from the first child node and/or the second child node with corresponding values associated with corresponding planes in the first BVH node.

Example 18. the method of example 12, further comprising: selecting between non-spatial segmentation binning or spatial segmentation binning based on a comparison of results generated by the non-spatial segmentation binning and spatial segmentation binning.

Example 19 the method of example 18, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

The method of example 19, wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.

An example 21. a machine-readable medium having program code stored thereon, which when executed by a machine, causes the machine to perform operations comprising: receiving graphics data for a scene, the graphics data including a plurality of primitives positioned in the scene within a global coordinate grid with a first precision; reading vertices of the primitive at the first precision; adaptively quantizing the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node, the second precision being lower than the first precision, wherein the local coordinate grid is associated with a location within the global coordinate grid of the first precision; determining coordinates of a child node of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, wherein final coordinates are determined for the child node based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the child nodes.

Example 22 the machine-readable medium of example 21, wherein the first precision comprises a 32-bit single precision floating point precision.

Example 23 the machine-readable medium of example 21, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

Example 24 the machine-readable medium of example 21, further comprising program code to cause the machine to perform operations comprising: constructing the global coordinate grid by conservatively aligning minimum and maximum coordinates of bounding boxes for the scene to the first precision.

Example 25 the machine-readable medium of example 21, wherein the child node includes a first child node and a second child node, and wherein adaptively quantizing further comprises: constructing a second and third local coordinate grid for the first and second child nodes, respectively, by identifying one or more planes from the first and/or second child nodes to be shared with the first BVH node.

Example 26 the machine-readable medium of example 25, wherein constructing the second local coordinate grid further comprises: replacing values of one or more of the planes from the first child node and/or the second child node with corresponding values associated with corresponding planes in the first BVH node.

Example 27 the machine-readable medium of example 21, further comprising program code to cause the machine to perform operations comprising: selecting between non-spatial segmentation binning or spatial segmentation binning based on a comparison of results generated by the non-spatial segmentation binning and spatial segmentation binning.

Example 28 the machine readable medium of example 27, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

Example 29 the machine-readable medium of example 28, wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.

As described herein, the instructions may relate to a particular configuration of hardware, such as an Application Specific Integrated Circuit (ASIC) configured to perform certain operations or having predetermined functionality, or software instructions stored in a memory embodied in a non-transitory computer readable medium. Thus, the techniques illustrated in the figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or over a network with other electronic devices) code and data using a computer machine-readable medium, such as a non-transitory computer machine-readable storage medium (e.g., a magnetic disk, an optical disk, a random access memory, a read-only memory, a flash memory device, a phase change memory) and a transitory computer machine-readable communication medium (e.g., an electrical, optical, acoustical or other form of propagated signals, such as carrier waves, infrared signals, digital signals, etc.).

Additionally, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The set of processors is typically coupled to other components through one or more buses and bridges (also referred to as bus controllers). The storage devices and the signals carrying the network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the memory device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of the electronic device. Of course, one or more portions of embodiments of the invention may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In certain instances, well-known structures and functions have not been described in detail so as not to obscure the subject matter of the present invention. Therefore, the scope and spirit of the present invention should be judged in terms of the claims which follow.

Claims

1. An apparatus, comprising:

a memory to store graphics data for a scene, the graphics data containing a plurality of primitives in the scene at a first precision;

a geometric quantizer to read vertices of the primitive at the first precision and adaptively quantize the vertices of the primitive to a second precision associated with a first local coordinate grid of a first BVH node located within a global coordinate grid, the second precision being lower than the first precision;

a BVH builder to determine coordinates for a child node of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, the BVH builder to determine final coordinates for the child node based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the child nodes.

2. The apparatus of claim 1, wherein the first precision comprises a 32-bit single precision floating point precision.

3. The apparatus of claim 1, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

4. The apparatus of claim 1, wherein the BVH builder is to construct the global coordinate grid by conservatively aligning minimum and maximum coordinates of bounding boxes for the scene to the first precision.

5. The apparatus of claim 1, wherein the child node comprises a first child node and a second child node, and wherein the geometry quantizer is to construct a second local coordinate grid and a third local coordinate grid for the first child node and the second child node, respectively, by identifying one or more planes from the first child node and/or the second child node to be shared with the first BVH node.

6. The apparatus of claim 5, wherein constructing the second local coordinate grid further comprises replacing values of one or more of the planes from the first child node and/or the second child node with corresponding values associated with corresponding ones of the first BVH nodes.

7. The apparatus of claim 1, wherein the BVH builder is to select between non-spatial binning or spatial binning based on a comparison of results generated by the non-spatial and spatial binning.

8. The apparatus of claim 7, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

9. The apparatus of claim 8, wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.

10. The apparatus of claim 1, further comprising:

a lossless memory compression circuit coupled to the memory, the lossless memory compression circuit to perform lossless compression on uncompressed graphics data to generate the graphics data stored in the memory, and to perform lossless decompression on the graphics data in response to a memory request for the graphics data to generate uncompressed graphics data.

11. The apparatus of claim 10, further comprising:

a first cache to store vertices of the primitives at the first precision, the geometry quantizer to read the vertices from the first cache to perform the adaptive quantization of the vertices to the second precision; and

A second cache to store the vertex at the second precision, wherein the BVH builder is to read the vertex from the second cache to determine coordinates of child nodes of the first BVH node.

12. A method, comprising:

receiving graphics data for a scene, the graphics data containing a plurality of primitives in the scene at a first precision;

reading vertices of the primitive at the first precision;

adaptively quantizing the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node located within a global coordinate grid, the second precision being lower than the first precision;

determining coordinates of a child node of the first BVH node by performing non-spatial binning or spatial binning for the first BVH node using a primitive associated with the first BVH node, wherein final coordinates are determined for the child node based at least in part on an evaluation of surface areas of different bounding boxes generated for each of the child nodes.

13. The method of claim 12, wherein the first precision comprises a 32-bit single precision floating point precision.

14. The method of claim 12, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

15. The method of claim 12, further comprising:

constructing the global coordinate grid by conservatively aligning minimum and maximum coordinates of bounding boxes for the scene to the first precision.

16. The method of claim 12, wherein the child node comprises a first child node and a second child node, and wherein adaptively quantizing further comprises:

constructing a second and third local coordinate grid for the first and second child nodes, respectively, by identifying one or more planes from the first and/or second child nodes to be shared with the first BVH node.

17. The method of claim 16, wherein constructing the second local coordinate grid further comprises:

replacing values of one or more of the planes from the first child node and/or the second child node with corresponding values associated with corresponding planes in the first BVH node.

18. The method of claim 12, further comprising:

Selecting between non-spatial segmentation binning or spatial segmentation binning based on a comparison of results generated by the non-spatial segmentation binning and spatial segmentation binning.

19. The method of claim 18, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

20. The method of claim 19 wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.

21. A machine-readable medium having program code stored thereon, which when executed by a machine, causes the machine to perform operations comprising:

receiving graphics data for a scene, the graphics data including a plurality of primitives positioned in the scene within a global coordinate grid with a first precision;

reading vertices of the primitive at the first precision;

adaptively quantizing the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node, the second precision being lower than the first precision, wherein the local coordinate grid is associated with a location within the global coordinate grid of the first precision;

22. The machine-readable medium of claim 21, wherein the first precision comprises a 32-bit single precision floating point precision.

23. The machine-readable medium of claim 21, wherein the second precision comprises an 8-bit or 16-bit unsigned integer precision.

24. The machine-readable medium of claim 21, further comprising program code to cause the machine to perform operations comprising:

25. The machine-readable medium of claim 21, wherein the child node comprises a first child node and a second child node, and wherein adaptively quantizing further comprises:

26. The machine-readable medium of claim 25, wherein constructing the second local coordinate grid further comprises:

27. The machine-readable medium of claim 21, further comprising program code to cause the machine to perform operations comprising:

28. The machine-readable medium of claim 27, wherein the non-spatial binning comprises object binning, wherein to perform the object binning, the geometric quantizer is to determine a centroid box that encompasses a plurality of centroids of the primitives and use the centroid box to create one or more bins.

29. The machine-readable medium of claim 28 wherein the centroid box is stored and propagated from the first BVH node to the child node to be used for binning operations within the child node.