CN111787320B - Transform coding system and method - Google Patents
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- CN111787320B CN111787320B CN202010632429.8A CN202010632429A CN111787320B CN 111787320 B CN111787320 B CN 111787320B CN 202010632429 A CN202010632429 A CN 202010632429A CN 111787320 B CN111787320 B CN 111787320B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
- H04N19/122—Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/186—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
Abstract
The invention discloses a transform coding system and a method, which are applied to video coding and decoding, wherein the system comprises the following steps: the device comprises an input conversion module, a judgment module and an output module; the judgment module is respectively connected with the input conversion module and the output module; wherein the input transformation module comprises a plurality of first buffers (ram) and a plurality of second buffers (ram), and the plurality of first buffers (ram) are used for buffering one-dimensional DCT transformation results in the X direction; the plurality of second buffers (ram) are used for buffering one-dimensional IDCT transformation results in the Y direction. Therefore, according to the embodiment of the application, the input transformation module uses a plurality of first buffers (ram) and a plurality of second buffers (ram) for buffering the transformation results, so that the chip size of the video encoder is reduced.
Description
Technical Field
The present invention relates to the field of chip implementation techniques for video encoders, and in particular, to a transform coding system and method.
Background
In recent years, with the popularization of high definition and ultra-high definition videos, the amount of original video data is increased sharply, great pressure is brought to storage and transmission, and how to further improve the compression efficiency of video coding is a crucial problem.
In the conventional implementation mode of encoding a pixel block in a video at present, four independent encoding modules are used for encoding the pixel block in the video, each encoding module is used for implementing a luminance block of a 1024-point pixel image with 32 points x32 points, a luminance block of a 256-point pixel image with 16 points x16 points is implemented by using one encoding module, a chrominance block of an image of a 256-point pixel block with 16 points x16 points is implemented by using one encoding module, a chrominance block of an 8x8 image is implemented by using one encoding module, and when the four independent encoding modules encode the pixel block in the video, a conventional latch is used for data caching. Because the traditional encoding mode adopts four similar modules for encoding, a latch is used for data caching during caching, and the chip volume of the video encoder is increased.
Disclosure of Invention
The embodiment of the application provides a transformation coding system and a method. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
In a first aspect, an embodiment of the present application provides a transform coding system, where the system includes:
the device comprises an input conversion module, a judgment module and an output module; wherein the content of the first and second substances,
the judgment module is respectively connected with the input conversion module and the output module; wherein the content of the first and second substances,
the input transformation module comprises a plurality of first buffers (ram) and a plurality of second buffers (ram), wherein the first buffers (ram) are used for buffering one-dimensional DCT transformation results in the X direction; the plurality of second buffers (ram) are used for buffering one-dimensional IDCT transformation results in the Y direction.
Optionally, the input transformation module further includes a residual error generator, a first DCT transformer, a second DCT transformer, a first IDCT transformer, and a second IDCT transformer; the residual error generator, the first DCT transformer, the first caches (ram), the second DCT transformer, the first IDCT transformer, the second caches (ram) and the second IDCT transformer are electrically connected in sequence.
Optionally, the first DCT transformer is an X-direction DCT transformer in a coordinate axis of the video image, and the second DCT transformer is a Y-direction DCT transformer in the coordinate axis.
Optionally, the first IDCT transformer is a Y-direction DCT transformer in a coordinate axis of the video image, and the second IDCT transformer is an X-direction DCT transformer in the coordinate axis.
Optionally, the input transform module is configured to obtain different size types of blocks, process the blocks to generate transform coefficients and reconstructed data; the judging module is used for generating coding cost after judging the current coding quality according to the transformation coefficient and the reconstruction data; and the output module outputs the transformation coefficient and the reconstruction data when the coding cost is less than a preset threshold value.
In a second aspect, an embodiment of the present application provides a transform coding method, including:
an input transformation module acquires blocks of different size types to process and generate transformation coefficients and reconstruction data;
the judgment module judges the current coding quality according to the transformation coefficient and the reconstruction data and then generates coding cost;
and the output module outputs the transformation coefficient and the reconstruction data according to the coding cost.
Optionally, the obtaining, by the input transform module, block processing of different size types to generate transform coefficients and reconstruction data includes:
a residual error generator acquires blocks of different size types and generates residual errors to be coded corresponding to the blocks of different size types;
the first DCT transformer carries out one-dimensional DCT transformation in the X direction on the residual errors to be coded corresponding to the blocks with different size types to generate one-dimensional DCT transformation results in the X direction;
a plurality of first buffers (ram) buffers the X-direction one-dimensional DCT transform results.
Optionally, after the buffering the one-dimensional DCT transform result in the X direction by the plurality of first buffers (ram), the method further includes:
the second DCT transformer carries out one-dimensional DCT transformation in the Y direction on the one-dimensional DCT transformation result in the X direction to generate a two-dimensional DCT transformation coefficient of a residual error to be coded;
quantizing the two-dimensional DCT transform coefficient of the residual error to be coded by a second DCT transformer to generate a transform coefficient;
the second DCT transformer outputs the transform coefficient.
Optionally, after the second DCT transformer outputs the transform coefficient, the method further includes:
the first IDCT converter performs inverse quantization on the transform coefficient, performs one-dimensional IDCT transform in the Y direction, and generates a one-dimensional IDCT transform result in the Y direction;
a plurality of second caches (ram) cache the one-dimensional IDCT conversion result in the Y direction;
the second IDCT converter carries out the IDCT conversion in the X direction on the one-dimensional IDCT conversion result in the Y direction to generate reconstructed data corresponding to the residual error to be coded;
the second IDCT transformer outputs the reconstructed data.
Optionally, the outputting, by the output module, the transform coefficient and the reconstruction data according to the coding cost includes:
and when the coding cost is less than a preset threshold value, outputting the transformation coefficient and the reconstruction data.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
in the embodiment of the application, a video encoder obtains blocks of different sizes and types through an input transformation module to process and generate transformation coefficients and reconstruction data, then generates coding cost after judging the current coding quality according to the transformation coefficients and the reconstruction data based on a judgment module, and finally outputs the transformation coefficients and the reconstruction data according to the coding cost through an output module. In the coding of the video pixel block, the functions realized by the traditional four independent coding modules are realized by one module, and then (ram) is used as cache in the data cache to replace a traditional register, so that the chip volume of the video coder is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic structural diagram of a transform coding system according to an embodiment of the present application;
fig. 2 is a schematic diagram of a transform coding method according to an embodiment of the present application;
fig. 3 is a process diagram of a transform coding process provided by an embodiment of the present application;
fig. 4 is a flowchart illustrating another transform coding method according to an embodiment of the present application.
Detailed Description
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
So far, in the encoding of video encoding and decoding, four independent encoding modules are used to encode pixel blocks in a video, each of which is implemented by using one encoding module for a luminance block of a 1024-point pixel image with 32 points x32 points, one encoding module for a luminance block of a 256-point pixel image with 16 points x16 points, one encoding module for a chrominance block of an image of a 256-point pixel block with 16 points x16 points, one encoding module for a chrominance block of an 8x8 image, and when the four independent encoding modules encode the pixel blocks in the video, a conventional latch is used to perform data buffering. Because the traditional encoding mode adopts four similar modules for encoding, a latch is used for data caching during caching, and the chip volume of the video encoder is increased. To this end, the present application provides a transform coding system and method to solve the above-mentioned problems associated with the related art. In the technical solution provided by the present application, in the encoding of a video pixel block, the functions implemented by the conventional four independent encoding modules are implemented by one module, and then (ram) is used as a cache in a data cache to replace a conventional register, so that the chip volume of a video encoder is reduced.
Referring to fig. 1, fig. 1 is a schematic diagram of a system for transform coding applied to video coding and decoding, the system including an input transform module, a determination module 08, and an output module 09, where the input transform module includes a residual error generator 01, a first DCT transformer 02 (i.e., X-to-DCT transform 02), a plurality of first buffers (RAM)03 (i.e., 32 buffers (RAM)03), a second DCT transformer 04 (Y-to-DCT transform 04), a first IDCT transformer 05 (i.e., Y-to-IDCT transform 05), a plurality of second buffers (RAM)06 (i.e., 32 buffers (RAM)06), and a second IDCT transformer 07 (i.e., X-to-IDCT transform 07), where the determination module 08 is respectively connected to the input transform module and the output module 09.
Further, the residual error generator 01, the first DCT transformer 02, the plurality of first buffers (ram)03, the second DCT transformer 04, the first IDCT transformer 05, the plurality of second buffers (ram)06, and the second IDCT transformer 07 are electrically connected in sequence.
Further, a plurality of first buffers (ram)03 are connected to the first DCT transformer 02 at one end and to the second DCT transformer 04 at the other end; the first DCT transformer 02 is an X-direction DCT transformer in the coordinate axis of the video image, and the second DCT transformer 04 is a Y-direction DCT transformer in the coordinate axis of the video image.
Further, a plurality of second buffers (ram)06 are connected to the first IDCT transformer 05 at one end and the second IDCT transformer 07 at the other end, wherein the first IDCT transformer 05 is a Y-direction DCT transformer in the coordinate axis of the video image, and the second IDCT transformer 07 is an X-direction DCT transformer in the coordinate axis of the video image.
Further, the input transformation module is used for obtaining different size types of blocks to process and generate transformation coefficients and reconstruction data. And the judging module 08 is used for generating coding cost after judging the current coding quality according to the transformation coefficient and the reconstruction data. And the output module 09 outputs the transformation coefficient and the reconstruction data when the coding cost is less than a preset threshold value.
Specifically, the embodiment of the present application is composed of a residual generator 01, an X-to-DCT transform 02, a 32-block buffer (ram)03, a Y-to-DCT transform 04, a Y-to-IDCT transform 05, a 32-block buffer (ram)06, an X-to-IDCT transform 07, a judgment module 08, and an output module 09. Wherein 01,02,04,05,07,08 and 09 modules work in a pipeline mode. In the embodiment of the application, firstly, a Y block of 32x32, a Y block of 16x16, a U/V block of 16x16 and a U/V block of 8x8 are selected as input according to a block type selection signal, and are subjected to residual error generation DCT (discrete cosine transformation) and IDCT transformation judgment modules, and finally, transformation coefficients and reconstruction output of a corresponding input block are output.
In the embodiment of the application, a video encoder obtains blocks of different sizes and types through an input transformation module to process and generate transformation coefficients and reconstruction data, then generates coding cost after judging the current coding quality according to the transformation coefficients and the reconstruction data based on a judgment module, and finally outputs the transformation coefficients and the reconstruction data according to the coding cost through an output module. In the coding of the video pixel block, the functions realized by the traditional four independent coding modules are realized by one module, and then (ram) is used as cache in the data cache to replace a traditional register, so that the chip volume of the video coder is reduced.
The transform coding method provided by the embodiments of the present application will be described in detail below with reference to fig. 2 to 4. The method may be implemented in dependence on a computer program, operable on a transform coding system based on the von neumann architecture. The computer program may be integrated into the application or may run as a separate tool-like application. The transform coding system in the embodiment of the present application may be a video encoder.
Referring to fig. 2, a flow chart of a transform coding method is provided for an embodiment of the present application. As shown in fig. 2, the method of the embodiment of the present application may include the steps of:
s101, an input transformation module obtains blocks of different size types to process and generate transformation coefficients and reconstruction data;
the input transformation module is a module for processing and transforming the acquired blocks with different size types.
Generally, the input transform module includes a residual generator, an X-directional DCT transformer, a 32-block buffer (ram), a Y-directional DCT transformer, a Y-directional IDCT transformer, a 32-block buffer (ram), and an X-directional IDCT transformer.
In the embodiment of the application, a residual error generator is adopted to obtain blocks with different size types, generate residual errors to be coded corresponding to the blocks with different size types, an X-direction DCT converter is used for carrying out X-direction one-dimensional DCT transformation on the residual errors to be coded corresponding to the blocks with different size types to generate an X-direction one-dimensional DCT transformation result, a 32-block cache (ram) is adopted for caching the X-direction one-dimensional DCT transformation result, a Y-direction DCT transformer is adopted for carrying out Y-direction one-dimensional DCT transformation on the X-direction one-dimensional DCT transformation result to generate a two-dimensional DCT transformation coefficient of the residual errors to be coded, a second DCT transformer is adopted for quantizing the two-dimensional DCT transformation coefficient of the residual errors to be coded to generate a transformation coefficient, the transformation coefficient is output by a second DCT transformer, a Y-direction IDCT transformer is adopted for carrying out inverse quantization on the transformation coefficient, and Y-direction one-dimensional IDCT transformation is carried out to generate a Y-direction one-dimensional IDCT transformation result, and caching the one-dimensional IDCT conversion result in the Y direction by adopting 32 blocks of cache (ram), then carrying out the IDCT conversion in the X direction on the one-dimensional IDCT conversion result in the Y direction by adopting an X-direction IDCT converter to generate reconstructed data corresponding to the residual error to be coded, and finally outputting the reconstructed data by adopting the X-direction IDCT converter.
In a possible implementation mode, firstly, a residual generator is used for obtaining different types of blocks, generating residual errors to be coded of the blocks, then an X-direction DCT converter is used for carrying out X-direction one-dimensional DCT transformation on the residual errors, generating an X-direction transformation result, then a plurality of caches (ram)03 are used for caching the X-direction one-dimensional DCT transformation result, then a Y-direction DCT converter is used for carrying out Y-direction one-dimensional DCT transformation on the X-direction one-dimensional DCT transformation result, generating a two-dimensional DCT transformation coefficient of the residual errors to be coded, quantizing the two-dimensional DCT transformation coefficient, outputting the transformation coefficient (namely the transformation coefficient to be output), then a Y-direction IDCT converter is used for carrying out inverse quantization on the transformation coefficient, and carrying out Y-direction one-dimensional inverse DCT transformation, generating a Y-direction one-dimensional inverse DCT transformation result, finally, a plurality of caches (ram) are used for caching the Y-direction one-dimensional inverse DCT transformation result, and an X-direction inverse DCT transformation is carried out on the Y-direction one-dimensional inverse transformation result, and finally outputting a two-dimensional inverse DCT conversion result after inverse quantization of the conversion coefficient. The result is the reconstructed data corresponding to the residual to be coded.
S102, a judgment module judges the current coding quality according to the transformation coefficient and the reconstruction data and then generates coding cost;
in a possible implementation manner, based on the transform coefficient and the reconstruction data obtained in step S101, the determining module determines the quality of the current encoding according to the transform coefficient, the reconstruction data, and the like to generate an encoding cost, and finally determines whether to output an encoding result. And when the coding cost is less than a preset threshold value, outputting the transformation coefficient and the reconstruction data.
And S103, the output module outputs the transformation coefficient and the reconstruction data according to the coding cost.
For example, as shown in fig. 3, fig. 3 is a schematic diagram of a transform coding process provided in an embodiment of the present application, first, blocks of different size types, such as a Y block of 32x32, a Y block of 16x16, a U/V block of 16x16, and a U/V block of 8x8, are obtained as inputs by a residual generator. Where a Y block of 32x32 is a 1024-point pixel block of 32 points x32 points, Y refers to the brightness of the image. Where a Y block of 16x16 is a 256-point pixel block of 16 points x16 points, Y refers to the brightness of the image. Wherein a U/V block of 16x16 is a 256-point pixel block of 16 points x16 points, and U/V is the chroma of the image. Wherein the U/V block of 8x8 is a 64-point pixel block of 8 points x8 points, and U/V is the chroma of the image.
When the residual error generator obtains blocks of different size types, the blocks of different size types are processed to generate residual errors to be coded corresponding to the blocks of different size types, then the residual errors to be coded corresponding to the blocks of different size types are input into an X-direction DCT converter, the X-direction DCT converter receives the residual errors to be coded corresponding to the blocks of different size types and then carries out one-dimensional DCT conversion in the X direction to generate a conversion result in the X direction, wherein the DCT is discrete cosine conversion, and the X direction is the row direction of the video image. When the line direction conversion result of the video image is generated, the line direction conversion result of the video image is input to a 32-block buffer (ram) for buffering. And acquiring a one-dimensional DCT conversion result of the video image in the row direction through the Y-direction DCT converter, performing one-dimensional DCT conversion in the Y direction, generating a two-dimensional DCT conversion coefficient of the residual error to be coded, quantizing the two-dimensional DCT conversion coefficient, and outputting the conversion coefficient. I.e. the transform coefficients to be output. Where the Y direction is the column direction of the video image.
And then inverse quantization is carried out on the transform coefficient through a Y-direction IDCT converter, and one-dimensional inverse DCT conversion in the Y direction is carried out to generate a one-dimensional inverse DCT conversion result in the Y direction. The IDCT transform is inverse discrete cosine transform, and the one-dimensional inverse DCT transform result in the Y direction is finally buffered in a 32-block buffer (ram).
And then the one-dimensional inverse DCT conversion result in the Y direction is subjected to inverse DCT conversion in the X direction through an X-direction IDCT converter, and finally a two-dimensional inverse DCT conversion result after inverse quantization of the conversion coefficient is output. The result is the reconstructed data corresponding to the residual to be coded.
And judging the coding quality of the time through a judging module, determining whether to output a coding result, and finally outputting a transformation coefficient and reconstruction data through an output module when the coding cost is less than a preset threshold value.
In the embodiment of the application, a video encoder obtains blocks of different sizes and types through an input transformation module to process and generate transformation coefficients and reconstruction data, then generates coding cost after judging the current coding quality according to the transformation coefficients and the reconstruction data based on a judgment module, and finally outputs the transformation coefficients and the reconstruction data according to the coding cost through an output module. In the coding of the video pixel block, the functions realized by the traditional four independent coding modules are realized by one module, and then (ram) is used as cache in the data cache to replace a traditional register, so that the chip volume of the video coder is reduced.
Referring to fig. 4, a flow chart of a transform coding method is provided for an embodiment of the present application. As shown in fig. 4, the method of the embodiment of the present application may include the steps of:
s201, a residual error generator acquires blocks of different size types and generates residual errors to be coded corresponding to the blocks of different size types;
s202, the first DCT transformer carries out one-dimensional DCT transformation in the X direction on the residual errors to be coded corresponding to the blocks with different sizes and types to generate one-dimensional DCT transformation results in the X direction;
s203, caching the one-dimensional DCT conversion result in the X direction by a plurality of first caches (ram);
s204, the second DCT transformer carries out one-dimensional DCT transformation in the Y direction on the one-dimensional DCT transformation result in the X direction to generate a two-dimensional DCT transformation coefficient of the residual error to be coded;
s205, quantizing the two-dimensional DCT transform coefficient of the residual error to be coded by a second DCT transformer to generate a transform coefficient;
s206, outputting the transformation coefficient by a second DCT transformer;
s207, the first IDCT converter performs inverse quantization on the transform coefficient, performs one-dimensional IDCT transform in the Y direction, and generates a one-dimensional IDCT transform result in the Y direction;
s208, caching the one-dimensional IDCT conversion result in the Y direction by a plurality of second caches (rams);
s209, the second IDCT converter performs IDCT conversion in the X direction on the one-dimensional IDCT conversion result in the Y direction to generate reconstructed data corresponding to the residual error to be coded;
s210, outputting the reconstruction data by a second IDCT converter;
s211, a judgment module judges the current coding quality according to the transformation coefficient and the reconstruction data and then generates a coding cost;
s212, when the coding cost is smaller than a preset threshold value, outputting the transformation coefficient and the reconstruction data.
In the embodiment of the application, a video encoder obtains blocks of different sizes and types through an input transformation module to process and generate transformation coefficients and reconstruction data, then generates coding cost after judging the current coding quality according to the transformation coefficients and the reconstruction data based on a judgment module, and finally outputs the transformation coefficients and the reconstruction data according to the coding cost through an output module. In the coding of the video pixel block, the functions realized by the traditional four independent coding modules are realized by one module, and then (ram) is used as cache in the data cache to replace a traditional register, so that the chip volume of the video coder is reduced.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.
Claims (3)
1. A transform coding system for video coding and decoding, the system comprising:
the device comprises an input conversion module, a judgment module and an output module; wherein the content of the first and second substances,
the judgment module is respectively connected with the input conversion module and the output module; wherein the content of the first and second substances,
the input transformation module comprises a plurality of first buffers (ram) and a plurality of second buffers (ram), wherein the first buffers (ram) are used for buffering one-dimensional DCT transformation results in the X direction; the plurality of second caches (ram) are used for caching one-dimensional IDCT transformation results in the Y direction;
the input transformation module further comprises a residual error generator, a first DCT transformer, a second DCT transformer, a first IDCT transformer and a second IDCT transformer; the residual error generator, the first DCT transformer, the first caches (ram), the second DCT transformer, the first IDCT transformer, the second caches (ram) and the second IDCT transformer are electrically connected in sequence;
the input transformation module is used for processing the obtained blocks with different sizes and types and then generating transformation coefficients and reconstruction data; the judging module is used for generating coding cost after judging the current coding quality according to the transformation coefficient and the reconstruction data; the output module outputs the transformation coefficient and the reconstruction data when the coding cost is smaller than a preset threshold value;
wherein, the processing the obtained blocks with different size types to generate transformation coefficient and reconstruction data comprises:
a residual error generator acquires blocks of different size types and generates residual errors to be coded corresponding to the blocks of different size types;
the first DCT transformer carries out one-dimensional DCT transformation in the X direction on the residual errors to be coded corresponding to the blocks with different size types to generate one-dimensional DCT transformation results in the X direction;
a plurality of first caches (ram) cache the one-dimensional DCT transform result in the X direction;
wherein after the first caches (ram) cache the X-direction one-dimensional DCT transform result, the method further includes:
the second DCT transformer carries out one-dimensional DCT transformation in the Y direction on the one-dimensional DCT transformation result in the X direction to generate a two-dimensional DCT transformation coefficient of a residual error to be coded;
quantizing the two-dimensional DCT transform coefficient of the residual error to be coded by a second DCT transformer to generate a transform coefficient;
the second DCT transformer outputs the transformation coefficient;
wherein, after the second DCT transformer outputs the transform coefficient, the method further includes:
the first IDCT converter performs inverse quantization on the transform coefficient, performs one-dimensional IDCT transform in the Y direction, and generates a one-dimensional IDCT transform result in the Y direction;
a plurality of second caches (ram) cache the one-dimensional IDCT conversion result in the Y direction;
the second IDCT converter carries out the IDCT conversion in the X direction on the one-dimensional IDCT conversion result in the Y direction to generate reconstructed data corresponding to the residual error to be coded;
the second IDCT transformer outputs the reconstructed data.
2. The transform coding system of claim 1,
the first DCT transformer is an X-direction DCT transformer in a coordinate axis of the video image, and the second DCT transformer is a Y-direction DCT transformer in the coordinate axis.
3. The transform coding system of claim 1,
the first IDCT converter is a Y-direction DCT converter in the coordinate axis of the video image, and the second IDCT converter is an X-direction DCT converter in the coordinate axis.
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| CN102065298B (en) * | 2011-01-05 | 2012-10-24 | 西安电子科技大学 | High-performance macroblock coding implementation method |
| US9747255B2 (en) * | 2011-05-13 | 2017-08-29 | Texas Instruments Incorporated | Inverse transformation using pruning for video coding |
| CN102209243B (en) * | 2011-05-27 | 2012-10-24 | 山东大学 | Depth map intra prediction method based on linear model |
| CN103581670B (en) * | 2013-10-09 | 2015-05-20 | 合一网络技术(北京)有限公司 | H264 self-adaptation intra-frame mode selection code rate estimated rate-distortion optimization method and device thereof |
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| CN103533378A (en) * | 2013-10-09 | 2014-01-22 | 天津大学 | Three-dimensional integer DCT (Discrete Cosine Transform) transformation system on basis of FPGA (Field Programmable Gate Array) and transformation method thereof |
| CN107249130A (en) * | 2017-07-24 | 2017-10-13 | 河南工程学院 | It is a kind of 3 to multiply 3 Integer DCT Transform quantizers for digital video decoding |
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