CN111782566A - High-frequency ground wave radar multichannel high-speed data acquisition device based on PCIe - Google Patents

Abstract

The invention discloses a PCIe-based high-frequency ground wave radar multi-channel high-speed data acquisition device, which comprises an analog front-end circuit, an ADC, an FPGA, a trigger control module, a reference clock module and a DDR, wherein the signal processing flow comprises the following steps: the receiver amplifies the received signals and inputs the amplified signals into the acquisition device, the signals are amplified and balanced by the analog front-end circuit, and then the analog signals are converted into digital signals through the ADC. And performing down conversion on the digital signal output by the ADC by using the FPGA, and caching the processed data into the DDR. And after receiving the trigger signal, the FPGA transmits the data cached in the DDR to the upper computer cache through a PCIe interface in a DMA mode. And finally, the upper computer control center performs signal processing by using the uploaded data to obtain the distance, the speed and the direction of the target, and performs positioning and tracking. The invention has the characteristics of simple frame structure, convenient system debugging, strong device stability and the like.

Description

High-frequency ground wave radar multichannel high-speed data acquisition device based on PCIe

Technical Field

The invention belongs to the field of high-frequency ground wave radar data acquisition and signal processing, relates to a novel high-frequency ground wave radar signal acquisition and processing device, and particularly relates to an acquisition device for connecting a radar receiver and a signal processor.

Background

The high-frequency ground wave radar works at 3-30 MHz, the maximum detection range of the high-frequency ground wave radar can cover 300-500 kilometers, the high-frequency ground wave radar can cover a 200 kilometer exclusive economic area and can realize over-the-horizon detection on a sea surface ship and a low-altitude flying target so as to achieve the effects of monitoring and early warning. The high-frequency ground wave radar is a favorable weapon for monitoring a special economic area, providing remote guarantee for ships and realizing over-the-horizon early warning and detection of targets by virtue of the advantages of large detection distance, wide range, over-the-horizon, all-weather working and the like. Data acquisition of the high-frequency ground wave radar is always a major difficulty and key point of the system, and the system acquires and processes speed, distance and direction information of a target in real time so as to position and track the target. Therefore, in the detection process of the radar, high-speed accurate acquisition and transmission of data are important. Due to interference, noise and energy loss of beyond-the-horizon transmission in the detection process, echo signals received by the antenna are very weak, and in order to better acquire and process the echo signals, the received signals need to be amplified and filtered before being acquired.

With the development of electronic technology, a multichannel high-speed data acquisition system has been developed greatly, and is widely applied to many fields such as radar, optical fiber, communication, sonar, satellite remote sensing and the like. In a high-frequency ground wave radar system, early data acquisition and transmission are realized by a radar receiver and an optical fiber card, the receiver amplifies received antenna echo signals, digital down-conversion processing is carried out by an FPGA through an internal 16-bit analog-to-digital converter (DAC) to obtain digital signals, and the digital signals obtained are transmitted to a signal processor by the optical fiber card. The acquisition and transmission structure has many difficulties and defects, and firstly, the manufacture and debugging of the optical fiber card are particularly complicated. Secondly, the method cannot obtain the original data signal, and the signal received by the signal processor is the signal after the digital down-conversion by the receiver. Finally, in the debugging process of the actual system, once the signal processing result is found to be incorrect, the problem is difficult to find, because the data processing is not completed in the signal processor.

Disclosure of Invention

The invention provides a PCIe-based high-frequency ground wave radar multi-channel high-speed data acquisition device, which aims to solve the problems in data acquisition and transmission of an early high-frequency ground wave radar system in the background art. The invention adopts a new data acquisition and transmission framework, designs a general multi-channel high-speed data acquisition device, obtains original data and solves the difficulty that the problem is difficult to determine in the debugging process. The acquisition device has the characteristics of simple frame structure, convenient system debugging, strong device stability and the like.

The purpose of the invention is realized by the following technical scheme:

the utility model provides a high frequency ground wave radar multichannel high speed Data acquisition device based on PCIe, includes Analog Front End (AFE) circuit, analog-to-digital converter (ADC), Field Programmable Gate Array (FPGA), triggers control module, reference clock module and double speed memory DDR (double Data range RAM), wherein:

the analog front-end circuit is provided with eight input signal channel ports and is used for converting an analog signal from a single-ended signal into a differential signal before the analog signal enters the ADC;

the ADC is a dual-channel ADC chip, the number of the ADC chips is four, the ADC chip is connected with the output end of the analog front-end circuit and the input end of the FPGA and is used for converting analog signals into digital signals;

the FPGA is provided with a JTAG interface and an 8-wire PCIe interface compatible with PCI-2.0 standard, and is used for carrying out down-conversion on the digital signal output by the ADC and caching the processed data into the DDR through a PCIe connector;

the trigger control module is provided with four external trigger input ports for realizing various trigger modes in the system, packaging the acquired data and transmitting the data to the DDR module through an axial flow bus;

the reference clock module comprises an external reference clock and an external sampling clock, the external reference clock is used for providing periodic pulses for the whole system and is provided with an external reference clock input port; the external sampling clock is used for providing sampling parameters for analog-to-digital conversion and is provided with an external sampling clock input port;

the DDR adopts DDR-3 type specification, is connected with the FPGA and the PCIe connector and is used for caching data processed by the FPGA, and the data cached in the DDR is transmitted to the host through the PCIe bus and the DMA transmission architecture.

The signal processing flow of the high-frequency ground wave radar multi-channel high-speed data acquisition device based on PCIe is as follows:

after being received by an antenna, an echo signal is amplified and filtered by a receiver to become a high-frequency narrow-band signal, and after an acquisition device receives an external trigger signal, the high-frequency narrow-band signal is input into the acquisition device;

in the acquisition device, firstly, an analog front-end circuit amplifies and balances, then an analog signal is converted into a digital signal through an ADC (analog to digital converter), the digital signal output by the ADC is subjected to down-conversion by using an FPGA (field programmable gate array), and processed data are cached in a DDR (double data rate); the external reference clock signal provides periodic pulses for various operations of the FPGA, and the clock frequency of the acquisition device and the clock frequency of the receiver are ensured to be homologous;

and thirdly, after receiving the trigger signal, the FPGA transmits the data cached in the DDR to the upper computer cache through a PCIe interface in a DMA mode, and finally, the upper computer control center performs signal processing by using the uploaded data to obtain the distance, the speed and the direction of the target so as to perform positioning and tracking.

Compared with the prior art, the invention has the following advantages:

1. the method can obtain the original echo signal of the high-frequency ground wave radar, is beneficial to inspection and troubleshooting in system debugging, has simpler frame structure compared with the old mode, and has the advantages of convenient implementation and easy operation.

2. The acquisition device has high signal-to-noise ratio and no stray dynamic range, almost no interference among channels and strong stability, and is convenient for signal processing in the later period.

3. The acquisition device of the present invention has eight input channel ports, four external trigger signal ports, an external reference clock port and an external sampling clock port. Meanwhile, the device has a JTAG interface to update an FPGA program and an eight-wire PCIe interface compatible with the PCI-2.0 standard to transmit data. Compared with the multiplexing scheme, the designed system structure effectively avoids the problem of signal crosstalk.

4. The acquisition device of the invention designs the analog front-end circuit, changes the single-end analog signal into a differential signal before entering the analog-to-digital converter, and avoids the signal from being interfered by differential transmission. Meanwhile, the analog front-end circuit has amplification and equalization functions, can eliminate higher harmonics and improve the power factor.

5. The reference clock can be internally defaulted or externally input, the trigger source of the device has a plurality of trigger modes and different trigger conditions, and the device also has a stable and reliable power conversion module.

6. The acquisition device reasonably combines and collocates the analog-digital converter and the FPGA chip with excellent performance, so that the system has strong anti-interference capability and high spurious-free dynamic range.

7. The data transmission of the acquisition device between the PCIe bus and the upper computer adopts a DMA transmission mechanism, and compared with the transmission by using an IP core, the acquisition device has higher average transmission rate and saves the computing resources of the host.

Drawings

Fig. 1 is a block diagram of a high-frequency ground wave radar acquisition device in the present invention.

Fig. 2 is a structural diagram of the multi-channel high-speed data acquisition device in the present invention.

Fig. 3 is a real object diagram of the multi-channel high-speed data acquisition device in the invention.

Fig. 4 is a flow chart of the operation of the multi-channel high-speed data acquisition device in the invention.

Fig. 5 is an internal frame diagram of the acquisition device FPGA.

Fig. 6 is an internal logic diagram of the acquisition device FPGA.

FIG. 7 is a connection diagram of FPGA and PCIe.

Fig. 8 is a schematic diagram of a system clock source.

FIG. 9 is a diagram of a DMA transfer architecture.

Fig. 10 is a diagram showing the results of performance tests of the acquisition device according to the present invention.

Fig. 11 is a diagram showing the results of performance tests of the acquisition device according to the present invention.

Fig. 12 is a diagram showing the results of performance tests of the acquisition device according to the present invention.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings, but not limited thereto, and any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the protection scope of the present invention.

The invention provides a high-frequency ground wave radar multi-channel high-speed data acquisition device based on PCIe (peripheral component interface express), and provides a novel acquisition and transmission framework by utilizing an acquisition and transmission device. The receiver amplifies the received signals and inputs the analog signals into the acquisition device through the SMA transmission line, the acquisition device obtains digital signals through analog-to-digital conversion and digital down-conversion operation, and the digital signals are cached into an upper computer of the signal processor through a DMA transmission mechanism and then subsequent operation is carried out. Compared with the prior art, the frame structure of the system is simpler, easier and easier to operate, and can obtain the original data of the echo signal, and the error of the transmitted signal is checked and judged in the system debugging process, so that the problem can be found more quickly. Besides, the acquisition device also has high signal-to-noise ratio and spurious-free dynamic range, and the interference between multiple channels of the acquisition device is almost zero and the stability is strong.

As shown in fig. 1, the acquisition device is composed of an Analog Front End (AFE) circuit, an analog-to-digital converter (ADC), a Field Programmable Gate Array (FPGA), a trigger control module, a reference clock module, and a double speed memory ddr (double Data rate ram). And (3) system signal processing flow: after the echo signal is received by the antenna, the echo signal is changed into a high-frequency narrow-band signal through the amplification and filtering of the receiver and then is input into the acquisition device. In the acquisition device, the analog signal is firstly amplified and balanced by an analog front-end circuit, and then converted into a digital signal through an ADC (analog-to-digital converter). And secondly, performing down-conversion on the digital signal output by the ADC by using the FPGA, and caching the processed data into the DDR. And after receiving the trigger signal, the FPGA transmits the data cached in the DDR to the upper computer cache through a PCIe interface in a DMA mode. And finally, the upper computer control center performs signal processing by using the uploaded data to obtain the distance, the speed and the direction of the target, and performs positioning and tracking.

As shown in fig. 2 and fig. 3, the PCIe-based high-speed multi-channel data acquisition device has a complex structure, and includes eight input signal channel ports, four external trigger input ports, an external reference clock input port, and an external sampling clock input port. Meanwhile, the test circuit also has a JTAG interface for testing an FPGA internal chip and an 8-wire PCIe interface compatible with the PCI-2.0 standard. A time sequence trigger circuit is further designed in the device and transmits the digital signals to a PCIe interface in the FPGA. In addition, the device adopts 4 two-channel ADC chips to carry out digital processing on the output signal of the 8-channel analog front end. Compared with the multiplexing scheme, the designed system structure can avoid the signal crosstalk problem. Fig. 4 illustrates the workflow of the device, namely: a series of operation processes of opening, initialization, setting mode, channel enabling, resetting and closing of the device.

Considering that high-frequency analog signals in a high-speed data acquisition device are easily interfered by signals, in order to avoid the interference, a system adopts differential signal transmission. It requires that the single-ended signal becomes differential before the analog signal enters the ADC, so a differential amplifier circuit is added before the ADC circuit, which is the role of the analog front-end circuit. When the differential signal encounters interference, the two differential lines are simultaneously influenced, but the voltage difference is not changed greatly, so that the differential signal has better anti-interference performance than a single-ended signal. The differential amplification circuit at the analog front end not only amplifies and balances the input radio frequency signal, but also eliminates higher harmonics and improves the power factor.

The ADC chip is connected with the output of the analog front-end circuit and the input of the FPGA, and plays a vital role in the whole acquisition system. Its input voltage range must meet the output voltage range of the analog front-end circuit. At the same time, the sampling rate of the ADC must meet the nyquist sampling rate, and the output of the ADC must be readable by the FPGA. The acquisition device adopts the general ADS42LB69 which is an analog-digital converter with high linearity, double channels and supporting DDR and LVDS output interfaces. The chip can provide excellent Spurious Free Dynamic Range (SFDR) in a large input frequency range with low power consumption.

The FPGA is widely applied to a high-speed data acquisition card due to the characteristics of high clock frequency, small internal delay, more interfaces, flexible use and the like. The acquisition device adopts the Xilinx FPGA chip Kintex7-XC7K325T to acquire the output signals (amplitude-1.5V, frequency 100 KHz-100 MHz) of the receiver, has stable operation and strong anti-interference capability, and has the functions of data combination, cache, information statistics and the like. As shown in fig. 5, the internal structure of the FPGA mainly includes seven aspects of trigger control, ADC interface, clock manager, embedded CPU, axial flow, DDR and PCIe interface. The internal logic diagram of the FPGA is shown in fig. 6, and includes an AD module, a user module, a trigger control module, a PCIe module, an SPI module, a VFIFO module, and an SOC module. The AD module is connected with the ADC chip and receives data collected by the ADC through the LVDS bus.

The user module has a logic re-development function and provides basic codes for reading and writing registers. The trigger control module is used for realizing various trigger modes in the system, packaging the acquired data and transmitting the data to the DDR module through the axial flow bus. The trigger control module comprises a PCI-E module, an SPI module, a DDR module and an SOC module, wherein: the PCI-E module is mainly used for DMA data transmission between the PC and the FPGA. The SPI module is an SPI main controller and can control various analog front-end chips and relays. The DDR module calls the Xilinx core, drives two sets of DDRs 3 on board, and combines these two sets of DDR3 interfaces into a virtual two sets of FIFO interfaces. The SOC module mainly includes: the software-core processor, the AXI bus controller, the trigger control module and the register interface of the SPI module.

A large amount of logic programming is realized in an FPGA by using Verilog HDL (hardware description language), such as conversion from serial data to parallel data, PCIe (peripheral component interconnect express) transmission bus protocol, realization of data cache, debugging of logic functions, performance test and the like. Finally, the processed data is transmitted to the host through the PCIe connector, as shown in fig. 7.

As shown in fig. 8, the reference clock of the acquisition device has two sources, one from the internal default clock source (100 MHz) and the other from the external input. A Phase Locked Loop (PLL) multiplies the internal sampling clock by the frequency required by the ADC. In addition, the frequency of the external input signal may also be used directly as the ADC sampling clock. The acquisition device supports a plurality of trigger sources, including software triggering, internal pulse triggering, external triggering and the like, wherein a plurality of logic operations can be carried out to obtain a final trigger signal. Meanwhile, different trigger conditions can be set for each trigger source, including falling edge trigger, rising edge trigger, low level trigger, high level trigger, bilateral trigger and the like.

The normal stable operation of the system is not always stable and reliable. The scheme of a power supply system of the current acquisition system is mature, and the normal and stable operation of the system cannot be realized by a stable and reliable power conversion module. The 12V is provided by a regulated power supply, and the 12V is converted into required power supply voltage, such as +/-5V, 1.2V, 2.5V, 3.3V and the like, by adopting a power conversion module.

FIG. 9 is a diagram of a DMA data transfer architecture that employs a PCIe bus and DMA mechanism to transfer data to a host. This is because there are some problems with using the PCIe IP core alone to transfer data. First, in the data transmission process, the CPU resource of the host is always occupied, so that the host itself cannot perform other operations. Secondly, when a large amount of data is transmitted using PCIe, multiple transmissions are performed, wasting a lot of time when starting and ending the transmissions, resulting in a drop in the average transmission rate. DMA mechanisms solve these problems well. The DMA controller uploads a fixed size of data to the host memory space specified by the CPU. And a CPU is not needed in the transmission process, so that the computing resources of the host are saved. The collected and processed data is buffered in an on-board memory, the FPGA firstly moves the data to a PC memory through an internal DMA engine, then the CPU transfers the data block to a hardware buffer through a Raid controller, and finally the data block is stored in a disk array. In order to achieve the highest transmission efficiency, the data transmission is automatically carried out in an interruption mode.

The process of DMA transfer can be divided into the following steps: first, the DMA engine issues an interrupt during the data transfer. Second, the driver layer responds to the interrupt and sends an event signal to the application layer. Then, upon receipt of the signal, the app transfers a certain amount of data from the PCIe space to the app data buffer for further processing, and then returns a signal to the driver layer informing the next DMA operation that can begin. Finally, it can continuously read data from the onboard memory to the PC memory.

After the performance of the high-frequency ground wave radar acquisition system is tested, the following conclusion can be drawn that the amplitude error between the channels and the angle error between the channels of the acquisition device is within 0.35dB and the angle error is not more than 3 degrees, as shown in fig. 10 and 11. As shown in fig. 12, the signal-to-noise ratio and the spurious free dynamic range of the acquisition system are 72dB and 87dB, respectively.

In conclusion, the method can obtain the original echo signal of the high-frequency ground wave radar, is beneficial to inspection and troubleshooting in system debugging, and has the advantages of simpler frame structure, convenience in implementation and easiness in operation compared with the frame structure in the old mode. In addition, the acquisition device also has high signal-to-noise ratio and spurious-free dynamic range, and the interference among channels is almost zero and has strong stability, thereby facilitating the signal processing in the later period.

Claims (8)

1. The utility model provides a high-speed data acquisition device of high frequency ground wave radar multichannel based on PCIe which characterized in that collection device includes analog front end circuit, ADC, FPGA, trigger control module, reference clock module and DDR, wherein:

the analog front-end circuit is used for converting an analog signal from a single-ended signal into a differential signal before the analog signal enters the ADC;

the ADC is connected with the output end of the analog front-end circuit and the input end of the FPGA and is used for converting analog signals into digital signals;

the FPGA is used for carrying out down-conversion on the digital signal output by the ADC and caching the processed data into the DDR through the PCIe connector;

the trigger control module is used for realizing various trigger modes in the system, packaging the acquired data and transmitting the data to the DDR module through the axial flow bus;

the reference clock module comprises an external reference clock and an external sampling clock, the external reference clock is used for providing periodic pulses for the whole system, and the external sampling clock is used for providing sampling parameters for analog-to-digital conversion;

the DDR is connected with the FPGA and the PCIe connector and used for caching data processed by the FPGA, and the data cached in the DDR is transmitted to the host through the PCIe bus and the DMA transmission architecture.

2. The PCIe-based high frequency ground wave radar multi-channel high speed data acquisition device as recited in claim 1, wherein said analog front end circuit is provided with eight input signal channel ports.

3. The PCIe-based high-frequency ground wave radar multi-channel high-speed data acquisition device as claimed in claim 1, wherein the ADCs are ADS42LB69, and the number is four.

4. The high-frequency ground wave radar multichannel high-speed data acquisition device based on PCIe (peripheral component interconnect express) of claim 1 is characterized in that the FPGA is provided with a JTAG interface and an 8-wire PCIe interface compatible with PCI-2.0 standard, and the device comprises an AD module, a user module, a trigger control module, a PCIe module, an SPI module, a VFIFO module and an SOC module.

5. The PCIe-based high-frequency ground wave radar multi-channel high-speed data acquisition device as claimed in claim 1, wherein the trigger control module is provided with four external trigger input ports, including a PCI-E module, an SPI module, a DDR module and an SOC module.

6. The PCIe-based high frequency ground wave radar multi-channel high speed data collection device as recited in claim 1, wherein said external reference clock is provided with an external reference clock input port and said external sampling clock is provided with an external sampling clock input port.

7. The PCIe-based high frequency ground wave radar multi-channel high speed data collection device as recited in claim 1, wherein said DDR is of DDR-3 type specification.

8. A signal processing method of a PCIe-based high frequency ground wave radar multi-channel high speed data acquisition apparatus according to any one of claims 1 to 7, characterized in that said method comprises the steps of:

after being received by an antenna, an echo signal is amplified and filtered by a receiver to become a high-frequency narrow-band signal, and after an acquisition device receives an external trigger signal, the high-frequency narrow-band signal is input into the acquisition device;

in the acquisition device, firstly, an analog front-end circuit amplifies and balances, then an analog signal is converted into a digital signal through an ADC (analog to digital converter), the digital signal output by the ADC is subjected to down-conversion by using an FPGA (field programmable gate array), and processed data are cached in a DDR (double data rate); the external reference clock signal provides periodic pulses for various operations of the FPGA, and the clock frequency of the acquisition device and the clock frequency of the receiver are ensured to be homologous;

and thirdly, after receiving the trigger signal, the FPGA transmits the data cached in the DDR to the upper computer cache through a PCIe interface in a DMA mode, and finally, the upper computer control center performs signal processing by using the uploaded data to obtain the distance, the speed and the direction of the target so as to perform positioning and tracking.

Images