CN111781885B - Soft direct-current converter valve optical trigger plate and trigger pulse signal redundancy method - Google Patents
Soft direct-current converter valve optical trigger plate and trigger pulse signal redundancy method Download PDFInfo
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- CN111781885B CN111781885B CN202010681600.4A CN202010681600A CN111781885B CN 111781885 B CN111781885 B CN 111781885B CN 202010681600 A CN202010681600 A CN 202010681600A CN 111781885 B CN111781885 B CN 111781885B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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Abstract
The invention belongs to the technical field of flexible direct current transmission, and discloses a flexible direct current converter valve optical trigger plate and a trigger pulse signal redundancy method, wherein the flexible direct current converter valve optical trigger plate comprises at least two first FPGA components, a second FPGA component, an arbitration switch and a plurality of optical ports; the first FPGA component comprises a first FPGA, a first power supply and a first crystal oscillator; the second FPGA component comprises a second FPGA, at least two second power supplies and at least two second crystals; the first power supply and the first crystal oscillator are connected with the first FPGA, the second power supply and the second crystal oscillator are connected with the second FPGA, all the first FPGAs are connected with the second FPGA, and all the first FPGAs and the second FPGAs are connected with the arbitration switch. Two first FPGA components and a second FPGA component are integrated on a board, redundancy of trigger pulse signals is achieved on the board based on an arbitration switch, the second FPGA component at least comprises two second power supplies and two second crystals, damage of any crystal oscillator, power supply or first FPGA in a circuit does not affect continuous operation of the light trigger plate, and reliability of the system is improved.
Description
Technical Field
The invention belongs to the technical field of flexible direct current transmission, and relates to a flexible direct current converter valve optical trigger plate and a trigger pulse signal redundancy method.
Background
The flexible DC transmission technology is a novel DC transmission technology based on a fully-controlled power electronic device, a voltage source converter and a pulse width modulation technology. In 1990, boon-TeckOoi et al, canada, proposed for the first time a high voltage direct current transmission technology (VSC-HVDC) based on a voltage source converter, called flexible direct current transmission technology. Experimental engineering of Flexible DC Transmission in the world in 1997Engineering (10 kV,3 MW) is built into operation. The german scholars Rainer Marquardt in 2001 proposed a modular multilevel converter based technology. In 2010, the world first flexible direct current transmission project based on modularized multi-level converters, namely Trans Bay Cable project (+ -200 kV,400 MW), is built for operation. Compared with the conventional direct current, the flexible direct current transmission system has the advantages of no commutation failure, independent regulation and control of active power and reactive power, low harmonic level, small occupied area, convenience for constructing a multi-terminal direct current system and the like, and is suitable for the fields of large-scale grid connection of renewable energy sources, asynchronous interconnection of large-scale power grids, power supply to a passive network and the like. With the continuous improvement of technical parameters of high-power fully-controlled power electronic devices, the demonstration application of the flexible direct current transmission technology in the aspect of high-voltage and high-capacity transmission engineering is further accelerated. Worldwide, flexible direct current transmission achieves a annual market scale of hundreds of billions, and presents an increasing trend, thus having wide market prospect.
The flexible direct current transmission converter valve is a core device of flexible direct current transmission, and the valve control is the brain of the flexible direct current converter valve, and whether the operation is normal or not is directly related to the safe and stable operation of the flexible direct current converter valve, so that the valve control of the converter valve is required to adopt a redundant configuration scheme in the valve control engineering design. At present, a valve control redundancy design mainly adopts a device-level redundancy method. Referring to fig. 1, the valve control protection device in valve control adopts A, B two sets of identical devices to realize redundancy configuration scheme, and it is generally considered that the optical trigger plate of the optical fiber distribution screen directly connected with the valve cannot be redundant on a single board card, and the redundancy is usually realized by adopting a mode that two identical trigger boards send identical optical signals.
However, the redundancy is achieved by adopting the mode that two identical trigger boards send identical optical signals, which results in that the two trigger boards can only send identical signals outwards in a pulse mode and cannot be used for sending protocol signals with strict requirements on time synchronization.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a soft direct current converter valve optical trigger plate and a trigger pulse signal redundancy method.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a soft direct current converter valve light trigger plate comprises at least two first FPGA components, a second FPGA component, an arbitration switch and a plurality of light ports; the first FPGA component comprises a first FPGA, a first power supply and a first crystal oscillator; the second FPGA component comprises a second FPGA, at least two second power supplies and at least two second crystals; the first FPGA is provided with a first power interface, a first clock Zhong Jiekou, a first pulse output interface, a life signal output interface and a board interface for connecting a superior board, wherein the first power interface and the first clock interface are respectively connected with a first power supply and a first crystal oscillator; the second FPGA is provided with a life signal input interface, an arbitration signal output interface, a plurality of second power interfaces and a plurality of second clock interfaces; the second power interfaces are connected with the second power sources in a one-to-one correspondence manner, the second clock interfaces are connected with the second crystal oscillator in a one-to-one correspondence manner, and the vital signal input interface is connected with the vital signal output interface; the arbitration switch is provided with a plurality of pulse input interfaces, an arbitration signal input interface and a plurality of second pulse output interfaces which are connected with the optical ports in a one-to-one correspondence manner; the pulse input interfaces are connected with the first pulse output interfaces in a one-to-one correspondence manner, and the arbitration signal input interfaces are connected with the arbitration signal output interfaces.
The invention is further improved in that:
the number of the first FPGA components is two.
The number of the second power supply and the second crystal oscillator are two.
The first FPGA and the second FPGA are both A7 35T/50T/75T FGG484 type FPGAs.
The first power supply and the second power supply are TPS54625PWP power supply chips.
The first crystal oscillator and the second crystal oscillator are both active patch crystal oscillator 7050SMD.
The arbitration switch is an analog switch chip CD4051.
In another aspect of the present invention, a method for triggering pulse signal redundancy includes the steps of:
s1: the method comprises the steps of respectively receiving signals issued by redundant two upper-level board cards through two first FPGA components;
s2: analyzing a signal issued by an upper-level board card into a trigger pulse signal and a life signal through a first FPGA;
s3: sending two trigger pulse signals to an arbitration switch; sending the two vital signals to a second FPGA;
s4: the second FPGA generates an arbitration signal according to the validity of the two vital signals and sends the arbitration signal to the arbitration switch;
s5: the arbitration switch sends one trigger pulse signal to the corresponding optical port according to the arbitration signal.
Compared with the prior art, the invention has the following beneficial effects:
through having integrated two at least first FPGA subassemblies, second FPGA subassembly and arbitration switch on a integrated board, receive the signal of redundant superior board through two first FPGA subassemblies, and detect the signal of redundant superior board and select through the second FPGA subassembly, send the signal of selecting to each light mouth through arbitration switch, and then send to the optical device, just can realize trigger signal's redundant design through a board, not only can outwards send the same signal with the pulse mode, can also be used for sending the protocol signal that requires strict to time synchronization, realize the redundancy of valve accuse equipment as far as, guarantee the safe and stable operation of converter valve. Meanwhile, at least two second power supplies and at least two second crystals are arranged in the second FPGA component, so that the damage of any one of the first crystals, the first power supply, the second crystals or the first FPGA does not affect the continuous operation of the optical trigger plate, and the reliability of the system is improved.
Drawings
FIG. 1 is a block diagram of a prior art valve control device level redundancy architecture;
fig. 2 is a block diagram of the structure of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 2, the flexible direct current converter valve optical trigger plate comprises two first FPGA components, a second FPGA component, an arbitration switch and a plurality of optical ports; the first FPGA component comprises a first FPGA, a first power supply and a first crystal oscillator; the second FPGA component comprises a second FPGA, two second power supplies and two second crystals; the first FPGA is provided with a first power interface, a first clock Zhong Jiekou, a first pulse output interface, a life signal output interface and a board interface for connecting a superior board, wherein the first power interface and the first clock interface are respectively connected with a first power supply and a first crystal oscillator; the second FPGA is provided with a life signal input interface, an arbitration signal output interface, a plurality of second power interfaces and a plurality of second clock interfaces; the second power interfaces are connected with the second power sources in a one-to-one correspondence manner, the second clock interfaces are connected with the second crystal oscillator in a one-to-one correspondence manner, and the vital signal input interface is connected with the vital signal output interface; the arbitration switch is provided with a plurality of pulse input interfaces, an arbitration signal input interface and a plurality of second pulse output interfaces which are connected with the optical ports in a one-to-one correspondence manner; the pulse input interfaces are connected with the first pulse output interfaces in a one-to-one correspondence manner, and the arbitration signal input interfaces are connected with the arbitration signal output interfaces.
In this embodiment, the first FPGA and the second FPGA are both A7T/50T/75T fgg484 type FPGAs, the first power supply and the second power supply are both TPS54625PWP power supply chips, the first crystal oscillator and the second crystal oscillator are both active patch crystal oscillator 7050 SMDs, their center frequencies and frequency differences are respectively 100MHz and 50ppm, and the arbitration switch is an analog switch chip CD4051, but it is not limited thereto, and it can be clearly understood by those skilled in the art that the above devices may also be other types of products having the same function.
In this embodiment, the number of the first FPGA component, the second power supply, and the second crystal oscillator is two, so that the effect of redundancy can be achieved, but the method is not limited thereto, and the number of the first FPGA component, the second power supply, and the second crystal oscillator can be more than two without considering other factors, so that the better effect of redundancy can be achieved.
The working process of the invention comprises the following steps: the first FPGAs in the two first FPGA components respectively receive signals from redundant upper-level board cards VGCB-A and VGCB-B through board card interfaces, the signals are resolved into trigger pulse signals and vital signals through the first FPGAs, the trigger pulse signals are sent to an arbitration switch through ase:Sub>A first pulse output interface and ase:Sub>A pulse input interface, meanwhile, the second FPGAs receive the vital signals from the two first FPGAs, an arbitration signal is generated according to the vital signals and is sent to the arbitration switch through the arbitration signal output interface and the arbitration signal input interface, the arbitration switch determines the trigger pulse signals sent by one of the two first FPGAs through the arbitration signal, then the arbitration switch sends the trigger pulse signals to corresponding optical ports, and the trigger pulse signals are sent to all optical devices to realize triggered redundancy. In the soft direct current converter valve optical trigger plate, the damage of any one of the first crystal oscillator, the first power supply, the second crystal oscillator or the first FPGA does not influence the continuous operation of the optical trigger plate, and the reliability of a system is improved.
The invention also discloses a trigger pulse signal redundancy method based on the soft direct current converter valve optical trigger plate, which comprises the following steps:
s1: and the two first FPGA components are used for respectively receiving signals issued by the redundant two upper-level board cards.
S2: and analyzing the signal issued by the upper-level board card into a trigger pulse signal and a life signal through the first FPGA.
S3: sending two trigger pulse signals to an arbitration switch; and sending the two vital signals to a second FPGA.
S4: the second FPGA generates arbitration signals according to the two vital signals and sends the arbitration signals to the arbitration switch, specifically, the arbitration signals are the trigger pulse signals of the first FPGA with the valid vital signals are set as selection objects, and when the vital signals of the two first FPGAs are valid, one of the two first FPGAs is selected randomly.
S5: the arbitration switch sends one of the trigger pulse signals to the corresponding optical port according to the arbitration signal, wherein the corresponding optical port is the optical port connected with the optical device to be driven by the trigger pulse signal.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (8)
1. The light trigger plate of the soft direct current converter valve is characterized by comprising at least two first FPGA components, a second FPGA component, an arbitration switch and a plurality of light ports; the first FPGA component comprises a first FPGA, a first power supply and a first crystal oscillator; the second FPGA component comprises a second FPGA, at least two second power supplies and at least two second crystals;
the first FPGA is provided with a first power interface, a first clock Zhong Jiekou, a first pulse output interface, a life signal output interface and a board interface for connecting a superior board, wherein the first power interface and the first clock interface are respectively connected with a first power supply and a first crystal oscillator;
the second FPGA is provided with a life signal input interface, an arbitration signal output interface, a plurality of second power interfaces and a plurality of second clock interfaces; the second power interfaces are connected with the second power sources in a one-to-one correspondence manner, the second clock interfaces are connected with the second crystal oscillator in a one-to-one correspondence manner, and the vital signal input interface is connected with the vital signal output interface;
the arbitration switch is provided with a plurality of pulse input interfaces, an arbitration signal input interface and a plurality of second pulse output interfaces which are connected with the optical ports in a one-to-one correspondence manner; the pulse input interfaces are connected with the first pulse output interfaces in a one-to-one correspondence manner, and the arbitration signal input interfaces are connected with the arbitration signal output interfaces;
the arbitration switch determines the arbitration switch to select a trigger pulse signal sent by one of the first FPGAs, and then the arbitration switch sends the trigger pulse signal to the corresponding optical port, and then sends the trigger pulse signal to all optical devices to realize the redundancy of triggering.
2. The flexible direct current converter valve light trigger plate of claim 1, wherein the number of first FPGA components is two.
3. The flexible direct current converter valve light trigger plate of claim 1, wherein the number of second power sources and second crystals are two.
4. The flexible direct current converter valve light trigger plate of claim 1, wherein the first and second FPGAs are each an A7 35T/50T/75T fgg484 type FPGA.
5. The flexible direct current converter valve light trigger plate of claim 1, wherein the first power supply and the second power supply are TPS54625PWP power chips.
6. The flexible direct current converter valve optical trigger plate of claim 1, wherein the first crystal oscillator and the second crystal oscillator are active patch crystal oscillator 7050SMD.
7. The flexible direct current converter valve light trigger plate of claim 1, wherein the arbitration switch is an analog switch chip CD4051.
8. A method for redundancy of trigger pulse signals based on the optical trigger plate of the soft direct current converter valve according to any one of claims 1 to 7, comprising the steps of:
s1: the method comprises the steps of respectively receiving signals issued by redundant two upper-level board cards through two first FPGA components;
s2: analyzing a signal issued by an upper-level board card into a trigger pulse signal and a life signal through a first FPGA;
s3: sending two trigger pulse signals to an arbitration switch; sending the two vital signals to a second FPGA;
s4: the second FPGA generates an arbitration signal according to the validity of the two vital signals and sends the arbitration signal to the arbitration switch;
s5: the arbitration switch sends one trigger pulse signal to the corresponding optical port according to the arbitration signal.
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| CN202010681600.4A CN111781885B (en) | 2020-07-15 | 2020-07-15 | Soft direct-current converter valve optical trigger plate and trigger pulse signal redundancy method |
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| CN202010681600.4A CN111781885B (en) | 2020-07-15 | 2020-07-15 | Soft direct-current converter valve optical trigger plate and trigger pulse signal redundancy method |
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| CN113472189B (en) * | 2021-07-07 | 2022-05-17 | 中国南方电网有限责任公司超高压输电公司天生桥局 | Double-slave judgment method and system for flexible direct current transmission valve control system |
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