CN111769158A - Double-channel super-junction VDMOS device with low reverse recovery charge and manufacturing method - Google Patents

Double-channel super-junction VDMOS device with low reverse recovery charge and manufacturing method Download PDF

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CN111769158A
CN111769158A CN202010439394.6A CN202010439394A CN111769158A CN 111769158 A CN111769158 A CN 111769158A CN 202010439394 A CN202010439394 A CN 202010439394A CN 111769158 A CN111769158 A CN 111769158A
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oxide layer
type column
heavily doped
column region
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CN111769158B (en
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成建兵
陈明
李浩铮
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Nanjing University of Posts and Telecommunications
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Nanjing University of Posts and Telecommunications
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Abstract

The invention discloses a double-channel super-junction VDMOS device with low reverse recovery charge and a manufacturing method thereof.A source electrode is respectively established above a gate electrode area and a JFET area, an N-pilar area, a P-body area and an N + source area are sequentially and newly established above the JFET area, so that a gate electrode of the device is divided into a plurality of areas, the whole gate is separated by the newly added area, the source electrode and the gate electrode, a separated gate is formed, and a source electrode is added. The super-junction VDMOS transistor structure maintains the breakdown voltage and the on-state current processing capacity of the super-junction VDMOS transistor, reduces the stored charges of the parasitic diode in the body, and improves the reverse recovery characteristic of the device.

Description

Double-channel super-junction VDMOS device with low reverse recovery charge and manufacturing method
Technical Field
The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to a double-channel super-junction VDMOS device having a low reverse recovery charge and a method for manufacturing the same.
Background
The super junction VDMOS is a very important power device in the middle and high voltage field, as shown in FIG. 1, the basic structure of the super junction VDMOS is a drift region composed of P columns (P-pilar) and N columns (N-pilar) which are alternately arranged, and the basic principle of charge balance is followed, the limitation (Ron-BV) of the traditional structure is broken through under the silicon limit limitation, the on resistance is reduced, and the reduced resistance is accompanied with the enhanced current saturation capacity, so that the super junction VDMOS is particularly attractive to PWM and motor control applications.
However, similar to the conventional VDMOS device, the super-junction VDMOS device also has a large parasitic body diode, and when a reverse bias occurs in the peripheral circuit application, i.e. the source (source) is connected to a high potential, the drain (drain) is connected to a low potential, and the gate (gate) is connected to a zero potential, the parasitic body diode starts to operate, and this operation mode is generally called a reverse conducting state of the super-junction VDMOS, as shown in fig. 2(a), when the potential difference of the P-body/N-drift region is greater than the conventional PN junction built-in potential (about 0.7V), the P-body and the P-pilar emit holes into the drift region, and at this time, the substrate (N + sub) is connected to a low potential, the holes flow to the drain under the action of the electric field. In order to maintain the electrical neutrality in the drift region, at the same time the N + substrate also starts to emit electrons into the drift region, and the holes and electrons undergo a conductivity modulation effect in the drift region, so that the resistance in the drift region drops rapidly, i.e. the reverse conduction voltage drop is low. Due to the introduction of the super-junction P column region, when hole injection occurs, the emission efficiency is enhanced, namely, when the super-junction device is in reverse conduction, the hole is injected into the N-pilar drift region, namely, the hole injected into the N column region is far more than the hole injected into the N-pilar drift region by the conventional VDMOS.
The super junction VDMOS reverse recovery process is essentially a turn-off process of the body diode, and as shown in fig. 3, when the diode transits from a reverse conducting state to a reverse blocking state, it needs to first release the remaining carriers (Qrr) stored in the drift region, and this process needs a period of time called a discharge time, that is, a reverse recovery time (Trr), as shown in fig. 2(b), during which current flows in the reverse direction through the diode, holes are repelled to the P-body well region under the action of a drain high voltage electric field, and finally flow out from the source, electrons are attracted to the N + sub substrate under the action of the drain high voltage electric field, and finally flow out from the drain, and this process is performed until the holes in the drift region are completely extracted. Because the number of hole electron pairs injected into the super-junction N column of the device is far larger than that of the traditional VDMOS when the super-junction VDMOS is reversely conducted, more energy can be lost in the process of reversely recovering and extracting the excess carriers by the super-junction VDMOS.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a double-channel super-junction VDMOS device with low reverse recovery charge, which reduces the reverse recovery charge of the super-junction VDMOS device and improves the reverse recovery characteristic of the device; the invention also aims to provide a manufacturing method of the double-channel super-junction VDMOS device with low reverse recovery charge.
The technical scheme is as follows: the invention discloses a double-channel super-junction VDMOS device with low reverse recovery charge, which comprises a drain electrode, an N-type heavily doped drain electrode ohmic contact layer, an N-type column region and a P-type column region which are alternately distributed to form a drift region, a P-type lightly doped body (P-body) region, a source electrode, a heavily doped N + region of a source electrode ohmic contact region, a thin oxide layer for enhancing barrier coupling of the source electrode to the P-base region, a gate electrode and a gate oxide layer; a thinner left side oxide layer corresponding to the right side gate oxide layer; the P-base region forming the longitudinal channel, the N + layer of the ohmic contact region of the source electrode, the N-pilar region extending upwards, the longitudinal gate oxide layer and the field oxide layer.
Namely: the drift region is formed by alternately distributing the first N-type column region and the P-type column region; two sides of the top of the first N-type column region are respectively provided with a P-body region, the P-body regions are respectively contacted with the first N-type column region and the P-type column region, and each P-body region is respectively provided with a first heavily doped N + region;
a second N-type column region, a P-base region and a second heavily doped N + region which are sequentially stacked are arranged above the first N-type column region, and the second N-type column region, the P-base region and the second heavily doped N + region form a stacked structure; one side of the laminated structure is provided with a gate oxide layer, and the other side of the laminated structure is provided with a first thin oxide layer along the longitudinal direction; the lower surface of the gate oxide layer is contacted with part of the first N-type column region, part of the P-body region and part of the first heavily doped N + region; a second thin oxide layer is arranged on one side of the first thin oxide layer, which is far away from the laminated structure, and the second thin oxide layer is contacted with part of the first N-type column region and part of the P-body region; a field oxide layer is arranged on one side, away from the first thin oxide layer, of the second thin oxide layer, and the field oxide layer is in contact with part of the first heavily doped N + region;
the gate electrode is embedded in the gate oxide layer, is positioned above the P-body area and covers the P-body area, the width of the longitudinal gate oxide layer at one side of the gate electrode close to the laminated structure is the same as the thickness of the gate oxide layer below the gate electrode, the lower surface of the gate electrode is lower than or level with the lower surface of the P-base area, and the height of the gate electrode is higher than that of the P-base area; the first thin oxide layer and the second thin oxide layer have the same thickness, and the thickness is smaller than the width of the longitudinal gate oxide layer;
the source electrode is arranged on the surface of the device, and the source electrode is contacted with the upper surfaces of part of the first heavily doped N + region and the P-body region, the two side surfaces and the upper surface of the field oxide layer, one side surface and the upper surface of the gate oxide layer, the upper surface of the second thin oxide layer and one side surface of the first thin oxide layer.
Wherein, the height of the field oxide layer and the height of the laminated structure can be the same or different; the left and right positions of the gate electrode are above the P-body area and can cover the P-body area; the lower surface of the gate electrode is flush with the lower surface of the P-base region or is positioned below the side of the P-base region.
Preferably, the second N-type column region and the first N-type column region have the same doping concentration, and the thickness of the second N-type column region is adjustable.
An upward extending N-Pillar region (a second N-type column region) is arranged above the JFET region, the property of the region is consistent with that of an N-type lightly doped region (a first N-type column region) of a conventional super-junction VDMOS, the opening voltage of two MOS structures controlled by a grid electrode is guaranteed to be consistent, and the opening voltage of the super-junction VDMOS in a reverse conduction stage is smaller than that of a parasitic body diode. Meanwhile, the thickness of the N-pilar region extending upwards influences the on-resistance of the super-junction VDMOS, the influence of the thickness of the N-pilar region on the on-resistance is enhanced along with the increase of the thickness, and then the thickness of the N-pilar region can be properly adjusted to optimize the on-resistance.
Preferably, the P-base region and the P-body region have the same doping concentration, and the second N-type column region and the P-base region have the same region width.
A P-base region is arranged above the upwardly extending N-Pillar region (a second N-type column region), the property of the P-base region is consistent with that of a body (P-body) region of a conventional super-junction VDMOS, so that the forward starting voltages of two MOS structures controlled by a grid electrode are ensured to be consistent, and the starting voltage of the reverse conduction stage of the super-junction VDMOS is smaller than that of a parasitic body diode; the thickness of the area ensures that the double-channel structure can not generate punch-through breakdown phenomenon during voltage resistance, and further, the thickness of the P-base area can be properly adjusted.
Preferably, the second heavily doped N + region and the first heavily doped N + region have the same doping concentration. The second heavily doped N + region has the same property with the N-type heavily doped region of the conventional super-junction VDMOS, and the region provides electrons for the conduction stage of the device, so that the thickness of the second heavily doped N + region can be properly adjusted.
Preferably, the thickness of the second thin oxide layer and the vertical gate oxide layer is adjustable. The thickness of the left side oxide layer (second thin oxide layer) is properly adjusted, so that the turn-on voltage of the P-body/N-pilar junction below the left side oxide layer is smaller than that of the conventional body diode when the super-junction VDMOS is reversely conducted.
The thickness of the gate oxide layer between the gate electrode and the upwards extending N-pilar region (second N-type column region) and the P-base region influences the starting voltage of the super-junction VDMOS, and the thickness of the longitudinal gate oxide layer can be adjusted.
Optionally, the gate oxide layer is silicon dioxide.
Preferably, the widths of the second N-type column region, the P-base region and the second heavily doped N + region are the same.
Wherein, the heavily doped semiconductor substrate of the device is N type or P type; if the heavily doped semiconductor substrate is of a P type, the IGBT device is formed.
The invention also provides a manufacturing method of the double-channel super-junction VDMOS device with low reverse recovery charge, which comprises the following steps:
(1) extending a film with the same doping concentration as that of the first N-type column region on the heavily doped semiconductor substrate, etching a groove of the P-type column region on the film, and forming the P-type column region by adopting a multi-time extending or filling method;
(2) forming a P-body region by an ion implantation or diffusion method, and forming a first heavily doped N + region by the ion implantation or diffusion method;
(3) oxidizing to form a field oxide layer, etching a gate electrode window, forming a gate oxide layer and a longitudinal gate oxide layer, and depositing to form a gate electrode;
(4) etching a second N-type column region epitaxial window on the field oxide layer, epitaxially forming a second N-type column region and a P-base region, and performing ion implantation to form a second heavily doped N + region;
(5) etching a source electrode window to form a first thin oxide layer and a second thin oxide layer, and metalizing to form a source electrode;
(6) the back side metallization forms the drain electrode.
The invention principle is as follows: the invention is a device which changes a reverse conduction path at one end, establishes another forward conduction path and optimizes the reverse recovery characteristic of a super-junction VDMOS; compared with a super junction device with a traditional structure, the double-channel structure provided by the invention has the advantages that the source electrodes are respectively established above the grid electrode area and the JFET area, the N-pilar area, the P-body area and the N + source area are sequentially and newly established above the JFET, and the newly established area and the newly established source electrode form an MOS structure controlled by two source electrodes; the device modulates the barrier height of an adjacent PN junction by controlling the thickness of a silicon dioxide layer of a source contact region, so as to change the starting voltage during reverse conduction, so that reverse current preferentially passes through a source control MOS region, and the injection of electrons of an N-pilar region into a P + pody region and a P-pilar region is reduced; meanwhile, another MOS structure is formed between the newly established region and the grid, two grid-controlled MOS are established in one grid region and used as a conduction path of the positive conduction of the super-junction VDMOS, the positive conduction path of the double-path structure is added, and the saturation current characteristic of the device is improved.
The conventional super-junction VDMOS has an internal parasitic diode with a large metallurgical junction area, so that a large number of excess carriers can be stored in an on state, and the power consumption in the switching process is increased. The invention reduces the storage of excess current carriers by introducing a new longitudinal channel and reducing the thickness of a transverse conventional channel oxide layer; on the one hand, smaller steering recovery charges are obtained, and on the other hand, the saturation current capability of the new structure is maintained.
The double-channel structure changes the size of the turn-on voltage of the device during reverse conduction by controlling the thickness of the silicon dioxide layer of the newly-built source contact area, and the change of the turn-on voltage changes the current which preferentially passes through the N-pilar drift area along with the change of the thickness of the silicon dioxide layer, so that the injection of electrons in the N-pilar drift area into a P-body area and a P-pilar area is reduced, and the stored charges in the drift area are reduced; meanwhile, a new forward conducting path is established between the grid region and the newly added region, the forward conducting path of the dual-path structure is optimized while the reverse recovery characteristic of the super-junction VDMOS body diode is improved, and the saturation current characteristic of the device is improved.
Has the advantages that: the super-junction structure provided by the invention optimizes the technical problem of reverse recovery of the device stored charges of the super-junction VDMOS in the prior art, and reduces the reverse recovery charges of the super-junction VDMOS device compared with the conventional structure; the novel structure of the invention reduces the stored charge of the parasitic diode in the body while maintaining the breakdown voltage and the on-state current processing capability of the super-junction VDMOS, thereby improving the reverse recovery characteristic of the device. The invention can be applied to the application fields with higher requirements on switching speed and electric energy conversion efficiency, such as the fields of power adapters, LED, LCD, PDP driving, industrial control, automobile electronics and the like.
Drawings
Fig. 1 is a conventional superjunction VDMOS structure;
fig. 2 is a motion trajectory of electrons and holes in a reverse recovery phase of the super-junction VDMOS, where fig. 2(a) is forward bias of a body diode and fig. 2(b) is reverse bias of the body diode;
FIG. 3 is a schematic diagram of a super junction VDMOS reverse recovery output characteristic curve;
FIG. 4 is a double channel super junction VDMOS structure with low reverse recovery charge;
fig. 5 is a graph comparing off current versus time for two configurations.
Detailed Description
The present invention will be described in further detail with reference to examples.
Example 1:
the heavily doped semiconductor substrate in this embodiment is an N-type substrate.
The double-channel super-junction VDMOS structure with low reverse recovery charge comprises a drain electrode 11, an N-type heavily doped semiconductor substrate 12, a first N-type column region 13 and a P-type column region 14 which are alternately distributed to form a drift region, a P-body region 15, a first heavily doped N + region 16, a source electrode 17, a gate oxide layer 18, a gate electrode 19, a second N-type column region 20, a P-base region 21 forming a longitudinal channel, a second heavily doped N + region 22, a first thin oxide layer 23, a second thin oxide layer 24, a longitudinal gate oxide layer 25 and a field oxide layer 26;
wherein, the N-type heavily doped semiconductor substrate 12 is an N-type heavily doped drain electrode ohmic contact layer; the first heavily doped N + region 16 is a heavily doped N + region in ohmic contact with the source electrode 17; the second N-type pillar region 20 is an upwardly extending N-pilar region and the second heavily doped N + region 22 is a heavily doped N + region in ohmic contact with the source electrode 17, the first thin oxide layer 23 is a thin oxide layer of the source electrode 17 for enhancing barrier coupling to the P-base region 21, and the second thin oxide layer 24 is a thinner left side oxide layer corresponding to the gate oxide layer 18 on the right side in fig. 4.
As shown in fig. 4, the bottom of the device is an N-type heavily doped semiconductor substrate 12, the lower surface of the N-type heavily doped semiconductor substrate 12 is provided with a drain electrode 11, the upper surface is provided with a first N-type column region (N-pillar)13 and a P-type column region (P-pillar)14, and the first N-type column region 13 and the P-type column region 14 are alternately distributed to form a drift region; the left side and the right side of the top of the first N-type column region 13 are respectively provided with a P-body region 15, the P-body regions 15 are respectively contacted with the first N-type column region 13 and the P-type column region 14, and each P-body region 15 is respectively provided with a first heavily doped N + region 16;
a second N-type column region (N-pillar)20, a P-base region 21 and a second heavily doped N + region 22 which are sequentially stacked are arranged above the first N-type column region 13, and the second N-type column region 20, the P-base region 21 and the second heavily doped N + region 22 form a stacked structure; the right side of the laminated structure is provided with a gate oxide layer 18, the left side of the laminated structure is provided with a first thin oxide layer 23 arranged along the longitudinal direction, the left side surface of the gate oxide layer 18 is contacted with the right side surface of the laminated structure, and the right side surface of the first thin oxide layer 23 is contacted with the left side surface of the laminated structure.
Wherein the lower surface of the gate oxide layer 18 contacts with part of the first N-type column region 13, the left part of the P-body region 15, and part of the first heavily doped N + region 16, where the P-body region 15 and the first heavily doped N + region 16 are located at the right side of the device.
A second thin oxide layer 24 along the transverse direction is arranged on one side (namely the left side) of the first thin oxide layer 23 away from the laminated structure, the second thin oxide layer 24 is in contact with part of the first N-type column region 13, the right side part of the P-body region 15 and part of the first heavily doped N + region 16, and the P-body region 15 and the first heavily doped N + region 16 are positioned on the left side of the device.
A field oxide layer 26 is arranged on one side (namely the left side) of the second thin oxide layer 24 away from the first thin oxide layer 23, and the field oxide layer 26 is in contact with part of the first heavily doped N + region 16;
the gate electrode 19 is embedded in the gate oxide layer 18 and positioned above the right P-body region 15 and can cover the P-body region 15, the width of the longitudinal gate oxide layer 25 of the gate electrode 19 close to one side of the laminated structure is the same as the thickness of the gate oxide layer 18 below the gate electrode 19, the vertical height of the gate electrode 19 is higher than that of the P-base region 21, the height of the upper surface of the gate electrode 19 is higher than that of the upper surface of the P-base region 21, and the lower surface of the gate electrode 19 is flush with the lower surface of the P-base region 21;
the thicknesses of the first thin oxide layer 23 and the second thin oxide layer 24 are the same, and the thicknesses of the first thin oxide layer and the second thin oxide layer are smaller than the width of the longitudinal gate oxide layer 25; the second thin oxide layer 24 is in contact with a portion of the first thin oxide layer 23 and a portion of the field oxide layer 26 on both sides, respectively.
The source electrode 17 covers the upper surface of the device, and the source electrode 17 is in contact with the upper surfaces of part of the first heavily doped N + region 16 and the P-body region 15, the left side surface, the right side surface and the upper surface of the field oxide layer 26, the right side surface and the upper surface of the gate oxide layer 18, the upper surface of the second thin oxide layer 24 and the left side surface of the first thin oxide layer 23.
As shown in fig. 5, it can be seen that the maximum reverse recovery current of the new structure is smaller than that of the conventional structure.
The super junction power device in this embodiment has a forward double-channel conduction path, one of which is a longitudinal channel formed by the P-base region 21 and the longitudinal gate oxide layer 25, and the other of which is a transverse channel formed by the P-body region and the gate oxide layer 18.
The super junction power device has a reverse three-channel conduction path, which is a first heavily doped N + region (N + layer) 16, a P-body region 15, a first N-type column region (N-pilar column region) 13 and an N-type heavily doped semiconductor substrate (N + substrate) 12 on the left side; the second is a second heavily doped N + region (N + layer) 22, a P-base region 21, a second N-type column region (upwardly extending N-pilar region) 20, a first N-type column region (N-pilar column region) 13, and an N-type heavily doped semiconductor substrate (N + substrate) 12; the third is the first heavily doped N + region (N + layer) 16, the P-body region 15, the first N-type pillar region (N-pilar pillar region) 13, and the N-type heavily doped semiconductor substrate (N + substrate) 12 on the right side. The difference between path one and path two is that the thickness of the second thin oxide layer 24 and the gate oxide layer 18 are different, and the barrier height of the metallurgical junction is also different.
Compared with the traditional super-junction VDMOS device, the double-channel structure provided by the structure of the invention respectively establishes the source electrode above the gate electrode area and the JFET area, and sequentially establishes the N-pilar area, the P-body area and the N + source area above the JFET, so that the gate electrode of the device is divided into a plurality of areas, as shown in figure 4, the whole gate is separated by the newly added area, the source electrode and the gate electrode, a separated gate is formed, and a source electrode is added.
The novel structure of the invention reduces the stored charge of the parasitic diode in the body and improves the reverse recovery characteristic of the device while maintaining the breakdown voltage and the on-state current processing capability of the super-junction VDMOS. The innovation of the double-channel super-junction VDMOS device with low reverse recovery charge is as follows:
(1) the thickness of the left gate oxide layer 24 of the new structure is thinner than that of a conventional device, the source electrode 17 is led to the position above the thin oxide layer 24, and the thin oxide layer 24 enhances the modulation of the source electrode 17 on the P-body/N-pilar (namely 15/13) junction barrier height, reduces the PN junction barrier height, so that minority carriers are more difficult to pass through a metallurgical junction surface, the carriers stored in the P-body region 15 and the N-pilar region 13 are reduced, and the reverse recovery charge is reduced;
(2) the modulation of the barrier height of the source electrode to the P-base/N + junction is enhanced by the longitudinal first thin oxide layer 23, and reverse recovery charges are reduced;
(3) the vertical channel formed by the vertical gate oxide layer 25 and the P-base region 21 provides a new current channel for the device in an on state, and the current saturation capacity of the new structure is kept.
Example 2:
the embodiment is a manufacturing method of a double-channel super-junction VDMOS structure with low reverse recovery charge, which comprises the following steps:
(1) extending a film with the same doping concentration as that of the first N-type column region 13 on a heavily doped semiconductor substrate (N-type or P-type) 12, etching a groove of the P-type column region 14 on the film, and forming the P-type column region 14 by adopting a multi-time extending or filling method;
(2) forming a P-body region 15 by means of ion implantation or diffusion, and forming a first heavily doped N + region 16 by means of ion implantation or diffusion;
(3) oxidizing to form a field oxide layer 26, etching a window of the gate electrode 19 to form a gate oxide layer 18 and a longitudinal gate oxide layer 25, and depositing to form the gate electrode 19;
(4) etching an epitaxial window of the second N-type column region 20 on the field oxide layer 26, epitaxially forming the second N-type column region 20 and the P-base region 21, and ion implantation forming a second heavily doped N + region 22;
(5) etching a window of the source electrode 17 to form a first thin oxide layer 23 and a second thin oxide layer 24, and metallizing to form the source electrode 17;
(6) the back side metallization forms the drain electrode 11.

Claims (8)

1. A double-channel super-junction VDMOS device with low reverse recovery charge is characterized in that: the transistor comprises a drain electrode (11), a heavily doped semiconductor substrate (12), a first N-type column region (13) and a P-type column region (14) which are positioned on the upper surface of the heavily doped semiconductor substrate, wherein the first N-type column region (13) and the P-type column region (14) are alternately distributed to form a drift region; two sides of the top of the first N-type column region (13) are respectively provided with a P-body region (15), the P-body regions (15) are respectively contacted with the first N-type column region (13) and the P-type column region (14), and each P-body region (15) is respectively provided with a first heavily doped N + region (16); a second N-type column region (20), a P-base region (21) and a second heavily doped N + region (22) which are sequentially stacked are arranged above the first N-type column region (13), and the second N-type column region (20), the P-base region (21) and the second heavily doped N + region (22) form a stacked structure; one side of the laminated structure is provided with a gate oxide layer (18), and the other side is provided with a first thin oxide layer (23) along the longitudinal direction;
the lower surface of the gate oxide layer (18) is in contact with a part of the first N-type column region (13), a part of the P-body region (15) and a part of the first heavily doped N + region (16); a second thin oxide layer (24) is arranged on one side, away from the laminated structure, of the first thin oxide layer (23), and the second thin oxide layer (24) is in contact with part of the first N-type column region (13) and part of the P-body region (15); a field oxide layer (26) is arranged on one side, away from the first thin oxide layer (23), of the second thin oxide layer (24), and the field oxide layer (26) is in contact with a part of the first heavily doped N + region (16); the gate electrode (19) is embedded in the gate oxide layer (18), the gate electrode (19) is positioned above the P-body region (15) and covers the P-body region (15), the width of the longitudinal gate oxide layer (25) on one side, close to the laminated structure, of the gate electrode (19) is the same as the thickness of the gate oxide layer (18) below the gate electrode (19), and the height of the gate electrode (19) is higher than that of the P-base region (21); the first thin oxide layer (23) and the second thin oxide layer (24) have the same thickness, and the thickness is smaller than the width of the longitudinal gate oxide layer (25); the source electrode (17) is arranged on the surface of the device, and the source electrode (17) is in contact with the upper surfaces of a part of the first heavily doped N + region (16) and the P-body region (15), the two side surfaces and the upper surface of the field oxide layer (26), one side surface and the upper surface of the gate oxide layer (18), the upper surface of the second thin oxide layer (24) and one side surface of the first thin oxide layer (23).
2. The dual-channel superjunction VDMOS device of claim 1, wherein: the second N-type column region (20) and the first N-type column region (13) have the same doping concentration, and the thickness of the second N-type column region (20) is adjustable.
3. The dual-channel superjunction VDMOS device of claim 1, wherein: the P-base region (21) and the P-body region (15) have the same doping concentration, and the thickness of the P-base region (21) is adjustable.
4. The dual-channel superjunction VDMOS device of claim 1, wherein: the second heavily doped N + region (22) and the first heavily doped N + region (16) have the same doping concentration, and the thickness of the second heavily doped N + region (22) is adjustable.
5. The dual-channel superjunction VDMOS device of claim 1, wherein: the thickness of the second thin oxide layer (24) and the vertical gate oxide layer (25) is adjustable.
6. The dual-channel superjunction VDMOS device of claim 1, wherein: the second N-type column region (20), the P-base region (21) and the second heavily doped N + region (22) have the same width.
7. The dual-channel superjunction VDMOS device of claim 1, wherein: the heavily doped semiconductor substrate (12) is N-type or P-type.
8. A method for manufacturing a double-channel super junction VDMOS device according to any claim 1 to 7, comprising the steps of:
(1) extending a film with the same doping concentration as that of the first N-type column region (13) on the heavily doped semiconductor substrate (12), etching a groove of the P-type column region (14) on the film, and forming the P-type column region (14) by adopting a multi-time extending or filling method;
(2) forming a P-body region (15) by means of ion implantation or diffusion, and forming a first heavily doped N + region (16) by means of ion implantation or diffusion;
(3) oxidizing to form a field oxide layer (26), etching a window of a gate electrode (19), forming a gate oxide layer (18) and a longitudinal gate oxide layer (25), and depositing to form the gate electrode (19);
(4) etching an epitaxial window of a second N-type column region (20) on the field oxide layer (26), epitaxially forming a second N-type column region (20) and a P-base region (21), and performing ion implantation to form a second heavily doped N + region (22);
(5) etching a source electrode (17) window to form a first thin oxide layer (23) and a second thin oxide layer (24), and metalizing to form a source electrode (17);
(6) the back side is metallized to form a drain electrode (11).
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