CN111768739A - Pixel circuit, driving method thereof and display device - Google Patents
Pixel circuit, driving method thereof and display device Download PDFInfo
- Publication number
- CN111768739A CN111768739A CN202010754246.3A CN202010754246A CN111768739A CN 111768739 A CN111768739 A CN 111768739A CN 202010754246 A CN202010754246 A CN 202010754246A CN 111768739 A CN111768739 A CN 111768739A
- Authority
- CN
- China
- Prior art keywords
- node
- circuit
- signal
- light
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
Abstract
The application provides a pixel circuit, a driving method thereof and a display device, and belongs to the technical field of display. The reset circuit can output a reference signal for resetting the first node to the first node connected with the light-emitting drive circuit, the light-emitting control circuit can output a reference signal for resetting the second node to the second node connected with the light-emitting drive circuit, and the light-emitting control circuit can control the on-off state of the detection signal line connected with the external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.
Background
Each pixel in the display substrate generally includes a light-emitting element and a pixel circuit connected to each other, and the pixel circuit can output a driving current to the light-emitting element to drive the light-emitting element to emit light. However, the drive current output from the pixel circuit to the light-emitting element is likely to be abnormal due to the influence of the threshold voltage shift of the transistor in the pixel circuit.
In the related art, in order to solve the problem of abnormal driving current output to the light emitting element due to threshold voltage drift, the voltage of the light emitting element may be collected, and the threshold voltage of the transistor may be externally compensated based on the collected voltage.
However, since the external compensation is not performed in real time, the external compensation is affected by the hysteresis effect of the transistor, the luminance of different light emitting elements is different, short-term afterimages are likely to appear on the display substrate, and the display effect is poor.
Disclosure of Invention
The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device, which can solve the problem of poor display effect of a display substrate in the related art, and the technical scheme is as follows:
in one aspect, a pixel circuit is provided, the pixel circuit including: a light emission control circuit, a reset circuit and a light emission drive circuit;
the light-emitting control circuit is respectively connected with a grid signal end, a data signal end, a scanning signal end, a detection signal line, a light-emitting control signal end, a first node, a second node and a light-emitting element, and the detection signal line is used for being connected with an external compensation circuit; the light-emitting control circuit is used for responding to a gate driving signal provided by the gate signal end, controlling the on-off state of the first node and the data signal end, responding to a scanning signal provided by the scanning signal end, controlling the on-off state of the second node and the detection signal line, and responding to a light-emitting control signal provided by the light-emitting control signal end, and controlling the on-off state of the second node and the light-emitting element;
the reset circuit is respectively connected with a reset signal end, a reference signal end and the first node, and is used for responding to a reset signal provided by the reset signal end and controlling the on-off state of the reference signal end and the first node;
the light-emitting driving circuit is respectively connected with a direct current power supply end, the first node and the second node, and the light-emitting driving circuit is used for responding to the potential of the first node and controlling the on-off state of the direct current power supply end and the second node.
Optionally, the reset circuit includes: a reset transistor;
the grid electrode of the reset transistor is connected with the reset signal end, the first pole of the reset transistor is connected with the reference signal end, and the second pole of the reset transistor is connected with the first node.
Optionally, the reset transistor is a low temperature polysilicon LTPS double gate transistor.
Optionally, the light emission control circuit includes: a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit and a light emission control sub-circuit;
the data writing sub-circuit is respectively connected with the grid signal end, the data signal end and the first node, and is used for responding to the grid driving signal and controlling the on-off state of the data signal end and the first node;
the compensation sub-circuit is respectively connected with the scanning signal end, the detection signal line and the second node, and is used for responding to the scanning signal and controlling the on-off state of the detection signal line and the second node;
the storage sub-circuit is respectively connected with the first node and the second node, and is used for adjusting the potential of the first node according to the potential of the second node;
the light-emitting control sub-circuit is respectively connected with the light-emitting control signal end, the second node and the light-emitting element, and is used for responding to the light-emitting control signal and controlling the on-off state of the second node and the light-emitting element.
Optionally, the data writing sub-circuit includes a transistor which is a low temperature polysilicon LTPS double gate transistor.
Optionally, the pixel circuit further includes: a switching circuit;
the switch circuit is respectively connected with a third node, the scanning signal end and the first node, and the switch circuit is used for responding to the scanning signal and controlling the on-off state of the first node and the third node;
wherein the third node is further connected to the data write sub-circuit and the reset circuit, respectively.
Optionally, the switching circuit includes: a switching transistor;
the grid electrode of the switch transistor is connected with the scanning signal end, the first pole of the switch transistor is connected with the third node, and the second pole of the switch transistor is connected with the first node.
Optionally, the switching transistor is an LTPS double-gate transistor, or an oxide transistor.
In another aspect, a driving method of a pixel circuit is provided, the method including:
in the reset stage, the potential of a reset signal provided by a reset signal terminal and the potential of a scanning signal provided by a scanning signal terminal are both first potentials, a reset circuit responds to the reset signal and controls a reference signal terminal to be conducted with a first node, a light-emitting control circuit responds to the scanning signal and controls a second node to be conducted with a detection signal line, the reference signal terminal outputs a first reference signal to the first node, and the detection signal line outputs a second reference signal to the second node;
in a data writing stage, the potential of a gate driving signal provided by a gate signal terminal and the potential of a scanning signal are both a first potential, the light emission control circuit controls the first node to be conducted with a data signal terminal in response to the gate driving signal, and controls the second node to be conducted with a detection signal line in response to the scanning signal, the data signal terminal outputs a data signal to the first node, the detection signal line outputs the second reference signal to the second node, and the data signal is a signal obtained by an external compensation circuit compensating an initial data signal based on a signal acquired by the detection signal line;
and in the light emitting stage, the potential of a light emitting control signal provided by the light emitting control signal end is a first potential, and the light emitting control circuit responds to the light emitting control signal and controls the conduction of the second node and the light emitting element.
In still another aspect, there is provided a display device including: the pixel circuit comprises a plurality of pixels, an external compensation circuit and a source electrode driving circuit connected with the external compensation circuit; each of the pixels includes: a light emitting element, and the pixel circuit as described in the above aspect;
the source electrode driving circuit is respectively connected with the data signal end connected with each pixel circuit, and is used for providing data signals for the data signal end;
each of the pixel circuits is connected to a detection signal line, each of the pixel circuits is configured to output a potential of a second node in the pixel circuit to the external compensation circuit through the detection signal line, and the external compensation circuit is configured to adjust a voltage of a data signal input to the source driver circuit according to the potential of the second node.
To sum up, the beneficial effects brought by the technical scheme provided by the embodiment of the present disclosure at least can include:
the embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device. The pixel circuit includes a light emission control circuit, a reset circuit, and a light emission driving circuit. The reset circuit can output a reference signal for resetting the first node to the first node connected with the light-emitting drive circuit, the light-emitting control circuit can output a reference signal for resetting the second node to the second node connected with the light-emitting drive circuit, and the light-emitting control circuit can control the on-off state of the detection signal line connected with the external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another pixel circuit provided in an embodiment of the present disclosure;
fig. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure;
fig. 7 is a timing diagram of signal terminals of a pixel circuit according to an embodiment of the disclosure;
fig. 8 is a timing diagram of signal terminals of another pixel circuit provided in the embodiments of the present disclosure;
fig. 9 is a timing diagram of signal terminals of another pixel circuit provided by the embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
The transistors used in all embodiments of the present disclosure may be field effect transistors or other devices having the same characteristics, and the transistors used in embodiments of the present disclosure are primarily switching transistors depending on the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole, or the drain is referred to as a first pole and the source is referred to as a second pole. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the signal output end is a drain. In addition, the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor that is turned on when the gate is at a low level and turned off when the gate is at a high level and an N-type switching transistor that is turned on when the gate is at a high level and turned off when the gate is at a low level. In addition, in each embodiment of the present disclosure, each of the plurality of signals corresponds to an effective potential and an ineffective potential, and the effective potential and the ineffective potential represent only 2 state quantities of the potential of the signal, and do not represent that the effective potential or the ineffective potential has a specific value throughout the text.
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 1, the pixel circuit may include: a light emission control circuit 10, a reset circuit 20, and a light emission driving circuit 30.
Referring to fig. 1, the light emission control circuit 10 may be connected with a gate signal terminal G1, a data signal terminal D1, a scan signal terminal S1, a sensing signal line SENSE, a light emission control signal terminal EM, a first node P1, a second node P2, and a light emitting element L1, respectively. The light emission control circuit 10 may be configured to control on/off states of the first node P1 and the data signal terminal D1 in response to a gate driving signal provided from a gate signal terminal G1, to control on/off states of the second node P2 and the sensing signal line SENSE in response to a scan signal provided from a scan signal terminal S1, and to control on/off states of the second node P2 and the light emitting element L1 in response to a light emission control signal provided from a light emission control signal terminal EM.
For example, the light emission control circuit 10 may control the first node P1 and the data signal terminal D1 to be turned on when the potential of the gate driving signal is a first potential, and control the first node P1 and the data signal terminal D1 to be turned off when the potential of the gate driving signal is a second potential. When the first node P1 and the data signal terminal D1 are turned on, the data signal terminal D1 outputs the data signal to the first node P1.
For another example, the light emission control circuit 10 may control the second node P2 to be turned on with the detection signal line SENSE when the potential of the scan signal is the first potential, and may control the second node P2 to be turned off with the detection signal line SENSE when the potential of the scan signal is the second potential. When the second node P2 is turned on by the SENSE signal line SENSE, the SENSE signal line SENSE can output a target signal (e.g., a reference signal for resetting the second node P2) to the second node P2 and collect the potential of the second node P2.
For another example, the light-emitting control circuit 10 can also control the second node P2 to be connected to the light-emitting element L1 when the potential of the light-emitting control signal is the first potential, and control the second node P2 to be disconnected from the light-emitting element L1 when the potential of the light-emitting control signal is the second potential. When the second node P2 is conducted with the light emitting device L1, the potential of the second node P2 is outputted to the light emitting device L1, and the light emitting device L1 emits light.
Optionally, in this embodiment of the disclosure, the first potential may be an active potential, the second potential may be an inactive potential, and the first potential may be a high potential with respect to the second potential.
It should be noted that the SENSE signal line SENSE may be used to connect an external compensation circuit. Accordingly, the external compensation circuit may read the potential on the sensing signal line SENSE (i.e., the potential of the second node P2), determine the magnitude of a relevant parameter (e.g., the threshold voltage Vth or the mobility k) affecting the light emission luminance based on the read potential, and adjust the data signal input to the source driving circuit based on the determined magnitude of the relevant parameter, so that the source driving circuit may provide the data signal to the data signal terminal D1 according to the adjusted data signal to achieve external compensation of the threshold voltage or the mobility.
With continued reference to fig. 1, the reset circuit 20 may be connected to the reset signal terminal R1, the reference signal terminal Vref, and the first node P1, respectively. The reset circuit 20 may be configured to control the on/off state of the reference signal terminal Vref and the first node P1 in response to a reset signal provided from the reset signal terminal R1.
For example, the reset circuit 20 may control the reference signal terminal Vref to be conductive with the first node P1 when the potential of the reset signal is a first potential, and control the reference signal terminal Vref to be disconnected with the first node P1 when the potential of the reset signal is a second potential. When the reference signal terminal Vref is conducted to the first node P1, the reference signal terminal Vref may output a first reference signal to the first node P1, so as to reset the first node P1.
By setting the reset circuit 20 to reset the first node P1 and the light-emission control circuit 10 to reset the second node P2, it is ensured that each pixel circuit can perform a display phase from the same operating state, and further, the short-term afterimage problem caused by the hysteresis effect is improved.
With continued reference to fig. 1, the light emission driving circuit 30 may be connected to the direct current power source ELVDD, the first node P1, and the second node P2, respectively. The light-emitting driving circuit 30 may be configured to control the on-off state of the direct current power source terminal ELVDD and the second node P2 in response to the potential of the first node P1.
For example, the light-emitting driving circuit 30 may control the dc power source terminal ELVDD to be turned on with the second node P2 when the potential of the first node P1 is a first potential, and to be turned off with the second node P2 when the potential of the first node P1 is a second potential. When the dc power source ELVDD is conducted to the second node P2, the dc power source ELVDD may output a dc power signal to the second node P2. Alternatively, the light-emitting driving circuit 30 may output a driving current to the second node P2 based on the potential of the first node P1 and the dc power signal, so that when the light-emitting control circuit 10 controls the second node P2 to be conducted with the light-emitting element L1, the driving current is further output to the light-emitting element L1, and the light-emitting element L1 emits light.
In summary, the embodiments of the present disclosure provide a pixel circuit including a light emission control circuit, a reset circuit, and a light emission driving circuit. The reset circuit can output a reference signal for resetting the first node to the first node connected with the light-emitting drive circuit, the light-emitting control circuit can output a reference signal for resetting the second node to the second node connected with the light-emitting drive circuit, and the light-emitting control circuit can control the on-off state of the detection signal line connected with the external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
Fig. 2 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure. As shown in fig. 2, the light emission control circuit 10 may include: a data writing sub-circuit 101, a compensation sub-circuit 102, a storage sub-circuit 103, and a light emission control sub-circuit 104.
Referring to fig. 2, the data writing sub-circuit 101 may be connected to the gate signal terminal G1, the data signal terminal D1, and the first node P1, respectively. The data write sub-circuit 101 may be configured to control the on/off states of the data signal terminal D1 and the first node P1 in response to a gate driving signal.
For example, the data writing sub-circuit 101 may control the data signal terminal D1 to be turned on with the first node P1 when the potential of the gate driving signal is a first potential, and control the data signal terminal D1 to be disconnected with the first node P1 when the potential of the gate driving signal is a second potential.
With continued reference to fig. 2, the compensation sub-circuit 102 may be connected to the scan signal terminal S1, the sensing signal line SENSE, and the second node P2, respectively. The compensation sub-circuit 102 may be used to control the on-off state of the SENSE signal line SENSE and the second node P2 in response to a scan signal.
For example, the compensation sub-circuit 102 may control the detection signal line SENSE to be conductive with the second node P2 when the potential of the scan signal is a first potential, and control the detection signal line SENSE to be disconnected with the second node P2 when the potential of the scan signal is a second potential.
With continued reference to FIG. 2, the storage sub-circuit 103 may be connected to a first node P1 and a second node P2, respectively. The memory sub-circuit 103 may be used to adjust the potential of the first node P1 according to the potential of the second node P2.
For example, the memory sub-circuit 103 may adjust the potential of the first node P1 according to the potential of the second node P2 through a coupling effect.
With continued reference to fig. 2, the light emission control sub-circuit 104 may be connected to the light emission control signal terminal EM, the second node P2, and the light emitting element L1, respectively. The light emitting control sub-circuit 104 may be configured to control the on/off states of the second node P2 and the light emitting element L1 in response to a light emitting control signal.
For example, the light emission control sub-circuit 104 may control the second node P2 to be turned on with the light emitting element L1 when the potential of the light emission control signal is a first potential, and control the second node P2 to be disconnected with the light emitting element L1 when the potential of the control signal is a second potential.
Fig. 3 is a schematic structural diagram of another pixel circuit provided in the embodiments of the present disclosure. As shown in fig. 3, the pixel circuit may further include: a switching circuit 40.
Referring to fig. 3, the switching circuit 40 may be connected to the third node P3, the scan signal terminal S1, and the first node P1, respectively. The switching circuit 40 may be used to control the on-off states of the first node P1 and the third node P3 in response to a scan signal. The third node P3 may be connected to the data writing sub-circuit 101 and the reset circuit 20, respectively.
For example, the switch circuit 40 may control the first node P1 and the third node P3 to be turned on when the potential of the scan signal is a first potential, and control the first node P1 and the third node P3 to be disconnected when the potential of the scan signal is a second potential.
Since the third node P3 is also connected to the data writing sub-circuit 101 and the reset circuit 20, when the first node P1 and the third node P3 are turned on, the data writing sub-circuit 101 can be turned on with the first node P1, and the reset circuit 20 can be turned on with the first node P1. Furthermore, when the data writing sub-circuit 101 is turned on with the first node P1 and the gate driving signal is at the first potential, the data signal terminal D1 can be turned on with the first node P1. When the reset circuit 20 is conducted to the first node P1 and the potential of the reset signal is the first potential, the reference signal terminal Vref can be conducted to the first node P1.
Taking the pixel circuit shown in fig. 2 as an example, fig. 4 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure. Taking the pixel circuit shown in fig. 3 as an example, fig. 5 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present disclosure.
Referring to fig. 4 and 5, the reset circuit 20 may include: the transistor T1 is reset.
A gate of the reset transistor T1 may be connected to a reset signal terminal R1, a first pole of the reset transistor T1 may be connected to a reference signal terminal Vref, and a second pole of the reset transistor T1 may be connected to the first node P1.
In the pixel circuit shown in fig. 2, since the reset circuit 20 is directly connected to the first node P1, it can be seen from fig. 4 that the second pole of the reset transistor T1 is directly connected to the first node P1. With the pixel circuit shown in fig. 3, since the reset circuit 20 is indirectly connected to the first node P1 through the switch circuit 40, it can be seen from fig. 5 that the second pole of the reset transistor T1 is connected to the third node P3 to which the switch circuit 40 is connected.
With continued reference to fig. 5, the switching circuit 40 may include: the transistor T2 is switched.
A gate of the switching transistor T2 may be connected to the scan signal terminal S1, a first pole of the switching transistor T2 may be connected to the third node P3, and a second pole of the switching transistor T2 may be connected to the first node P1.
With continued reference to fig. 4 and 5, the data write sub-circuit 101 may include: a data write transistor T3; the compensation sub-circuit 102 may include: a compensation transistor T4; the memory sub-circuit 103 may include: a storage capacitor C1; the emission control sub-circuit 104 may include: the light emission controlling transistor T5. The light emission driving circuit 30 may include: driving the transistor T6.
Among them, the gate of the data writing transistor T3 may be connected to the gate signal terminal G1, the first pole of the data writing transistor T3 may be connected to the data signal terminal D1, and the second pole of the data writing transistor T3 may be connected to the first node P1.
As with the reset transistor T1, for the pixel circuit shown in fig. 2, since the data write sub-circuit 101 is directly connected to the first node P1, it can be seen from fig. 4 that the second pole of the data write transistor T3 is directly connected to the first node P1. For the pixel circuit shown in fig. 3, since the data writing sub-circuit 101 is indirectly connected to the first node P1 through the switch circuit 40, it can be seen from fig. 5 that the second pole of the data writing transistor T3 is connected to the third node P3 to which the switch circuit 40 is connected.
A gate of the compensation transistor T4 may be connected to the scan signal terminal S1, a first pole of the compensation transistor T4 may be connected to the sensing signal line SENSE, and a second pole of the compensation transistor T4 may be connected to the second node P2.
One end of the storage capacitor C1 may be connected to the first node P1, and the other end of the storage capacitor C1 may be connected to the second node P2.
The gate of the light emission controlling transistor T5 may be connected to the light emission control signal terminal EM, the first pole of the light emission controlling transistor T5 may be connected to the second node P2, and the second pole of the light emission controlling transistor T5 may be connected to the light emitting element L1.
The gate of the driving transistor T6 may be connected to the first node P1, the first pole of the driving transistor T6 may be connected to the direct current power source ELVDD, and the second pole of the driving transistor T6 may be connected to the second node P2.
Optionally, in combination with the pixel circuit shown in fig. 4, since the reset transistor T1 and the data write transistor T3 are both directly connected to the first node P1 (i.e., the gate of the driving transistor T6), in order to effectively avoid the influence of the reset transistor T1 and the data write transistor T3, the potential of the gate of the driving transistor T6 has a leakage phenomenon in the display stage, and the reset transistor T1 and the data write transistor T3 may both be Low Temperature Polysilicon (LTPS) dual-gate transistors. Of course, the double-gate transistor may be made of other materials (e.g., amorphous silicon) than LTPS material. Alternatively, the reset transistor T1 and the data write transistor T3 may be both oxide (oxide) transistors.
Alternatively, in conjunction with the pixel circuit shown in fig. 5, since neither the reset transistor T1 nor the data write transistor T3 is directly connected to the first node P1, but is indirectly connected to the first node P1 through the switch transistor T2, that is, the switch transistor T2 is directly connected to the first node P1. Therefore, in order to effectively avoid the influence of the switching transistor T2, the potential of the gate of the driving transistor T6 may leak in the display period, and the switching transistor T2 may be only an LTPS double gate transistor, or an oxide transistor.
With continued reference to fig. 4 and 5, the light emitting element L1 is also connected to a power integrated circuit (power IC) 50. Among them, the power IC 50 may include a first transistor M1 and a second transistor M2.
Here, the gate of the first transistor M1 may be connected to the first switch control terminal SW1, the first pole may be connected to one terminal of the light emitting element L1, and the second pole may be connected to the dc power source terminal ELVDD. The first transistor M1 may control the on/off states of the light emitting element L1 and the dc power source ELVDD in response to a first switch control signal provided from the first switch control terminal SW 1.
For example, the first transistor M1 may control the light emitting element L1 to be turned on from the dc power source ELVDD when the potential of the first switch control signal is a first potential, and control the light emitting element L1 to be turned off from the dc power source ELVDD when the potential of the first switch control signal is a second potential. When the light emitting element L1 is turned on with the dc power source ELVDD, the dc power source ELVDD may output a dc power signal to the light emitting element L1, and the potential of the dc power signal may be the first potential.
The gate of the second transistor M2 may be connected to the second switch control terminal SW2, the first pole is connected to one terminal of the light emitting element L1, and the second pole is connected to the dc power source terminal ELVSS. The second transistor M2 may control the on/off states of the light emitting element L1 and the dc power source terminal ELVSS in response to a second switch control signal provided from the second switch control terminal SW 2.
For example, the second transistor M2 may control the light emitting element L1 to be connected to the dc power source terminal ELVSS when the potential of the second switch control signal is a first potential, and control the light emitting element L1 to be disconnected from the dc power source terminal ELVSS when the potential of the second switch control signal is a second potential. When the light emitting element L1 is turned on from the dc power source ELVSS, the dc power source ELVSS may output a dc power signal to the light emitting element L1, and the potential of the dc power signal may be the second potential.
In the embodiment of the present disclosure, when the external compensation is performed, the first switch control potential provided by the first switch control terminal SW1 may be a first potential, and the second switch control potential provided by the second switch control terminal SW2 may be a second potential. The direct current power source terminal ELVDD may be turned on with the light emitting element L1. In the light emission driving, the first switch control potential provided by the first switch control terminal SW1 may be the second potential, and the second switch control potential provided by the second switch control terminal SW2 may be the first potential. The direct current power source terminal ELVSS may be turned on with the light emitting element L1.
It should be noted that, in the embodiment of the present disclosure, the light-emitting control circuit 10 may have a structure including other number of transistors, such as a 6T1C structure, besides the structure of 3T1C (i.e., three transistors and one capacitor) shown in fig. 4 or fig. 5, which is not limited in the embodiment of the present disclosure.
It should be further noted that, in the embodiments of the present disclosure, each transistor included in the pixel circuit may be an N-type transistor. Accordingly, as described in the above embodiments, the first potential may be a high potential with respect to the second potential. Of course, each transistor included in the pixel circuit may be a P-type transistor. Accordingly, the first potential is a low potential relative to the second potential.
In summary, the embodiments of the present disclosure provide a pixel circuit including a light emission control circuit, a reset circuit, and a light emission driving circuit. The reset circuit can output a reference signal for resetting the first node to the first node connected with the light-emitting drive circuit, the light-emitting control circuit can output a reference signal for resetting the second node to the second node connected with the light-emitting drive circuit, and the light-emitting control circuit can control the on-off state of the detection signal line connected with the external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
Fig. 6 is a flowchart of a driving method of a pixel circuit according to an embodiment of the disclosure, which can be applied to the pixel circuit shown in any one of fig. 1 to 5. As shown in fig. 6, the method may include:
The data signal may be a signal obtained by compensating an initial data signal (i.e., a data signal input to the source driving circuit) by an external compensation circuit based on a signal collected by the detection signal line.
In summary, the embodiment of the present disclosure provides a driving method of a pixel circuit, in a reset phase, a reset circuit may output a reference signal for resetting a first node to a first node connected to a light-emitting driving circuit, a light-emitting control circuit may output a reference signal for resetting a second node to a second node connected to the light-emitting driving circuit, and the light-emitting control circuit may control on/off states of a detection signal line connected to an external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
With reference to fig. 4 and 5, before the reset phase (i.e., step 601) is performed, the threshold voltage Vth and the mobility k of the light emitting driving circuit (i.e., the driving transistor T6) may be externally compensated by an external compensation circuit, so as to ensure a better display effect. Taking the pixel circuit shown in fig. 4 and taking the transistors in the pixel circuit as N-type transistors as an example, the specific operation principle of the external compensation and the light-emitting driving will be described as follows:
FIG. 7 shows a timing diagram of the signal terminals during the threshold voltage sensing (i.e., Vth sensing) phase. As shown in fig. 7, the threshold voltage sensing phase includes three phases t11, t12 and t13, and in the three phases, the potential of the first control signal provided by the first switch control terminal SW1 is a first potential, the potential of the second control signal provided by the second switch control terminal SW2 is a second potential, the first transistor M1 in the power IC is turned on, and the second transistor M2 is turned off. Accordingly, the dc power supply terminal ELVDD is turned on with the light emitting element L1, and the dc power supply terminal ELVDD outputs a dc power supply signal at the first potential to the light emitting element L1.
With continued reference to fig. 7, at the stage T11, the potential of the gate driving signal provided by the gate signal terminal G1 and the potential of the scan signal provided by the scan signal terminal S1 are both the first potential, and the data writing transistor T3 and the compensation transistor T4 are both turned on. The data signal terminal D1 outputs a data signal at a first potential (e.g., the potential of the data signal may be Vdata) to the first node P1 through the data write transistor T3. The detection signal line SENSE outputs an initial signal (e.g., the potential of the initial signal may be Vinit) to the second node P2 through the compensation transistor T4 to effect resetting of the second node P2.
In a phase t12, the sensing signal line SENSE is controlled to be in a floating state, i.e., no voltage is supplied to the sensing signal line SENSE. The potentials of the gate driving signal and the scanning signal are still maintained at the first potential, and the data writing transistor T3 and the compensating transistor T4 are still maintained turned on. At this time, the data signal terminal D1 continues to output the data signal to the first node P1 through the data write transistor T3. And since the data signal terminal D1 outputs the data signal at the first potential to the first node P1 at the stage T11, the driving transistor T6 is turned on. In this stage T12, the dc power source ELVDD may be charged to the sensing signal line SENSE through the driving transistor T6 until the driving transistor T6 is turned off, and the charging time is typically about several hundred microseconds (μ s) to several milliseconds (ms). When the driving transistor T6 is turned off, the gate-source voltage difference Vgs thereof may be Vdata-Vth.
In addition, in the phases T11 and T12, the potential of the reset signal supplied from the reset signal terminal R1 and the potential of the emission control signal supplied from the emission control signal terminal EM are both kept at the second potential, and the reset transistor T1 and the emission control transistor T5 are both in the off state.
At stage t13, the external compensation circuit, i.e., the external compensation IC, provides the sampled signal (Hsync shown in fig. 10) with the first potential, and the external compensation IC (e.g., the analog-to-digital converter ADC in the external compensation IC) can start reading the potential on the sensing signal line SENSE. Further, the external compensation IC can calculate the threshold voltage Vth of the driving transistor T6 based on the read potential. At this point, sensing of the threshold voltage Vth is completed, which may also be referred to as sampling.
Fig. 8 shows a timing diagram of the signal terminals during the mobility sensing (i.e., k sensing) phase. As shown in fig. 8, the mobility sensing phase also includes three phases t21, t22, and t23 in total. And like the Vth sensing stage, in the three stages, the potential of the first control signal is the first potential, the potential of the second control signal is the second potential, the first transistor M1 in the power IC is turned on, and the second transistor M2 is turned off. The dc power source terminal ELVDD is turned on with the light emitting element L1, and the dc power source terminal ELVDD outputs a dc power source signal at the first potential to the light emitting element L1.
With continued reference to FIG. 8, the timing of the phase t21 is the same as the timing of the phase t11, and the timing of the phase t23 is the same as the timing of the phase t13, which are not repeated herein. In the phase T22, the detection signal line SENSE is controlled to be in a flowing state, and the gate-source voltage difference of the driving transistor T6 is controlled to be fixed to Vdata-Vinit so that the driving transistor T6 is in a saturation operating region. In conjunction with the timing shown in fig. 8, the potentials of the first node P1 and the second node P2 change simultaneously at the stage T12, thereby ensuring that the driving transistor T6 can operate in the saturation region. And at the stage T12, only the potential of the scan signal provided by the scan signal terminal S1 is the first potential, and the compensation transistor T4 is turned on. The SENSE signal line SENSE is charged by a fixed current, and referring to fig. 8, the charging time may be represented as t. Further, at the stage T23, the external compensation IC may read the potential on the SENSE signal line SENSE and calculate the mobility k of the driving transistor T6 based on the read potential.
Optionally, the mobility k may satisfy:
k＝2*Csense*(Vsense-Vinit)/t/(Vdata-Vinit)2. Where Csense is the capacitance on the SENSE signal line SENSE and Vsense is the voltage on the SENSE signal line SENSE.
Fig. 9 shows a timing chart of each signal terminal in the light emission driving phase. As shown in fig. 9, the light-emitting driving phase includes three phases, i.e., a reset phase t31, a data writing phase t32 and a light-emitting phase t33, in which the potential of the first control signal provided by the first switch control terminal SW1 is the second potential, the potential of the second control signal provided by the second switch control terminal SW2 is the first potential, the first transistor M1 in the power IC is turned off, and the second transistor M2 is turned on. Accordingly, the dc power supply terminal ELVSS is turned on with the light emitting element L1, and the dc power supply terminal ELVSS outputs a dc power supply signal at the second potential to the light emitting element L1. And the external compensation IC always provides the sampling signal at the second potential, and further, the external compensation IC does not read the potential of the sensing signal line SENSE.
With continued reference to fig. 9, in the reset phase T31, the potential of the reset signal provided by the reset signal terminal R1 and the potential of the scan signal may both be the first potential, and the reset transistor T1 and the compensation transistor T4 may both be turned on. The reference signal terminal Vref outputs the first reference signal at the second potential to the first node P1 through the reset transistor T1. The detection signal line SENSE outputs the second reference signal at the second potential to the second node P2 through the compensation transistor T4. Assuming that the potential of the first reference signal is Vref0 and the potential of the second reference signal is Vref1, the potential difference between the first node P1 and the second node P2 is: vref0-Vref 1. Namely, the gate-source voltage difference Vgs of the driving transistor T6 is Vref0-Vref 1. In the reset period T31, the gate driving signal and the light emitting control signal are both at the second potential, and the data writing transistor T3 and the light emitting control transistor T5 are both turned off.
In the data writing phase T32, the potential of the gate driving signal jumps to the first potential, and the potential of the scan signal remains at the first potential, and the data writing transistor T3 and the compensation transistor T4 are both turned on. The data signal terminal D1 outputs a data signal to the first node P1 through the data write transistor T3. The detection signal line SENSE continues to output the second reference signal at the second potential to the second node P2 through the compensation transistor T4. And in the data writing period T32, the potential of the reset signal jumps to the second potential, the potential of the emission control signal is maintained at the second potential, and both the reset transistor T1 and the emission control transistor T5 are turned off.
In the light emitting period T33, the potential of the light emitting control signal jumps to the first potential, the light emitting control transistor T5 is turned on, and the second node P2 and the light emitting element L1 are turned on. The driving transistor T6 outputs a driving current generated based on the potential of the first node P1 and the potential of the dc power signal supplied from the dc power source ELVDD to the light emitting element L1 via the light emission controlling transistor T5, and the light emitting element L1 emits light. In the light-emitting period t33, the potential of the reset signal is maintained at the second potential, the potential of the gate drive signal jumps to the second potential, and the potential of the scan signal also jumps to the second potential. Reset transistor T1, data write transistor T3, and complementThe transistors T4 are all off. Optionally, the driving current I may satisfy: i-1/2 k (Vdata-Vref1-Vth)2。
With reference to the timing shown in fig. 7 to 9, before entering the light emitting driving phase, the external compensation IC may compensate the data signal based on the calculated threshold voltage Vth and mobility k, so that the driving current finally output to the light emitting element L1 is independent of the threshold voltage Vth and the mobility k, thereby avoiding the shift of the threshold voltage Vth or the mobility k, and ensuring the display effect due to the influence on the light emitting brightness of the light emitting element L1.
In fig. 7 to 9, the first potential is represented by ON, and the second potential is represented by OFF. The threshold voltage sensing phase shown in fig. 7 and the mobility sensing phase shown in fig. 8 may be performed in a blanking phase, such as a vertical blanking (VBlank) phase. Alternatively, the display device may be turned off. The embodiments of the present disclosure do not limit this. For the pixel circuit shown in fig. 5, the timing diagrams of the various stages can refer to the timing diagrams shown in fig. 7 to fig. 9, and are not repeated herein. Compared with the internal compensation, the external compensation has a larger compensation range, can compensate the drift of the mobility, is not limited by the line period in the compensation time, and can be applied to high frame frequency driving.
In summary, the embodiment of the present disclosure provides a driving method of a pixel circuit, in a reset phase, a reset circuit may output a reference signal for resetting a first node to a first node connected to a light-emitting driving circuit, a light-emitting control circuit may output a reference signal for resetting a second node to a second node connected to the light-emitting driving circuit, and the light-emitting control circuit may control on/off states of a detection signal line connected to an external compensation circuit and the second node. Therefore, by flexibly controlling the potential of each signal end, after threshold voltage is reliably compensated based on an external compensation technology, each pixel circuit enters a display stage of driving the light-emitting element to emit light under the same initial state. Thus, the problem of short-term afterimage caused by the hysteresis effect of the transistor is improved. The display substrate adopting the pixel circuit has good display effect.
Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 10, the display device may include: a plurality of pixels 01, an external compensation circuit 02, and a source driver circuit 03 connected to the external compensation circuit 02. Each pixel 01 may include: a light emitting element L1, and a pixel circuit 011 as shown in any one of fig. 1 to 5.
The source driver circuit 03 may be connected to a data signal terminal to which each pixel circuit 01 is connected, respectively, and the source driver circuit 03 may supply a data signal to the data signal terminal. The detection signal lines to which each pixel circuit is connected may each be connected to an external compensation circuit 02 (a specific connection relationship is not shown in fig. 10).
Each pixel circuit 01 can output the potential of the second node in the pixel circuit to the external compensation circuit 02 through the detection signal line, the external compensation circuit 02 can adjust the voltage of the data signal input to the source driving circuit 03 according to the potential of the second node, and the source driving circuit 03 can provide the data signal to the data signal terminal according to the adjusted voltage of the data signal, so that the external compensation of the threshold voltage of the driving transistor is realized.
Optionally, the display device may be: an Organic Light Emitting Diode (OLED) display device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and any other product or component having a display function.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the pixel circuit, the sub-circuits and the transistors described above may refer to the corresponding processes in the method embodiments, and are not described herein again.
The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.
Claims (10)
1. A pixel circuit, comprising: a light emission control circuit, a reset circuit and a light emission drive circuit;
the light-emitting control circuit is respectively connected with a grid signal end, a data signal end, a scanning signal end, a detection signal line, a light-emitting control signal end, a first node, a second node and a light-emitting element, and the detection signal line is used for being connected with an external compensation circuit; the light-emitting control circuit is used for responding to a gate driving signal provided by the gate signal end, controlling the on-off state of the first node and the data signal end, responding to a scanning signal provided by the scanning signal end, controlling the on-off state of the second node and the detection signal line, and responding to a light-emitting control signal provided by the light-emitting control signal end, and controlling the on-off state of the second node and the light-emitting element;
the reset circuit is respectively connected with a reset signal end, a reference signal end and the first node, and is used for responding to a reset signal provided by the reset signal end and controlling the on-off state of the reference signal end and the first node;
the light-emitting driving circuit is respectively connected with a direct current power supply end, the first node and the second node, and the light-emitting driving circuit is used for responding to the potential of the first node and controlling the on-off state of the direct current power supply end and the second node.
2. The pixel circuit according to claim 1, wherein the reset circuit comprises: a reset transistor;
the grid electrode of the reset transistor is connected with the reset signal end, the first pole of the reset transistor is connected with the reference signal end, and the second pole of the reset transistor is connected with the first node.
3. The pixel circuit according to claim 2, wherein the reset transistor is a Low Temperature Polysilicon (LTPS) double gate transistor.
4. The pixel circuit according to any one of claims 1 to 3, wherein the emission control circuit comprises: a data writing sub-circuit, a compensation sub-circuit, a storage sub-circuit and a light emission control sub-circuit;
the data writing sub-circuit is respectively connected with the grid signal end, the data signal end and the first node, and is used for responding to the grid driving signal and controlling the on-off state of the data signal end and the first node;
the compensation sub-circuit is respectively connected with the scanning signal end, the detection signal line and the second node, and is used for responding to the scanning signal and controlling the on-off state of the detection signal line and the second node;
the storage sub-circuit is respectively connected with the first node and the second node, and is used for adjusting the potential of the first node according to the potential of the second node;
the light-emitting control sub-circuit is respectively connected with the light-emitting control signal end, the second node and the light-emitting element, and is used for responding to the light-emitting control signal and controlling the on-off state of the second node and the light-emitting element.
5. The pixel circuit according to claim 4, wherein the data writing sub-circuit comprises transistors that are Low Temperature Polysilicon (LTPS) double gate transistors.
6. The pixel circuit according to claim 4, further comprising: a switching circuit;
the switch circuit is respectively connected with a third node, the scanning signal end and the first node, and the switch circuit is used for responding to the scanning signal and controlling the on-off state of the first node and the third node;
wherein the third node is further connected to the data write sub-circuit and the reset circuit, respectively.
7. The pixel circuit according to claim 6, wherein the switching circuit comprises: a switching transistor;
the grid electrode of the switch transistor is connected with the scanning signal end, the first pole of the switch transistor is connected with the third node, and the second pole of the switch transistor is connected with the first node.
8. The pixel circuit according to claim 7, wherein the switching transistor is an LTPS double gate transistor, or an oxide transistor.
9. A method of driving a pixel circuit, the method comprising:
in the reset stage, the potential of a reset signal provided by a reset signal terminal and the potential of a scanning signal provided by a scanning signal terminal are both first potentials, a reset circuit responds to the reset signal and controls a reference signal terminal to be conducted with a first node, a light-emitting control circuit responds to the scanning signal and controls a second node to be conducted with a detection signal line, the reference signal terminal outputs a first reference signal to the first node, and the detection signal line outputs a second reference signal to the second node;
in a data writing stage, the potential of a gate driving signal provided by a gate signal terminal and the potential of a scanning signal are both a first potential, the light emission control circuit controls the first node to be conducted with a data signal terminal in response to the gate driving signal, and controls the second node to be conducted with a detection signal line in response to the scanning signal, the data signal terminal outputs a data signal to the first node, the detection signal line outputs the second reference signal to the second node, and the data signal is a signal obtained by an external compensation circuit compensating an initial data signal based on a signal acquired by the detection signal line;
and in the light emitting stage, the potential of a light emitting control signal provided by the light emitting control signal end is a first potential, and the light emitting control circuit responds to the light emitting control signal and controls the conduction of the second node and the light emitting element.
10. A display device, characterized in that the display device comprises: the pixel circuit comprises a plurality of pixels, an external compensation circuit and a source electrode driving circuit connected with the external compensation circuit; each of the pixels includes: a light emitting element, and the pixel circuit according to any one of claims 1 to 8;
the source electrode driving circuit is respectively connected with the data signal end connected with each pixel circuit, and is used for providing data signals for the data signal end;
each of the pixel circuits is connected to a detection signal line, each of the pixel circuits is configured to output a potential of a second node in the pixel circuit to the external compensation circuit through the detection signal line, and the external compensation circuit is configured to adjust a voltage of a data signal input to the source driver circuit according to the potential of the second node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010754246.3A CN111768739B (en) | 2020-07-30 | 2020-07-30 | Pixel circuit, driving method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010754246.3A CN111768739B (en) | 2020-07-30 | 2020-07-30 | Pixel circuit, driving method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111768739A true CN111768739A (en) | 2020-10-13 |
| CN111768739B CN111768739B (en) | 2021-11-23 |
Family
ID=72728088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010754246.3A Active CN111768739B (en) | 2020-07-30 | 2020-07-30 | Pixel circuit, driving method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111768739B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113421511A (en) * | 2021-06-17 | 2021-09-21 | 昆山国显光电有限公司 | Display panel driving method, driving device and display device |
| CN113611248A (en) * | 2021-08-11 | 2021-11-05 | 合肥京东方卓印科技有限公司 | Display panel, driving method of switch circuit of display panel and display device |
| CN113838421A (en) * | 2021-07-30 | 2021-12-24 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display panel |
| CN114005396A (en) * | 2021-10-29 | 2022-02-01 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN114283720A (en) * | 2022-01-04 | 2022-04-05 | 京东方科技集团股份有限公司 | Display panel, method for testing defective pixels of display panel and display device |
| WO2023024072A1 (en) * | 2021-08-27 | 2023-03-02 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, and display apparatus |
| WO2023050165A1 (en) * | 2021-09-29 | 2023-04-06 | 京东方科技集团股份有限公司 | Pixel circuit, driving method, display substrate, and display apparatus |
| WO2023151194A1 (en) * | 2022-02-10 | 2023-08-17 | 北京小米移动软件有限公司 | Pixel unit circuit, display panel, and compensation method and apparatus for pixel unit |
| GB2620507A (en) * | 2021-01-05 | 2024-01-10 | Boe Technology Group Co Ltd | Pixel circuit and driving method therefor and display panel |
| WO2024045115A1 (en) * | 2022-09-01 | 2024-03-07 | 京东方科技集团股份有限公司 | Pixel circuit, pixel driving circuit, and display device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968954A (en) * | 2011-08-30 | 2013-03-13 | 乐金显示有限公司 | Organic light emitting diode display device for sensing pixel current and method for sensing pixel current thereof |
| US20170154578A1 (en) * | 2015-12-01 | 2017-06-01 | Samsung Display Co., Ltd. | Display panel and display device having the same |
| CN107731171A (en) * | 2017-11-29 | 2018-02-23 | 合肥京东方光电科技有限公司 | Image element circuit and its control method, display base plate, display device |
| CN107863067A (en) * | 2017-12-05 | 2018-03-30 | 京东方科技集团股份有限公司 | Display device, image element circuit and its compensation method and compensation device |
| CN110520923A (en) * | 2018-09-20 | 2019-11-29 | 京东方科技集团股份有限公司 | The pixel circuit, pixel compensation method and display equipment of signal wire are shared with the time |
| CN111261114A (en) * | 2020-03-25 | 2020-06-09 | 京东方科技集团股份有限公司 | Display panel and pixel compensation circuit |
-
2020
- 2020-07-30 CN CN202010754246.3A patent/CN111768739B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968954A (en) * | 2011-08-30 | 2013-03-13 | 乐金显示有限公司 | Organic light emitting diode display device for sensing pixel current and method for sensing pixel current thereof |
| US20170154578A1 (en) * | 2015-12-01 | 2017-06-01 | Samsung Display Co., Ltd. | Display panel and display device having the same |
| CN107731171A (en) * | 2017-11-29 | 2018-02-23 | 合肥京东方光电科技有限公司 | Image element circuit and its control method, display base plate, display device |
| CN107863067A (en) * | 2017-12-05 | 2018-03-30 | 京东方科技集团股份有限公司 | Display device, image element circuit and its compensation method and compensation device |
| CN110520923A (en) * | 2018-09-20 | 2019-11-29 | 京东方科技集团股份有限公司 | The pixel circuit, pixel compensation method and display equipment of signal wire are shared with the time |
| CN111261114A (en) * | 2020-03-25 | 2020-06-09 | 京东方科技集团股份有限公司 | Display panel and pixel compensation circuit |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2620507A (en) * | 2021-01-05 | 2024-01-10 | Boe Technology Group Co Ltd | Pixel circuit and driving method therefor and display panel |
| CN113421511B (en) * | 2021-06-17 | 2022-05-03 | 昆山国显光电有限公司 | Display panel driving method, driving device and display device |
| CN113421511A (en) * | 2021-06-17 | 2021-09-21 | 昆山国显光电有限公司 | Display panel driving method, driving device and display device |
| CN113838421A (en) * | 2021-07-30 | 2021-12-24 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display panel |
| WO2023005621A1 (en) * | 2021-07-30 | 2023-02-02 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor and display panel |
| CN113611248B (en) * | 2021-08-11 | 2023-08-11 | 合肥京东方卓印科技有限公司 | Display panel, driving method of switch circuit of display panel and display device |
| CN113611248A (en) * | 2021-08-11 | 2021-11-05 | 合肥京东方卓印科技有限公司 | Display panel, driving method of switch circuit of display panel and display device |
| WO2023024072A1 (en) * | 2021-08-27 | 2023-03-02 | 京东方科技集团股份有限公司 | Pixel circuit and driving method therefor, and display apparatus |
| WO2023050165A1 (en) * | 2021-09-29 | 2023-04-06 | 京东方科技集团股份有限公司 | Pixel circuit, driving method, display substrate, and display apparatus |
| CN114005396A (en) * | 2021-10-29 | 2022-02-01 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN114005396B (en) * | 2021-10-29 | 2024-01-16 | 昆山国显光电有限公司 | Pixel circuit and display panel |
| CN114283720A (en) * | 2022-01-04 | 2022-04-05 | 京东方科技集团股份有限公司 | Display panel, method for testing defective pixels of display panel and display device |
| CN114283720B (en) * | 2022-01-04 | 2023-12-26 | 京东方科技集团股份有限公司 | Display panel, testing method of defective pixels of display panel and display device |
| WO2023151194A1 (en) * | 2022-02-10 | 2023-08-17 | 北京小米移动软件有限公司 | Pixel unit circuit, display panel, and compensation method and apparatus for pixel unit |
| WO2024045115A1 (en) * | 2022-09-01 | 2024-03-07 | 京东方科技集团股份有限公司 | Pixel circuit, pixel driving circuit, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111768739B (en) | 2021-11-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111768739B (en) | Pixel circuit, driving method thereof and display device | |
| CN109545145B (en) | Pixel circuit, driving method thereof and display device | |
| US11030959B2 (en) | Pixel circuit and driving method thereof, and display device | |
| US10714005B2 (en) | Pixel compensation circuit and method of driving the same, display panel, and display device | |
| CN107342044B (en) | Pixel circuit, display panel and driving method of pixel circuit | |
| CN107358916B (en) | Pixel circuit, driving method thereof, electroluminescent display panel and display device | |
| US10535302B2 (en) | Pixel circuit, method for driving the same, and display apparatus | |
| US9852687B2 (en) | Display device and driving method | |
| CN109801592B (en) | Pixel circuit, driving method thereof and display substrate | |
| CN111105751B (en) | Display device, method for driving the same, and electronic apparatus | |
| CN111179854A (en) | Pixel driving circuit, driving method thereof and display device | |
| CN109817165B (en) | Pixel driving circuit, pixel driving method, display panel and display device | |
| EP3654324A1 (en) | Amoled pixel driving circuit and pixel driving method | |
| CN108777131B (en) | AMOLED pixel driving circuit and driving method | |
| US11798473B2 (en) | Pixel driving circuit and display panel | |
| JP2018105917A (en) | Display panel and display device | |
| CN110706654A (en) | OLED pixel compensation circuit and OLED pixel compensation method | |
| CN109389937B (en) | Pixel circuit, display device and driving method of pixel circuit | |
| CN111613178A (en) | Pixel circuit, driving method thereof, display substrate and display device | |
| US10210799B2 (en) | Pixel compensation circuit and display device | |
| KR20100054001A (en) | Display device and driving method thereof | |
| US11024232B2 (en) | Pixel driving circuit and driving method therefor, and display panel | |
| CN112802429B (en) | Pixel driving circuit and display panel | |
| US20220199013A1 (en) | Display device | |
| US11508301B2 (en) | Pixel circuit, display substrate, display panel and pixel driving method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |