CN111755346B - Integrated chip and manufacturing process thereof - Google Patents

Integrated chip and manufacturing process thereof Download PDF

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Publication number
CN111755346B
CN111755346B CN202010618543.5A CN202010618543A CN111755346B CN 111755346 B CN111755346 B CN 111755346B CN 202010618543 A CN202010618543 A CN 202010618543A CN 111755346 B CN111755346 B CN 111755346B
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Prior art keywords
chip
plastic package
substrate
conductive layer
pin
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CN111755346A (en
Inventor
陈建超
于上家
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Qingdao Goertek Microelectronic Research Institute Co ltd
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Qingdao Goertek Microelectronic Research Institute Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention provides an integrated chip and a manufacturing process thereof, comprising the following steps: the first chip is inversely arranged on the first substrate and is electrically connected with the first substrate; injecting plastic modified plastics to the first substrate to form a first plastic package part, and packaging the first chip by using the first plastic package part; forming a through hole at a position of the first plastic package corresponding to the pin of the first chip; filling a conductor into the via hole to connect the pin of the first chip with the surface of the first plastic package part; activating the surface of the first plastic package by laser to form a conductive layer; and forming a circuit layer on the surface of the first plastic package part through a chemical plating process, wherein the circuit layer is connected with the conductive layer. According to the technical scheme, the surface of the first plastic package part is activated, and the through hole and the circuit layer are formed in the first plastic package part, so that the pins on the first chip can be connected with the circuit layer through the through hole, the use of the adapter plate is reduced, the structure is simplified, and the integration level is improved.

Description

Integrated chip and manufacturing process thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an integrated chip manufacturing process and an integrated chip.
Background
The rapid development of electronic products is the main driving force for improving the packaging technology at present, and the miniaturization, high density, high frequency, high speed, high performance, high reliability and low cost of electronic products are the mainstream development direction of advanced packaging. System-in-package is one of the most important and potentially most promising technologies for such high-density system integration. Among them, Package-on-Package (PoP) is one of three-dimensional stacking technologies developed for IC packaging of mobile devices and available for system integration.
In the prior art, the stacked package structure needs to be integrated in the vertical direction through the horizontal direction of a substrate adapter plate or laser perforation ball-planting connection of a plastic package body, and different chips and/or passive elements cannot be directly integrated in the horizontal direction of the surface of the plastic package body.
Disclosure of Invention
The invention mainly aims to provide an integrated chip and a manufacturing process thereof, and aims to solve the technical problem that different chips and/or passive elements cannot be directly integrated on the surface of a plastic package in the horizontal direction in the prior art.
In order to achieve the above object, the present invention provides an integrated chip manufacturing process, which comprises the following steps:
the method comprises the steps that a first chip is inversely arranged on a first substrate and is electrically connected with the first substrate;
injecting modified plastics to the first substrate to form a first plastic package piece, and packaging the first chip by using the first plastic package piece;
forming a through hole at a position of the first plastic package corresponding to the pin of the first chip;
filling an electric conductor into the via hole so as to connect the pin of the first chip with the surface of the first plastic package part;
activating the surface of the first plastic package by laser to form a conductive layer;
and forming a circuit layer on the surface of the first plastic package part through a chemical plating process, wherein the circuit layer is connected with the conductive layer.
Optionally, the step of forming a via hole at a position on the first plastic package corresponding to the pin of the chip includes:
acquiring a first projection position of the first chip on the first substrate according to the position of the first chip on the first substrate;
acquiring a preset position of a pin of the first chip on the first chip, and acquiring a second projection position of the pin of the first chip on the first substrate according to the first projection position and the preset position;
and performing laser on the first plastic package part at a position corresponding to the second projection position to form the through hole, so that the pin of the chip is in contact with air through the through hole.
Optionally, forming a via hole in the position of the first plastic package corresponding to the pin of the first chip; filling an electric conductor into the via hole so as to replace the step of connecting the pin of the first chip with the surface of the first plastic package part with the following steps:
and polishing the surfaces of the first plastic package part corresponding to the pins of the first chip until the pins of the first chip are exposed on the surface of the first plastic package part, so that the pins of the first chip are connected with the surface of the first plastic package part.
Optionally, the step of activating the surface of the first molding member by laser to form the conductive layer includes:
manufacturing a hollowed-out circuit pattern on a mask, and paving the mask on the surface of the first plastic package part to expose the surface of the first plastic package part at the position of the circuit pattern in the air;
irradiating the surface of the first plastic package by laser to activate the part exposed in the air on the first plastic package to form the conductive layer;
wherein the via hole is located on the circuit pattern or the position of the pin of the first chip corresponds to the circuit pattern.
Optionally, the step of forming the conductive layer by irradiating the surface of the first molding member with laser light to activate the portion of the first molding member exposed to air includes:
and contacting the part exposed in the air on the first plastic package part through laser to release metal ions in the surface modified plastic of the first plastic package part, so that a conductive layer consisting of the metal ions is formed on the surface of the first plastic package part.
Optionally, the step of activating the surface of the first molding member by laser to form the conductive layer includes:
planning a line path of the conductive layer on the surface of the first plastic package part, so that the via hole is located on the line path or the position of the pin of the first chip corresponds to the line path;
and irradiating laser along the line path so as to activate and form a conductive layer on the surface of the first plastic package at a position along the preset line.
Optionally, the step of flip-chip mounting the first chip on the first substrate and electrically connecting the first chip to the first substrate through the communication line is replaced by:
attaching a second chip on the first substrate and electrically connecting the second chip with the first substrate;
and inversely mounting the first chip on the second chip.
Optionally, the step of flip-chip mounting the first chip on the second chip includes:
and adhering an adhesive film to the upper surface of the second chip, and inversely installing the first chip on the adhesive film of the second chip.
Optionally, after the step of forming a circuit layer on the surface of the first molding compound by a chemical plating process, the step of connecting the circuit layer with the conductive layer further includes:
arranging a second substrate on the circuit layer, and electrically connecting the second substrate with the circuit layer;
mounting a passive device on the second substrate;
and performing injection molding on the second substrate to form a second plastic package, and packaging the passive device by using the second plastic package.
In addition, in order to solve the above problems, the present invention further provides an integrated chip, where the integrated chip includes a substrate, a chip, a conductive layer, a circuit layer, and a plastic-sealed component, the chip is disposed on the substrate, the plastic-sealed component covers the chip, the conductive layer is disposed on a side surface of the plastic-sealed component corresponding to a pin of the chip, the pin of the chip is electrically connected to the conductive layer, the circuit layer is disposed on the conductive layer, and the circuit layer is electrically connected to the conductive layer.
According to the technical scheme, the first plastic package part is made of modified plastics, the first chip is packaged on the substrate through the first plastic package part, the surface of the first plastic package part is activated to form the conductive layer, meanwhile, the surface of the first plastic package part is provided with the through hole, and the circuit layer is arranged to be connected with the conductive layer, so that pins (pad) on the first chip can be connected to the circuit layer through the through hole, the first chip can be directly connected to other passive devices through the circuit layer on the surface of the first plastic package part, the use of a transfer board is reduced, the structure is simplified, and the integration level is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic flow chart of a first embodiment of an IC fabrication process according to the present invention;
FIG. 2 is a schematic flow chart of a second embodiment of an IC fabrication process according to the present invention;
FIG. 3 is a flow chart of a third embodiment of an IC fabrication process according to the present invention;
FIG. 4 is a schematic flow chart of a fourth embodiment of an IC fabrication process according to the present invention;
FIG. 5 is a flow chart illustrating a fifth embodiment of an IC fabrication process according to the present invention;
FIG. 6 is a schematic flow chart of a sixth embodiment of an IC fabrication process according to the present invention;
FIG. 7 is a flow chart illustrating a seventh embodiment of an IC manufacturing process according to the present invention;
FIG. 8 is a flowchart illustrating an eighth embodiment of an IC manufacturing process according to the present invention;
FIG. 9 is a flow chart illustrating a ninth embodiment of an IC manufacturing process according to the present invention;
FIG. 10 is a diagram illustrating an integrated chip according to the present invention.
The reference numbers illustrate:
reference numerals Name (R) Reference numerals Name (R)
10 First plastic package part 11 Via hole
20 First chip 21 Pin
30 First substrate 40 Circuit layer
50 Second plastic package 60 Second chip
70 Second substrate
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides an integrated chip manufacturing process, please refer to fig. 1 and 10, fig. 1 is a schematic flow chart of a first embodiment of the integrated chip manufacturing process of the invention, and the integrated chip manufacturing process includes the following steps:
step S10: the first chip 20 is inversely arranged on the first substrate 30 and is electrically connected with the first substrate 30;
step S20: injecting a modified plastic to the first substrate 30 to form a first plastic package 10, and encapsulating the first chip 20 with the first plastic package 10;
step S30: forming a through hole 11 at a position of the first plastic package 10 corresponding to the pin 21 of the first chip 20;
step S40: filling an electric conductor into the via hole 11 to connect the pin 21 of the first chip 20 with the surface of the first molding compound 10;
step S50: activating the surface of the first molding compound 10 by laser to form a conductive layer;
step S60: and forming a circuit layer 40 on the surface of the first plastic package part 10 through a chemical plating process, wherein the circuit layer 40 is connected with the conductive layer.
Firstly, the wafer is thinned to a corresponding thickness by grinding, then the wafer is cut into the first chip 20, and the first chip 20 is flip-chip mounted on the first substrate 30 by processes of bonding, curing, wire bonding, flip-chip mounting, reflow soldering, cleaning and the like, wherein the flip-chip mounting of the first chip 20 means that the pins 21 of the first chip 20 are arranged towards one side away from the first substrate 30, that is, the surface of the first chip 20 is arranged towards the first substrate 30, so that the pins 21 of the first chip 20 can be directly connected to external passive devices, such as capacitors, resistors or other functional devices, through the surface of the first plastic package 10 (that is, the surface of the first plastic package 10 opposite to the pins 21 of the first chip 20, and the surfaces of the following first plastic package 10 all refer to the surface opposite to the pins 21 of the first chip 20), so as to achieve the purpose of reducing the packaging volume. In addition, the first chip 20 may also be electrically connected to the first substrate 30 by means of a solder communication line, so as to implement data transmission, interaction, and the like. Then, the modified plastic is injection-molded on the first substrate 30 through an injection-molding process to form the first mold package 10, where the first mold package 10 is used to package the first chip 20 on the first substrate 30. Wherein, the modified plastic refers to plastic which is added with metal ions so as to change partial properties of the plastic, such as rigidity, hardness and the like. The first plastic package 10 includes a top wall and a plurality of side walls, the top wall is disposed opposite to the first substrate 30, one end of the side wall is connected to the first substrate 30, and the other end of the side wall is connected to the top wall, wherein the volume of the first plastic package 10 can be adjusted according to an application scenario, for example, when the volume of the first plastic package 10 is large, the side walls can be disposed along the edge of the first substrate 30, that is, the entire substrate is packaged by the first plastic package 10; when the volume of the first molding compound 10 is small, the side walls may be disposed along the edge of the first chip 20, so that only the first chip 20 is encapsulated.
Then, the through hole 11 is opened on the surface of the first plastic package 10, the pin 21 of the first chip 20 overlaps with the projection position of the through hole 11 on the first substrate 30, and the pin 21 of the first chip 20 is in contact with the outside air through the through hole 11. And then, filling the conductor into the via hole 11, so that one end of the conductor is connected with the pin 21 of the first chip 20, and the other end fills the via hole 11 to be flush with the surface of the first plastic package 10. The electric conductor is a conductive material which can adopt silver paste or tin paste and the like, and after the electric conductor is baked, the electric conductivity is realized through solidification, so that the pin 21 of the first chip 20 can be connected onto the electric conductor through the via hole 11.
Then, the surface of the first plastic package 10 is irradiated with laser, metal ions in the modified plastic are activated under the action of the laser, and the activated metal ions are gathered on the surface of the first plastic package 10, so that the position irradiated with the laser has a conductive performance, the surface of the first plastic package 10 can form the conductive layer at the position irradiated with the laser, and the conductive layer is filled to be flush with the surface of the first plastic package 10, so that the pins 21 of the first chip 20 can be connected to the conductive layer through the conductive body.
Finally, the circuit layer 40 is fabricated on the conductive layer by a chemical plating process, and metal ions, such as gold, copper, nickel, etc., are deposited on the activated conductive layer to form the circuit layer 40, in this embodiment, taking copper ions as an example, copper ions are deposited on the conductive layer to form copper wires or pads, etc., that is, the circuit layer 40. The circuit layer 40 is electrically connected with the electrical conductor, under the combined action of the electrical conductor, the conductive layer and the circuit layer 40, the pin 21 of the first chip 20 is connected with the circuit layer 40, and when other passive devices, such as a capacitor, a resistor or other functional elements, are connected to the circuit layer 40, the circuit layer can be directly electrically connected with the first chip 20 to perform information interaction, so that an adapter plate is not needed, the cost is saved, the packaging integration level of the first chip 20 can be improved, the packaging space is reduced, the miniaturization is realized, and the requirement for higher density is met. It should be noted that the integrated chip manufacturing process of the present invention can be applied to stacked integrated packages of different types of chips.
According to the technical scheme, the first plastic package part 10 is made of modified plastics, the first chip 20 is packaged on the substrate by the first plastic package part 10, the surface of the first plastic package part 10 is activated to form the conductive layer, meanwhile, the surface of the first plastic package part 10 is provided with the through hole 11, and the circuit layer 40 is arranged to be connected with the conductive layer, so that the pin 21 on the first chip 20 can be connected to the circuit layer 40 through the through hole 11, and further the first chip 20 can be directly connected to other passive devices through the circuit layer 40 on the surface of the first plastic package part 10, so that the use of a transfer board is reduced, the structure is simplified, and the integration level is improved.
Further, referring to fig. 2, fig. 2 is a schematic flow chart of a second embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, wherein the step S30 includes:
step S31: acquiring a first projection position of the first chip 20 on the first substrate 30 according to the position of the first chip 20 on the first substrate 30;
step S32: acquiring a preset position of the pin 21 of the first chip 20 on the first chip 20, and acquiring a second projection position of the pin 21 of the first chip 20 on the first substrate 30 according to the first projection position and the preset position;
step S33: and performing laser on the first plastic package part 10 at a position corresponding to the second projection position to form the through hole 11, so that the pin 21 of the chip is in contact with air through the through hole 11.
In this embodiment, when the distance between the surface of the first molding compound 10 and the pins 21 of the first chip 20 is large, for example, when the distance is greater than 40 micrometers, it means that the distance between the surface of the first molding compound 10 and the pins 21 of the first chip 20 is large. In order to ensure that the via 11 can accurately correspond to the pin 21 on the first chip 20, when the first chip 20 is mounted, the first projection position of the first chip 20 on the first substrate 30 is recorded; then, a preset position of the pin 21 of the first chip 20 on the first chip 20 is obtained, where the preset position may be obtained by measuring the first chip 20, however, in practical applications, because the positions of the pin 21 of different first chips 20 are different, before the first chip 20 is mounted, chips with different sizes and dimensions need to be measured to obtain the preset position, so as to obtain a second projection position of the pin 21 of the first chip 20 projected on the first substrate 30 according to the first projection position and the preset position, that is, the first projection position and the preset position are overlapped to obtain the second projection position. In this embodiment, after the injection molding is completed, the laser gun is controlled to move to the surface of the first plastic package 10, wherein the position of the laser gun projected on the first substrate 30 is overlapped with the second projection position, and the laser gun is controlled to perform laser engraving to form the via hole 11 in a direction perpendicular to the first substrate 30, so that the projection position of the via hole 11 on the first substrate 30 is ensured to be overlapped with the second projection position, and the situation that the pin 21 of the first chip 20 cannot be normally connected to the conductive layer or the circuit layer 40 due to the fact that the via hole 11 cannot be aligned with the pin 21 of the first chip 20 is avoided, thereby improving the reliability and stability of the integrated chip manufacturing process of the present invention.
Further, referring to fig. 3, fig. 3 is a flowchart illustrating a third embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, in which step S30 is replaced with:
step S70: the surfaces of the first molding compound 10 corresponding to the pins 21 of the first chip 20 are polished until the pins 21 of the first chip 20 are exposed on the surface of the first molding compound 10, so that the pins 21 of the first chip 20 are connected with the surface of the first molding compound 10.
As an alternative, in this embodiment, when the distance between the surface of the first plastic package 10 and the pins 21 of the first chip 20 is smaller, for example, when the distance is less than or equal to 40 micrometers, it means that the distance between the surface of the first plastic package 10 and the pins 21 of the first chip 20 is smaller, so that the distance between the surface of the first plastic package 10 and the pins 21 of the first chip 20 can be reduced by directly polishing the surface of the first plastic package 10 until the pins 21 of the first chip 20 are exposed on the surface of the first plastic package 10, thereby ensuring that the pins 21 of the first chip 20 can be stably connected with the conductive layer, so that the pins 21 of the first chip 20 do not need to be positioned, and the step of laser engraving the first plastic package 10 is omitted, the production efficiency is improved, and the manufacturing cost of the integrated chip manufacturing process can be saved.
Further, referring to fig. 4, fig. 4 is a schematic flow chart of a fourth embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, and step S50 includes:
step S51: manufacturing a hollowed-out circuit pattern on a mask, and paving the mask on the surface of the first plastic package 10 to expose the surface of the first plastic package 10 at the position of the circuit pattern in the air;
step S52: irradiating the surface of the first molding compound 10 by laser to activate the portion of the first molding compound 10 exposed to the air to form the conductive layer;
wherein the via hole 11 is located on the circuit pattern or the position of the pin 21 of the first chip 20 corresponds to the circuit pattern.
In practical applications, the conductive layer has different lines in order to make the fabricated integrated chip applicable to various usage scenarios. Therefore, in order to improve the wide adaptability of the integrated chip manufacturing process of the present invention, a Mask (Mask) is disposed on the surface of the first plastic package 10, specifically, a hollowed-out circuit pattern is firstly manufactured on the Mask, that is, the Mask is hollowed out at the position of the circuit pattern, when the Mask is laid on the surface of the first plastic package 10, only the portion of the surface of the first plastic package 10 that needs to be activated by laser irradiation is exposed, that is, the portion of the Mask that is located on the circuit pattern, and the portion that does not need to be activated by laser irradiation is blocked by the Mask, so as to avoid being activated by laser irradiation. Under the irradiation of the laser, the exposed portion on the surface of the first molding compound 10 is activated to form the conductive layer, i.e., a conductive seed layer, so as to fabricate the circuit layer 40 on the conductive layer. In this embodiment, the conductive layers of different circuits can be manufactured on the first plastic package 10 only by adjusting the layout of the circuit pattern, so as to improve the wide adaptability of the integrated chip manufacturing process of the present invention. It is understood that in the present embodiment, the via 11 is located on the circuit pattern or the position of the pin 21 of the first chip 20 corresponds to the circuit pattern, so that the pin 21 of the first chip 20 can be electrically connected to the conductive layer.
Further, referring to fig. 5, fig. 5 is a flowchart illustrating a fifth embodiment of the integrated chip manufacturing process according to the present invention based on the fourth embodiment, wherein step S52 includes:
step S521: the laser is contacted with the portion of the first plastic package 10 exposed to the air to release the metal ions in the surface modified plastic of the first plastic package 10, so that a conductive layer composed of the metal ions is formed on the surface of the first plastic package 10.
The surface of the first plastic package 10 is irradiated with laser, metal ions in the modified plastic are activated under the action of the laser, the metal ions are gathered on the surface of the first plastic package 10 after being activated, so that the position irradiated with the laser has a conductive performance, the surface of the first plastic package 10 can form the conductive layer at the position irradiated with the laser, and the conductive layer is filled to be flush with the surface of the first plastic package 10, so that the pins 21 of the first chip 20 can be connected to the conductive layer through the conductive body.
Further, referring to fig. 6, fig. 6 is a flowchart illustrating a sixth embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, wherein step S50 includes:
step S53: planning a line path of the conductive layer on the surface of the first plastic package 10, so that the via 11 is located on the line path or the position of the pin 21 of the first chip 20 corresponds to the line path;
step S54: and irradiating laser along the line path to activate and form a conductive layer on the surface of the first plastic package 10 at a position along the preset line.
As an alternative, in this embodiment, a circuit path of the conductive layer is planned on the surface of the first plastic package 10 to replace a scheme of making a hollow circuit pattern on the mask, that is, the laser emitted by the laser generator is controlled to move along the circuit path, so that the position of the first plastic package 10 on the circuit path is activated, and metal ions are released to form the conductive layer; and the part which does not need to be activated by laser irradiation is blocked by the mask, so that the part is prevented from being activated by the laser irradiation. In this embodiment, the conductive layers of different circuits can be manufactured on the first plastic package 10 only by adjusting the layout of the circuit paths, so as to improve the wide adaptability of the integrated chip manufacturing process of the present invention. It is understood that in the present embodiment, the via 11 is located on the line path or the position of the pin 21 of the first chip 20 corresponds to the line path, so that the pin 21 of the first chip 20 can be electrically connected to the conductive layer.
Further, referring to fig. 7, fig. 7 is a flowchart illustrating a seventh embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, in which step S10 is replaced with:
step S80: attaching a second chip 60 to the first substrate 30 to be electrically connected to the first substrate 30;
step S90: the first chip 20 is flip-chip mounted on the second chip 60.
In this embodiment, in order to further improve the integration level of the integrated chip manufacturing process of the present invention, the second chip 60 may be mounted on the first substrate 30, that is, the second chip 60 is directly mounted on the second substrate 70, specifically, the wafer is thinned to a corresponding thickness by grinding, and the second chip 60 is mounted on the first substrate 30 by processes of mounting, curing, bonding, flip-chip mounting, reflow soldering, cleaning, and the like; in addition, one end of the communication line may be soldered to the second chip 60, and the other end may be soldered to the first substrate 30, so that the second chip 60 and the first substrate 30 are electrically connected to each other; after that, the first chip 20 is flip-chip mounted on the second chip 60, or one or more layers of chips are continuously mounted on the first chip 20, in this embodiment, a plurality of first chips 20 are stacked together, so as to further improve the integration level of the integrated chip manufacturing process of the present invention.
Further, referring to fig. 8, fig. 8 is a flowchart illustrating an eighth embodiment of the integrated chip manufacturing process according to the present invention based on the seventh embodiment, wherein step S90 includes:
step S91: an adhesive film is attached to the upper surface of the second chip 60, and the first chip 20 is flip-chip mounted on the adhesive film of the second chip 60.
In this embodiment, a layer of adhesive film is firstly attached to the second chip 60, the first chip 20 is flip-chip mounted on the adhesive film, and the first chip 20 is separated from the second chip 60 by the adhesive film, so as to avoid mutual interference between the first chip 20 and the second chip 60, and improve reliability and stability of the integrated chip manufacturing process product of the invention.
Further, referring to fig. 9, fig. 9 is a schematic flow chart of an eighth embodiment of the integrated chip manufacturing process according to the present invention based on the first embodiment, and after step S60, the method further includes the following steps:
step S100: disposing a second substrate 70 on the circuit layer 40, and electrically connecting the second substrate 70 with the circuit layer 40;
step S110: mounting a passive device on the second substrate 70;
step S120: and injecting the second substrate 70 to form a second plastic package 50, and encapsulating the passive device with the second plastic package 50.
Metal ions are deposited on the conductive layer through a electroless plating process to form pads or wirings, etc., on the conductive layer, i.e., the circuit layer 40. In this embodiment, the second substrate 70 is soldered on the pads or wires of the circuit layer 40, and the passive device (such as a capacitor, a resistor, or a functional element) is mounted on the second substrate 70, and the passive device is electrically connected to the first chip 20 through the second substrate 70, the circuit layer 40, and the conductive layer. In this embodiment, the passive device is directly soldered on the side surface of the first plastic package 10 through the second substrate 70, that is, the connection with the first chip 20 can be achieved, so that a package structure of a plurality of passive devices can be integrated in vertical and horizontal directions, and the package volume of the integrated chip manufacturing process of the invention is reduced; finally, the second molding compound 50 is formed on the second substrate 70 by injection molding, and the second molding compound 50 is used for encapsulating the flip chip or the passive device on the second substrate 70, so as to form a complete integrated chip.
In addition, the invention also provides an integrated chip, which comprises a substrate, a chip, a conducting layer, a circuit layer 40 and a plastic package part, wherein the chip is arranged on the substrate, the plastic package part covers the chip, the conducting layer is arranged on the surface of one side of the plastic package part corresponding to the pin 21 of the chip, the pin 21 of the chip is electrically connected with the conducting layer, the circuit layer 40 is arranged on the conducting layer, and the circuit layer 40 is electrically connected with the conducting layer.
Firstly, the wafer is thinned to a corresponding thickness by grinding, then the wafer is cut into the first chip 20, and the first chip 20 is flip-chip mounted on the first substrate 30 by processes of bonding, curing, wire bonding, flip-chip mounting, reflow soldering, cleaning, and the like, wherein the flip-chip mounting of the first chip 20 means that the pins 21 of the first chip 20 are arranged towards a side away from the first substrate 30, that is, the surface of the first chip 20 is arranged towards the first substrate 30, so that the pins 21 of the first chip 20 can be directly connected to external passive devices, such as capacitors, resistors, or other functional devices, through the surface of the first molding compound 10 (that is, the surface of the first molding compound 10 opposite to the pins 21 of the first chip 20, and the surface of the first molding compound 10 below refers to the surface opposite to the pins 21 of the first chip 20), so as to achieve the purpose of reducing the packaging volume. In addition, the first chip 20 may also be electrically connected to the first substrate 30 by means of a solder communication line, so as to implement data transmission, interaction, and the like. Then, the modified plastic is injection-molded on the first substrate 30 through an injection-molding process to form the first mold package 10, where the first mold package 10 is used to package the first chip 20 on the first substrate 30. Wherein, the modified plastic refers to plastic which is added with metal ions so as to obtain partial properties of the surface plastic, such as rigidity, hardness and the like. The first plastic package 10 includes a top wall and a plurality of side walls, the top wall is disposed opposite to the first substrate 30, one end of the side wall is connected to the first substrate 30, and the other end of the side wall is connected to the top wall, wherein the volume of the first plastic package 10 can be adjusted according to an application scenario, for example, when the volume of the first plastic package 10 is large, the side walls can be disposed along the edge of the first substrate 30, that is, the entire substrate is packaged by the first plastic package 10; when the volume of the first molding compound 10 is small, the side walls may be disposed along the edge of the first chip 20, so that only the first chip 20 is encapsulated.
Then, the through hole 11 is opened on the surface of the first plastic package 10, the pin 21 of the first chip 20 overlaps with the projection position of the through hole 11 on the first substrate 30, and the pin 21 of the first chip 20 is in contact with the outside air through the through hole 11. And then, filling the conductor into the via hole 11, so that one end of the conductor is connected with the pin 21 of the first chip 20, and the other end fills the via hole 11 to be flush with the surface of the first plastic package 10. The electric conductor is a conductive material which can adopt silver paste or tin paste and the like, and after the electric conductor is baked, the electric conductivity is realized through solidification, so that the pin 21 of the first chip 20 can be connected onto the electric conductor through the via hole 11.
Then, the surface of the first plastic package 10 is irradiated with laser, metal ions in the modified plastic are activated under the action of the laser, and the activated metal ions are gathered on the surface of the first plastic package 10, so that the position irradiated with the laser has a conductive performance, the surface of the first plastic package 10 can form the conductive layer at the position irradiated with the laser, and the conductive layer is filled to be flush with the surface of the first plastic package 10, so that the pins 21 of the first chip 20 can be connected to the conductive layer through the conductive body.
Finally, the circuit layer 40 is fabricated on the conductive layer by a chemical plating process, and metal ions, such as gold, copper, nickel, etc., are deposited on the activated conductive layer to form the circuit layer 40, in this embodiment, taking copper ions as an example, copper ions are deposited on the conductive layer to form copper wires or pads, etc., that is, the circuit layer 40. The circuit layer 40 is electrically connected with the electrical conductor, under the combined action of the electrical conductor, the conductive layer and the circuit layer 40, the pin 21 of the first chip 20 is connected with the circuit layer 40, and when other passive devices, such as a capacitor, a resistor or other functional elements, are connected to the circuit layer 40, the circuit layer can be directly electrically connected with the first chip 20 to perform information interaction, so that an adapter plate is not needed, the cost is saved, the packaging integration level of the first chip 20 can be improved, the packaging space is reduced, the miniaturization is realized, and the requirement for higher density is met. It should be noted that the integrated chip manufacturing process of the present invention can be applied to stacked integrated packages of different types of chips.
According to the technical scheme, the first plastic package part 10 is made of modified plastics, the first chip 20 is packaged on the substrate by the first plastic package part 10, the surface of the first plastic package part 10 is activated to form the conductive layer, meanwhile, the surface of the first plastic package part 10 is provided with the through hole 11, and the circuit layer 40 is arranged to be connected with the conductive layer, so that the pin 21 on the first chip 20 can be connected to the circuit layer 40 through the through hole 11, and further the first chip 20 can be directly connected to other passive devices through the circuit layer 40 on the surface of the first plastic package part 10, so that the use of a transfer board is reduced, the structure is simplified, and the integration level is improved.
Further, a second substrate 70 is disposed on the surface of the first plastic package 10, the second substrate 70 is electrically connected to the circuit layer 40, and a passive device is disposed on the second substrate 70. The integrated chip further comprises a second molding compound 50, and the second molding compound 50 encapsulates the passive device on the second substrate 70.
Metal ions are deposited on the conductive layer through a electroless plating process to form pads or wirings, etc., on the conductive layer, i.e., the circuit layer 40. In this embodiment, the second substrate 70 is soldered on the pads or wires of the circuit layer 40, and the passive device (such as a capacitor, a resistor, or a functional element) is mounted on the second substrate 70, and the passive device is electrically connected to the first chip 20 through the second substrate 70, the circuit layer 40, and the conductive layer. In this embodiment, the passive device is directly soldered on the side surface of the first plastic package 10 through the second substrate 70, that is, the connection with the first chip 20 can be achieved, so that a package structure of a plurality of passive devices can be integrated in vertical and horizontal directions, and the package volume of the integrated chip manufacturing process of the invention is reduced; finally, the second molding compound 50 is formed on the second substrate 70 by injection molding, and the second molding compound 50 is used for encapsulating the flip chip or the passive device on the second substrate 70, so as to form a complete integrated chip.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (9)

1. An integrated chip manufacturing process, comprising the steps of:
the method comprises the steps that a first chip is inversely arranged on a first substrate and is electrically connected with the first substrate;
injecting modified plastics to the first substrate to form a first plastic package piece, and packaging the first chip by using the first plastic package piece;
forming a through hole at a position of the first plastic package corresponding to the pin of the first chip;
filling an electric conductor into the via hole so as to connect the pin of the first chip with the surface of the first plastic package part;
activating the surface of the first plastic package by laser to form a conductive layer;
forming a circuit layer on the surface of the first plastic package part through a chemical plating process, wherein the circuit layer is connected with the conductive layer;
the modified plastic is a plastic doped with metal ions.
2. The integrated chip manufacturing process according to claim 1, wherein the step of forming a via hole on the first plastic package corresponding to the pin position of the chip comprises:
acquiring a first projection position of the first chip on the first substrate according to the position of the first chip on the first substrate;
acquiring a preset position of a pin of the first chip on the first chip, and acquiring a second projection position of the pin of the first chip on the first substrate according to the first projection position and the preset position;
and performing laser on the first plastic package part at a position corresponding to the second projection position to form the through hole, so that the pin of the chip is in contact with air through the through hole.
3. The integrated chip manufacturing process according to claim 1, wherein a via hole is formed at a position of the first plastic package corresponding to the pin of the first chip; filling an electric conductor into the via hole so as to replace the step of connecting the pin of the first chip with the surface of the first plastic package part with the following steps:
and polishing the surfaces of the first plastic package part corresponding to the pins of the first chip until the pins of the first chip are exposed on the surface of the first plastic package part, so that the pins of the first chip are connected with the surface of the first plastic package part.
4. The integrated chip manufacturing process according to claim 1, wherein the step of activating the surface of the first molding compound by laser to form a conductive layer comprises:
manufacturing a hollowed-out circuit pattern on a mask, and paving the mask on the surface of the first plastic package part to expose the surface of the first plastic package part at the position of the circuit pattern in the air;
irradiating the surface of the first plastic package by laser to activate the part exposed in the air on the first plastic package to form the conductive layer;
wherein the via hole is located on the circuit pattern or the position of the pin of the first chip corresponds to the circuit pattern.
5. The integrated chip manufacturing process according to claim 4, wherein the step of forming the conductive layer by laser irradiation of the surface of the first molding member to activate the portion of the first molding member exposed to air comprises:
and contacting the part exposed in the air on the first plastic package part through laser to release metal ions in the surface modified plastic of the first plastic package part, so that a conductive layer consisting of the metal ions is formed on the surface of the first plastic package part.
6. The integrated chip manufacturing process according to claim 1, wherein the step of activating the surface of the first molding compound by laser to form a conductive layer comprises:
planning a line path of the conductive layer on the surface of the first plastic package part, so that the via hole is located on the line path or the position of the pin of the first chip corresponds to the line path;
and irradiating laser along the line path to activate and form a conductive layer on the surface of the first plastic package at a position along the line path.
7. The integrated chip manufacturing process according to claim 1, wherein the step of flip-chip mounting the first chip on the first substrate and electrically connecting with the first substrate is replaced by:
attaching a second chip on the first substrate and electrically connecting the second chip with the first substrate;
and inversely mounting the first chip on the second chip.
8. The integrated chip fabrication process of claim 7, wherein the step of flip-chip mounting the first chip on the second chip comprises:
and adhering an adhesive film to the upper surface of the second chip, and inversely installing the first chip on the adhesive film of the second chip.
9. The integrated chip manufacturing process according to claim 1, wherein after the step of forming a circuit layer on the surface of the first molding compound by a chemical plating process, the step of connecting the circuit layer to the conductive layer further comprises:
arranging a second substrate on the circuit layer, and electrically connecting the second substrate with the circuit layer;
mounting a passive device on the second substrate;
and performing injection molding on the second substrate to form a second plastic package, and packaging the passive device by using the second plastic package.
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