CN111751685A - Circuit breaker partial discharge fault and arc light short circuit fault monitoring device - Google Patents
Circuit breaker partial discharge fault and arc light short circuit fault monitoring device Download PDFInfo
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- CN111751685A CN111751685A CN202010650902.5A CN202010650902A CN111751685A CN 111751685 A CN111751685 A CN 111751685A CN 202010650902 A CN202010650902 A CN 202010650902A CN 111751685 A CN111751685 A CN 111751685A
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- 238000012806 monitoring device Methods 0.000 title claims abstract description 21
- 238000006243 chemical reaction Methods 0.000 claims abstract description 80
- 239000000835 fiber Substances 0.000 claims abstract description 20
- 239000013307 optical fiber Substances 0.000 claims abstract description 20
- 238000004891 communication Methods 0.000 claims abstract description 15
- 239000003990 capacitor Substances 0.000 claims description 85
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- 238000009421 internal insulation Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1218—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing using optical methods; using charged particle, e.g. electron, beams or X-rays
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- G—PHYSICS
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- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
- G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
- G01D5/32—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light
- G01D5/34—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells
- G01D5/353—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre
- G01D5/35306—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre using an interferometer arrangement
- G01D5/35309—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre using an interferometer arrangement using multiple waves interferometer
- G01D5/35312—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre using an interferometer arrangement using multiple waves interferometer using a Fabry Perot
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Abstract
The invention discloses a monitoring device for a circuit breaker partial discharge fault and an arc short circuit fault, which comprises an adjustable optical fiber F-P filter circuit, a D/A conversion circuit, an amplifying circuit, an FPGA chip, a photoelectric detector, a photoelectric conversion circuit, an A/D conversion circuit, a clock circuit and a USB communication circuit, wherein the adjustable optical fiber F-P filter circuit is connected with the D/A conversion circuit; the D/A conversion circuit, the A/D conversion circuit, the clock circuit and the USB communication circuit are respectively connected with the FPGA chip; the amplifying circuit is respectively connected with the D/A conversion circuit and the adjustable optical fiber F-P filter circuit; the photoelectric conversion circuit is respectively connected with the A/D conversion circuit and the photoelectric detector; the adjustable optical fiber F-P filter circuit is connected with the photoelectric detector. According to the fiber Bragg grating demodulation system based on the FPGA, in the demodulation process, optical signals are mainly collected through a photoelectric detector, are converted into visible wavelength signals through AD conversion, are combined with sawtooth waves, peak values are measured in a clock period, and detection of insulation faults inside a circuit breaker can be achieved according to different environments and power fluctuation of light source wavelengths.
Description
Technical Field
The embodiment of the invention relates to the technical field of optical fiber sensing, in particular to a monitoring device for a partial discharge fault and an arc short circuit fault of a circuit breaker.
Background
Circuit breakers are important devices in power systems, which can pose a significant threat to system operation if a fault occurs and result in significant economic losses. In order to ensure safe operation of the circuit breaker and to improve reliability of operation of the power system, fault monitoring thereof must be enhanced.
A Fiber Grating Sensor (FBG), which belongs to one of Fiber sensors, obtains sensing information by modulating the wavelength of a Fiber Bragg Grating (Bragg) through external physical parameters in a sensing process based on the FBG, and is a wavelength modulation type Fiber Sensor. The fiber grating sensor can realize direct measurement of physical quantities such as temperature, strain and the like. In the present society, the sensor technology mainly based on the fiber grating sensor plays an important role in the aspects of fiber communication and fiber sensing, and the prior art applies the sensor technology to the internal insulation fault partial discharge of the circuit breaker and the online monitoring of arc faults.
At present, in the demodulation process of the fiber grating sensor, instruments with high measurement precision such as a spectrometer and a monochromator are generally used, but the spectrometer is expensive, is not suitable for general users, and is not suitable for large-scale application of a power system.
Disclosure of Invention
The invention provides a monitoring device for a partial discharge fault and an arc short circuit fault of a circuit breaker, which aims to overcome the defects of the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a circuit breaker partial discharge fault and arc short circuit fault monitoring device comprises an adjustable optical fiber F-P filter circuit, a D/A conversion circuit, an amplifying circuit, an FPGA chip, a photoelectric detector, a photoelectric conversion circuit, an A/D conversion circuit, a clock circuit and a USB communication circuit; wherein,
the D/A conversion circuit, the A/D conversion circuit, the clock circuit and the USB communication circuit are respectively connected with the FPGA chip;
the amplifying circuit is respectively connected with the D/A conversion circuit and the adjustable optical fiber F-P filter circuit;
the photoelectric conversion circuit is respectively connected with the A/D conversion circuit and the photoelectric detector;
the adjustable optical fiber F-P filter circuit is connected with the photoelectric detector.
Furthermore, the device for monitoring the partial discharge fault and the arc short circuit fault of the circuit breaker further comprises a programmable read-only memory;
the programmable read-only memory is connected with the FPGA chip.
Furthermore, the device for monitoring the partial discharge fault and the arc short circuit fault of the circuit breaker further comprises a reset switch;
the reset switch is connected with the FPGA chip.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the road divider, the adjustable optical fiber F-P filter circuit comprises a first resistor, a first inductor, a first capacitor and a second capacitor;
the first resistor, the first inductor and the first capacitor are sequentially connected in series and then connected in parallel with the second capacitor.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the circuit divider, the D/A conversion circuit comprises a D/A conversion chip.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the road divider, the amplifying circuit comprises a first operational amplifier, a second operational amplifier and a first triode;
the positive input end of the first operational amplifier is connected with an Iout2 pin of the D/A conversion chip, and the negative input end of the first operational amplifier is connected with an Iout1 pin of the D/A conversion chip;
the positive input end of the first operational amplifier is pulled down to the ground;
the output end of the first operational amplifier is connected with the positive input end of the second operational amplifier through a second resistor, and the Rfb pin of the D/A conversion chip is connected between the output end of the first operational amplifier and the second resistor;
the output end of the second operational amplifier is connected with the base electrode of the first triode through a third resistor and a fourth resistor which are connected in series, and the negative input end of the second operational amplifier is grounded through a fifth resistor;
the collector of the triode is connected with a power supply voltage, and the emitter of the triode is used as a sawtooth wave output to be connected with the adjustable optical fiber F-P filter circuit;
the emitting electrode of the triode is grounded with the adjustable optical fiber F-P filter circuit through a sixth resistor;
the output end of the second operational amplifier is grounded with the third resistor through a third capacitor;
the third resistor and the fourth resistor are grounded through a fourth capacitor;
and the fourth resistor is grounded with the base electrode of the triode through a fifth capacitor, and is grounded through a seventh resistor.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the circuit breaker, the photoelectric conversion circuit comprises a first integrated operational amplifier chip and a second integrated operational amplifier chip;
the second pin of the first integrated operational amplifier chip is connected with the photoelectric detector and then is connected to the third pin of the first integrated operational amplifier chip;
a sixth pin of the first integrated operational amplifier chip is connected with a third pin of the second integrated operational amplifier chip;
the seventh pin of the first integrated operational amplifier chip and the seventh pin of the second integrated operational amplifier chip are both connected with a positive power supply and are grounded through a seventh capacitor and an eighth capacitor which are connected in parallel;
the fourth pin of the first integrated operational amplifier chip and the fourth pin of the second integrated operational amplifier chip are both connected with a negative power supply and are grounded through a ninth capacitor and a tenth capacitor which are connected in parallel;
the second pin of the first integrated operational amplifier chip is connected with the sixth pin of the first integrated operational amplifier chip through an eighth resistor and a sixth capacitor which are connected in parallel;
a sixth pin of the second integrated operational amplifier chip is used as a voltage output end;
a second pin of the second integrated operational amplifier chip is grounded through a ninth resistor;
and the sixth pin of the second integrated operational amplifier chip is connected between the second pin of the second integrated operational amplifier chip and the ninth resistor through a tenth resistor and an eleventh capacitor which are connected in parallel.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the road divider, the A/D conversion circuit comprises an AD chip;
the CLK pin of the AD chip is connected with an external clock through a twelfth capacitor and is connected with a power supply voltage through an eleventh resistor;
the DRVDD pin of the AD chip is connected with the power supply voltage;
the VINA pin of the AD chip is connected with one end of the SMA interface through a thirteenth capacitor and a twelfth resistor which are connected in series; a thirteenth resistor is connected in parallel with two ends of the twelfth resistor;
the VINAB pin of the AD chip is connected with the VINA pin of the AD chip through a fourteenth resistor;
the SENSE pin of the AD chip is connected with the AVSS pin of the AD chip and then grounded;
the other end of the SMA interface is grounded;
and a MODE pin, a CAPT pin, a CAPB pin and a VREF pin of the AD chip are grounded through a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor and a seventeenth capacitor respectively.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the circuit divider, the clock circuit comprises a crystal oscillator, an eighteenth capacitor and a nineteenth capacitor;
the first end of the eighteenth capacitor is connected with the first end of the crystal oscillator;
the first end of the nineteenth capacitor is connected with the second end of the crystal oscillator;
and the second end of the eighteenth capacitor and the second end of the nineteenth capacitor are grounded.
Further, in the device for monitoring the partial discharge fault and the arc short circuit fault of the road junction box, the USB communication circuit comprises a USB interface chip;
pins D0-D7, pins WR, pins RD, pins A0 and pins INT of the USB interface chip are all connected with the FPGA chip.
According to the monitoring device for the partial discharge fault and the arc short-circuit fault of the circuit breaker, provided by the embodiment of the invention, based on the characteristics of the fiber bragg grating, the fiber bragg grating demodulation system based on the FPGA is used, in the demodulation process, optical signals are mainly collected by the photoelectric detector, are converted into visible wavelength signals through AD conversion, and are combined with sawtooth waves, the peak value is measured in a clock period, and the detection on the internal insulation fault of the circuit breaker can be realized according to different environments and the power fluctuation of the light source wavelength.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic functional block diagram of a circuit breaker partial discharge fault and arc short circuit fault monitoring device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the demodulation principle provided by the embodiment of the present invention;
FIG. 3 is a schematic diagram of a tunable fiber F-P filter circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a D/A conversion circuit and an amplifying circuit provided by an embodiment of the present invention;
fig. 5 is a schematic diagram of a photoelectric conversion circuit provided in an embodiment of the present invention;
FIG. 6 is a schematic diagram of an A/D conversion circuit provided by an embodiment of the invention;
FIG. 7 is a fitting graph of AD acquisition data provided by an embodiment of the invention;
FIG. 8 is a schematic diagram of a clock circuit provided by an embodiment of the invention;
FIG. 9 is a schematic diagram of a USB communication circuit according to an embodiment of the present invention;
FIG. 10 is an overall flow chart of the solution provided by the embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating the operation of a D/A conversion chip according to an embodiment of the present invention;
fig. 12 is a logic block diagram and a pin arrangement diagram of a D/a conversion chip according to an embodiment of the present invention;
fig. 13 is a functional diagram of each pin of the D/a conversion chip according to the embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present.
Furthermore, the terms "long", "short", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present invention, but do not indicate or imply that the referred devices or elements must have the specific orientations, be configured to operate in the specific orientations, and thus are not to be construed as limitations of the present invention.
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Example one
Referring to fig. 1, an embodiment of the present invention provides a device for monitoring a circuit breaker partial discharge fault and an arc short circuit fault, including an adjustable fiber F-P filter circuit, a D/a conversion circuit, an amplifying circuit, an FPGA chip, a photodetector, a photoelectric conversion circuit, an a/D conversion circuit, a clock circuit, and a USB communication circuit; wherein,
the D/A conversion circuit, the A/D conversion circuit, the clock circuit and the USB communication circuit are respectively connected with the FPGA chip;
the amplifying circuit is respectively connected with the D/A conversion circuit and the adjustable optical fiber F-P filter circuit;
the photoelectric conversion circuit is respectively connected with the A/D conversion circuit and the photoelectric detector;
the adjustable optical fiber F-P filter circuit is connected with the photoelectric detector;
preferably, the monitoring device for the partial discharge fault and the arc short circuit fault of the circuit breaker further comprises a programmable read-only memory;
the programmable read-only memory is connected with the FPGA chip.
Preferably, the monitoring device for the partial discharge fault and the arc short circuit fault of the circuit breaker further comprises a reset switch;
the reset switch is connected with the FPGA chip.
It should be noted that the fabry-perot cavity (F-P cavity) is the core of the demodulation hardware design. In the Slave FIFO module, the fiber grating completes the transceiving of the optical signal, and the frequency of the optical signal is generally around 20MP2013857 s.
The light signal which can not be detected can be converted into a detectable electric signal through the photoelectric detector, the detectable electric signal is sent to the A/D conversion circuit for collection, the collected signal is transmitted to the FPGA chip, and the collected signal is combined with the clock period pulse and the sawtooth waveform. The detected signal can be used to indicate the magnitude of the optical signal. The hardware schematic diagram of the signal acquisition device is shown in fig. 2.
From hardware probing, it can be seen that the voltage of the tunable fiber F-P filter circuit can be represented by the reflected wavelength in the FBG. The method has the unique characteristics that: the demodulation equipment is low in price and small in size, the electric signals can be directly detected, the tuning range is wide, the practicability is good, and the price is low.
The broadband light source is selected, the influence of the bandwidth, the working wavelength, the stability and the power of the broadband light source on the broadband light source is the most important consideration, so that the selection of a proper light source for detection is the primary task, the system cost can be reduced, and the more stable operation of the system can be increased. In this system, the light source used to be detected may be a broadband light source that amplifies the spontaneous emission. Since the wavelength of the light source includes C, L sections, the detectable range is 1520-1605 nm. The structure of the refrigerator is designed by adopting a secondary refrigeration technology with high precision. Thereby assisting the system.
Preferably, as shown in fig. 3, the tunable fiber F-P filter circuit includes a first resistor R1, a first inductor L1, a first capacitor C1, and a second capacitor C2;
the first resistor R1, the first inductor L1 and the first capacitor C1 are sequentially connected in series and then are connected in parallel with the second capacitor C2.
It should be noted that, in this embodiment, a driving circuit is designed to control the tunable fiber F-P filter circuit, and specifically, the driving circuit includes a D/a conversion circuit and an amplification circuit. In the demodulation system, the output voltage of the driving circuit gives a digital signal through an FPGA chip, the digital signal is added to a D/A conversion circuit and then output by the D/A conversion circuit, the output signal generates a sawtooth wave through the amplification and filtering links of an amplifying circuit, and the sawtooth wave is used for controlling the cavity change of an F-P cavity. The core of designing a driving circuit is to grasp the structure and characteristics of a filter. The advantages of such a driving circuit are different from those of general PZT.
In general, a filter requires driving of a large load, and the driving of the load can be increased by the following methods: the frequency of the control signal is reduced or an isolation resistor may be added to the load. The resistance value is selected according to the application scene, and the range is 5-100 ohms; in addition, the system gain is increased, which can be used for multiplying the driving capacity of the circuit; in another method for increasing the load, a transistor may be added to the output terminal, and the transistor is used to increase the driving capability of the circuit. The method used in this example is the latter method.
Preferably, as shown in fig. 4, the D/a conversion circuit includes a D/a conversion chip U1.
The amplifying circuit comprises a first operational amplifier OP1, a second operational amplifier OP2 and a first triode Q1;
the positive input end of the first operational amplifier OP1 is connected with an Iout2 pin of the D/A conversion chip U1, and the negative input end of the first operational amplifier OP1 is connected with an Iout1 pin of the D/A conversion chip U1;
a positive input terminal of the first operational amplifier OP1 is pulled down to ground;
the output end of the first operational amplifier OP1 is connected to the positive input end of the second operational amplifier OP2 through a second resistor R2, and the Rfb pin of the D/a conversion chip U1 is connected between the output end of the first operational amplifier OP1 and the second resistor R2;
the output end of the second operational amplifier OP2 is connected with the base of the first triode Q1 through a third resistor R3 and a fourth resistor R4 which are connected in series, and the negative input end of the second operational amplifier OP2 is grounded through a fifth resistor R5;
the collector of the triode is connected with a power supply voltage, and the emitter of the triode is used as a sawtooth wave output to be connected with the adjustable optical fiber F-P filter circuit;
the emitting electrode of the triode is grounded with the adjustable optical fiber F-P filter circuit through a sixth resistor R6;
the output end of the second operational amplifier OP2 and the third resistor R3 are grounded through a third capacitor C3;
the third resistor R3 and the fourth resistor R4 are grounded through a fourth capacitor C4;
the fourth resistor R4 is grounded with the base of the triode through a fifth capacitor C5 and a seventh resistor R7.
Preferably, as shown in fig. 5, the photoelectric conversion circuit includes a first integrated operational amplifier chip U2 and a second integrated operational amplifier chip U3;
the second pin of the first integrated operational amplifier chip U2 is connected with the photodetector and then is connected to the third pin of the first integrated operational amplifier chip U2;
a sixth pin of the first integrated operational amplifier chip U2 is connected to a third pin of the second integrated operational amplifier chip U3;
the seventh pin of the first integrated operational amplifier chip U2 and the seventh pin of the second integrated operational amplifier chip U3 are both connected with a positive power supply and are grounded through a seventh capacitor C7 and an eighth capacitor C8 which are connected in parallel;
the fourth pin of the first integrated operational amplifier chip U2 and the fourth pin of the second integrated operational amplifier chip U3 are both connected with a negative power supply and are grounded through a ninth capacitor C9 and a tenth capacitor C10 which are connected in parallel;
the second pin of the first integrated operational amplifier chip U2 is connected with the sixth pin of the first integrated operational amplifier chip U2 through an eighth resistor R8 and a sixth capacitor C6 which are connected in parallel;
a sixth pin of the second integrated operational amplifier chip U3 is used as a voltage output end;
a second pin of the second integrated operational amplifier chip U3 is grounded through a ninth resistor R9;
the sixth pin of the second integrated operational amplifier chip U3 is connected between the second pin of the second integrated operational amplifier chip U3 and the ninth resistor R9 through a tenth resistor R10 and an eleventh capacitor C11 connected in parallel.
The seventh capacitor C7 and the ninth capacitor C9 are polar capacitors.
It should be noted that there are some interference factors when designing the circuit, so it is necessary to specifically grasp the principles of the noise source and the optical detection, and this is to avoid that the unnecessary noise has a certain influence on the demodulation and affects the performance of the whole system. In general, light reflected by an optical signal grating is very weak, and a photoelectric conversion circuit must be able to detect the Na level of a photocurrent. The main device of the photoelectric conversion circuit is an integrated operational amplifier chip. The high-precision photoelectric detection circuit is mainly used for operational amplifier bias current, noise density, offset voltage, gain, input impedance and conversion speed.
The resistance of the precision metal film resistor is far smaller than that of the high carbon film, but the thermal noise is smaller. However, due to the feedback resistance, noise is also easily introduced in practical applications. It is necessary to connect a small capacitor in parallel with the feedback resistor so that the capacitor does not become large. When the capacitor is short-circuited, the photoelectric conversion circuit is also under-designed, which may cause a delay to be large, causing an unnecessary influence on the demodulation system. The parallel capacitor is selected to be 1-100 pf.
When the circuit is designed, the photodetector (photodiode) plays an excessive role, so that a protection measure needs to be added to protect it. For PCB circuits, the photodiode should be as close as possible to the input of the operational amplifier. It is necessary to add a guard ring to the input of the previous operational amplifier and shield the entire photodetector circuitry with a metal housing.
Preferably, as shown in fig. 6, the a/D conversion circuit includes an AD chip U4;
the CLK pin of the AD chip U4 is connected with an external clock through a twelfth capacitor C12 and is connected with a power supply voltage (D +3.3V) through an eleventh resistor R11;
the DRVDD pin of the AD chip U4 is connected with the power supply voltage (D + 3.3V);
the VINA pin of the AD chip U4 is connected with one end of the SMA interface through a thirteenth capacitor C13 and a twelfth resistor R12 which are connected in series; a thirteenth resistor R13 is connected in parallel with two ends of the twelfth resistor R12;
the VINAB pin of the AD chip U4 is connected with the VINA pin of the AD chip U4 through a fourteenth resistor R14;
the SENSE pin of the AD chip U4 and the AVSS pin of the AD chip U4 are connected and then grounded;
the other end of the SMA interface is grounded;
the MODE pin, the CAPT pin, the CAPB pin and the VREF pin of the AD chip U4 are grounded through a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16 and a seventeenth capacitor C17 respectively.
The SMA interface receives a voltage signal of-5V and inputs the voltage signal into the AD chip U4.
It should be noted that the system uses a sensor to convert the analog signal from the photodetector to a digital signal, and a precision converter is provided in the AD, which has a multiplexer and channels into which the analog signal is input. The hardware control can be used as a control center of an analog signal channel. Each analog signal is converted and then registered in a register.
In this design, the 2V internal reference voltage of the AD chip U4 is used. This has the advantage of a simple circuit configuration. The maximum input analog voltage is 2V. The sampling clock of the AD chip U4 is provided by a custom phase locked bad PLL. The sampling frequency is typically 20M, and in photoelectric conversion, there is an output terminal, which functions to interrupt the input signal. Fig. 7 shows a data simulation diagram of the AD-converted optical signal. The temperature and humidity inside the circuit breaker can be detected according to different waveforms.
Preferably, as shown in fig. 8, the clock circuit includes a crystal oscillator Y1, an eighteenth capacitor C18, and a nineteenth capacitor C19;
a first end of the eighteenth capacitor C18 is connected with a first end of the crystal oscillator Y1;
a first terminal of the nineteenth capacitor C19 is connected with a second terminal of the crystal oscillator Y1;
the second end of the eighteenth capacitor C18 and the second end of the nineteenth capacitor C19 are grounded.
The eighteenth capacitor C18 and the nineteenth capacitor C19 are polar capacitors.
It should be noted that, an oscillating circuit is connected outside the system, and this circuit needs to operate at a low frequency, and its function is to increase the compatibility of the system. When the circuit is designed, an external clock is selected, and the internal oscillator can achieve the effect of the external clock. A 20MHz crystal oscillator is generally chosen for the relevant design. The crystal oscillator and system load capacitance are used to clock the system at 100MHz with an internal 5 times frequency.
Preferably, as shown in fig. 9, the USB communication circuit includes a USB interface chip U5;
the pins D0-D7, WR, RD, A0 and INT of the USB interface chip U5 are all connected with the FPGA chip.
It should be noted that the USB interface chip U5 is generally selected from the CH376, because such a chip is very practical. The local controller and the communication between the computer and the CH376 are two forms of its communication.
The idea of the design of this embodiment is to generate a count block from 0 to 255, generating a sawtooth wave mainly by using an FPGA and adding the output to the D/a conversion chip U1. The flow chart is as shown in fig. 10.
The D/a conversion chip U1 is a digital-to-analog converter. The technology used is CMOS. Fig. 11 is a schematic diagram showing the specific operation of the D/a conversion chip U1. The structure of the D/A conversion chip U1 is easy to understand and comprises an inverse T-type R-2R resistor network, an analog switch, an operational amplifier and a reference voltage. The output analog quantity of the sawtooth wave can be represented as V0, and the expression can be represented as:
as can be seen from the above formula, the output analog quantity is proportional to the input digital quantity, i.e. conversion from digital quantity to analog quantity is realized. The logic block diagram and pin arrangement of the D/A conversion chip U1 are shown in FIG. 12, and the functions of the pins of the D/A conversion chip U1 are shown in FIG. 13. The idea of this embodiment is to use the FPGA to generate 0-255 counting modules and generate a sawtooth wave on the D/A conversion chip U1.
According to the monitoring device for the partial discharge fault and the arc short-circuit fault of the circuit breaker, provided by the embodiment of the invention, based on the characteristics of the fiber bragg grating, the fiber bragg grating demodulation system based on the FPGA is used, in the demodulation process, optical signals are mainly collected by the photoelectric detector, are converted into visible wavelength signals through AD conversion, and are combined with sawtooth waves, the peak value is measured in a clock period, and the detection on the internal insulation fault of the circuit breaker can be realized according to different environments and the power fluctuation of the light source wavelength.
The foregoing description of the embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where applicable, are interchangeable and can be used in a selected embodiment, even if not specifically shown or described. The same elements or features may also vary in many respects. Such variations are not to be regarded as a departure from the disclosure, and all such modifications are intended to be included within the scope of the disclosure.
Example embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those skilled in the art. Numerous details are set forth, such as examples of specific parts, devices, and methods, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details need not be employed, that example embodiments may be embodied in many different forms and that neither should be construed to limit the scope of the disclosure. In certain example embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises" and "comprising" are intended to be inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed and illustrated, unless explicitly indicated as an order of performance. It should also be understood that additional or alternative steps may be employed.
When an element or layer is referred to as being "on" … … "," engaged with "… …", "connected to" or "coupled to" another element or layer, it can be directly on, engaged with, connected to or coupled to the other element or layer, or intervening elements or layers may also be present. In contrast, when an element or layer is referred to as being "directly on … …," "directly engaged with … …," "directly connected to" or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship of elements should be interpreted in a similar manner (e.g., "between … …" and "directly between … …", "adjacent" and "directly adjacent", etc.). As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region or section from another element, component, region or section. Unless clearly indicated by the context, use of terms such as the terms "first," "second," and other numerical values herein does not imply a sequence or order. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
Spatially relative terms, such as "inner," "outer," "below," "… …," "lower," "above," "upper," and the like, may be used herein for ease of description to describe a relationship between one element or feature and one or more other elements or features as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below … …" can encompass both an orientation of facing upward and downward. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted.
Claims (10)
1. A circuit breaker partial discharge fault and arc short circuit fault monitoring device is characterized by comprising an adjustable optical fiber F-P filter circuit, a D/A conversion circuit, an amplifying circuit, an FPGA chip, a photoelectric detector, a photoelectric conversion circuit, an A/D conversion circuit, a clock circuit and a USB communication circuit; wherein,
the D/A conversion circuit, the A/D conversion circuit, the clock circuit and the USB communication circuit are respectively connected with the FPGA chip;
the amplifying circuit is respectively connected with the D/A conversion circuit and the adjustable optical fiber F-P filter circuit;
the photoelectric conversion circuit is respectively connected with the A/D conversion circuit and the photoelectric detector;
the adjustable optical fiber F-P filter circuit is connected with the photoelectric detector.
2. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, further comprising a programmable read only memory;
the programmable read-only memory is connected with the FPGA chip.
3. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, further comprising a reset switch;
the reset switch is connected with the FPGA chip.
4. The circuit breaker partial discharge fault and arc short fault monitoring device of claim 1, wherein the tunable fiber F-P filter circuit comprises a first resistor, a first inductor, a first capacitor, and a second capacitor;
the first resistor, the first inductor and the first capacitor are sequentially connected in series and then connected in parallel with the second capacitor.
5. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, wherein the D/a conversion circuit comprises a D/a conversion chip.
6. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 5, wherein the amplifying circuit comprises a first operational amplifier, a second operational amplifier and a first triode;
the positive input end of the first operational amplifier is connected with an Iout2 pin of the D/A conversion chip, and the negative input end of the first operational amplifier is connected with an Iout1 pin of the D/A conversion chip;
the positive input end of the first operational amplifier is pulled down to the ground;
the output end of the first operational amplifier is connected with the positive input end of the second operational amplifier through a second resistor, and the Rfb pin of the D/A conversion chip is connected between the output end of the first operational amplifier and the second resistor;
the output end of the second operational amplifier is connected with the base electrode of the first triode through a third resistor and a fourth resistor which are connected in series, and the negative input end of the second operational amplifier is grounded through a fifth resistor;
the collector of the triode is connected with a power supply voltage, and the emitter of the triode is used as a sawtooth wave output to be connected with the adjustable optical fiber F-P filter circuit;
the emitting electrode of the triode is grounded with the adjustable optical fiber F-P filter circuit through a sixth resistor;
the output end of the second operational amplifier is grounded with the third resistor through a third capacitor;
the third resistor and the fourth resistor are grounded through a fourth capacitor;
and the fourth resistor is grounded with the base electrode of the triode through a fifth capacitor, and is grounded through a seventh resistor.
7. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, wherein the photoelectric conversion circuit comprises a first integrated operational amplifier chip and a second integrated operational amplifier chip;
the second pin of the first integrated operational amplifier chip is connected with the photoelectric detector and then is connected to the third pin of the first integrated operational amplifier chip;
a sixth pin of the first integrated operational amplifier chip is connected with a third pin of the second integrated operational amplifier chip;
the seventh pin of the first integrated operational amplifier chip and the seventh pin of the second integrated operational amplifier chip are both connected with a positive power supply and are grounded through a seventh capacitor and an eighth capacitor which are connected in parallel;
the fourth pin of the first integrated operational amplifier chip and the fourth pin of the second integrated operational amplifier chip are both connected with a negative power supply and are grounded through a ninth capacitor and a tenth capacitor which are connected in parallel;
the second pin of the first integrated operational amplifier chip is connected with the sixth pin of the first integrated operational amplifier chip through an eighth resistor and a sixth capacitor which are connected in parallel;
a sixth pin of the second integrated operational amplifier chip is used as a voltage output end;
a second pin of the second integrated operational amplifier chip is grounded through a ninth resistor;
and the sixth pin of the second integrated operational amplifier chip is connected between the second pin of the second integrated operational amplifier chip and the ninth resistor through a tenth resistor and an eleventh capacitor which are connected in parallel.
8. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, wherein the a/D conversion circuit comprises an AD chip;
the CLK pin of the AD chip is connected with an external clock through a twelfth capacitor and is connected with a power supply voltage through an eleventh resistor;
the DRVDD pin of the AD chip is connected with the power supply voltage;
the VINA pin of the AD chip is connected with one end of the SMA interface through a thirteenth capacitor and a twelfth resistor which are connected in series; a thirteenth resistor is connected in parallel with two ends of the twelfth resistor;
the VINAB pin of the AD chip is connected with the VINA pin of the AD chip through a fourteenth resistor;
the SENSE pin of the AD chip is connected with the AVSS pin of the AD chip and then grounded;
the other end of the SMA interface is grounded;
and a MODE pin, a CAPT pin, a CAPB pin and a VREF pin of the AD chip are grounded through a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor and a seventeenth capacitor respectively.
9. The circuit breaker partial discharge fault and arc short fault monitoring device of claim 1, wherein the clock circuit comprises a crystal oscillator, an eighteenth capacitor and a nineteenth capacitor;
the first end of the eighteenth capacitor is connected with the first end of the crystal oscillator;
the first end of the nineteenth capacitor is connected with the second end of the crystal oscillator;
and the second end of the eighteenth capacitor and the second end of the nineteenth capacitor are grounded.
10. The circuit breaker partial discharge fault and arc short circuit fault monitoring device of claim 1, wherein the USB communication circuit comprises a USB interface chip;
pins D0-D7, pins WR, pins RD, pins A0 and pins INT of the USB interface chip are all connected with the FPGA chip.
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| CN202010650902.5A CN111751685A (en) | 2020-07-08 | 2020-07-08 | Circuit breaker partial discharge fault and arc light short circuit fault monitoring device |
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| CN202010650902.5A CN111751685A (en) | 2020-07-08 | 2020-07-08 | Circuit breaker partial discharge fault and arc light short circuit fault monitoring device |
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Application publication date: 20201009 |