CN111740847A

CN111740847A - High-speed network data transmission system and method based on FPGA

Info

Publication number: CN111740847A
Application number: CN202010853885.5A
Authority: CN
Inventors: 王自伟; 王志奇; 胡啸东; 徐亚东; 朱峰; 李振斌
Original assignee: Changzhou Nanfei Microelectronics Co ltd
Current assignee: Changzhou Nanfei Microelectronics Co ltd
Priority date: 2020-08-24
Filing date: 2020-08-24
Publication date: 2020-10-02
Anticipated expiration: 2040-08-24
Also published as: CN111740847B

Abstract

The invention discloses a high-speed network data transmission system and method based on FPGA, the system of the invention includes an upper computer, a PCIe switch, a network switch and at least two FPGA computing boards installed on the PCIe switch, in the method of the invention, the upper computer sends operation data to a message sending FPGA computing board, the message sending FPGA computing board sends the processed data to a message receiving FPGA computing board according to a connection number, if the computation is not completed, the message receiving FPGA computing board is used as a next message sending FPGA computing board to send the processed data to the next message receiving FPGA computing board until the computation is completed and returns the computation result to the upper computer, the invention realizes the data transmission between the upper computer and the FPGA computing board and the data forwarding between the FPGA computing boards, and realizes the high-speed network data transmission by using the bandwidth of FPGA.

Description

High-speed network data transmission system and method based on FPGA

Technical Field

The invention relates to a computer network technology, in particular to a high-speed network data transmission system and a high-speed network data transmission method based on an FPGA (field programmable gate array).

Background

Along with the rapid development of big data, the data operation scale is rapidly expanded, and great challenges are brought to the existing operation processing equipment. One way to upgrade the computing power of existing devices, and another way is to coordinate operations, which are decomposed into small computing units and then put on different computing devices for processing. Since the computing task is flexible, ASIC (application specific integrated circuit) development is costly and long-term. A lot of time is spent on deploying a lot of accelerator cards of certain neural networks on a large scale, another more efficient neural network is quickly appeared, and the replacement of the accelerator cards of the ASIC again consumes more cost. While FPGAs have excellent performance and flexibility. FPGAs are more energy efficient than CPUs and even GPUs because both CPUs and GPUs belong to von neumann structures, instruction decoding is performed, and memories are shared, whereas FPGAs are essentially instruction-free and memory-sharing-free architectures. Most importantly, the logic function of the FPGA can be updated only by hundreds of milliseconds, hardware does not need to be replaced, and more cost is saved. For communication intensive tasks, the advantages of the FPGA are greater than those of a CPU and a GPU. In terms of throughput, a transceiver on the FPGA can be directly connected with a 40Gbps or even 100Gbps network cable to process data packets with any size at a line speed; the CPU needs to receive the data packet from the network card for processing, and many network cards cannot process 64-byte small data packets at a linear speed. Although high performance can be achieved by plugging multiple network cards, the number of PCIe slots supported by the CPU and the motherboard is often limited, and the network cards and the switches themselves are expensive. In terms of delay, the network card receives the data packet to the CPU, and the CPU sends the data packet to the network card, so that even if a high-performance data packet processing frame such as a DPDK (data plane development kit) is used, the delay is 4-5 microseconds. A more serious problem is that the delay of a general-purpose CPU is not stable enough.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a high-speed network data transmission system and method based on an FPGA (field programmable gate array), which can reduce the intervention of an upper computer on FPGA calculation board cards, realize the direct data transmission between the FPGA calculation board cards, and can transmit the data to the next FPGA calculation board card after the data is loaded into a memory for processing through PCIe (peripheral component interface express), thereby reducing the data transmission delay between the FPGA calculation board cards.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a high-speed network data transmission system based on FPGA is characterized by comprising an upper computer, a PCIe switch, a network switch and at least two FPGA computing board cards arranged on the PCIe switch, wherein the upper computer is connected with each FPGA computing board card through the PCIe switch, the FPGA computing board cards are mutually connected through the network switch, the FPGA computing board cards comprise a network interface module and a core computing module which are mutually connected, the network interface module comprises a medium access control unit, a packet analysis unit, a packet editing unit, a session unit and a cache unit, the network switch, the medium access control unit, the session unit, the cache unit, the core computing module and the upper computer are sequentially and bidirectionally connected, the packet analysis unit is arranged between the output end of the medium access control unit and the input end of the session unit in the data transmission direction from the network switch to the upper computer, the package editing unit is arranged between the input end of the medium access control unit and the output end of the session unit in the data transmission direction from the upper computer to the network switch, wherein:

the medium access control unit is used for converting the received messages or data packets into one another and then transmitting the messages or data packets;

the packet analysis unit is used for extracting descriptor information in the message and checking the validity of the message;

the packet editing unit is used for editing the descriptor information and the load into a legal message;

the session unit is used for initiating a request for establishing connection or canceling connection, completing message response according to a TCP/IP protocol, and acquiring a load requested to be sent by the cache unit and then sending the load; the device is also used for establishing connection or canceling connection according to a TCP/IP protocol aiming at the received message and sending the load carried by the message to a cache unit;

the buffer unit is used for temporarily storing the data of different connections and also used for sending the corresponding data after receiving the request.

Further, the cache unit is connected with the core computing module through an AXI-Stream interface.

Further, the session unit includes a session checker, a session maintainer and a lookup table, the session checker is connected with the session maintainer in two ways through the lookup table, the packet parsing unit is connected with the cache unit through the session checker, and the packet editing unit is connected with the cache unit through the session maintainer, where:

the session checker is used for acquiring message header information and load, completing connection establishment or connection cancellation or data message reception according to a TCP/IP protocol, and sending the acquired load to the cache unit;

the lookup table is used for recording the connection number and the corresponding message header information;

the session maintainer is used for executing the initiation of establishing a connection request or canceling the connection request according to the configuration of the upper computer, executing and acquiring the data load in the cache unit and sending the data load, and is also used for completing message response according to a TCP/IP protocol.

The invention also provides a high-speed network data transmission method based on the FPGA, which is applied to the high-speed network data transmission system based on the FPGA and comprises the following steps:

step 1), each FPGA computing board card is respectively electrified to be ready;

step 2), restarting the upper computer and identifying each FPGA computing board card;

step 3) the upper computer respectively configures network interface parameters of each FPGA computing board card;

step 4), establishing connection between every two FPGA computing board cards to generate connection numbers, and respectively sending the connection numbers of each pair of FPGA computing board cards to an upper computer;

step 5) the upper computer configures the data transmission direction between the FPGA calculation board cards according to the connection number;

step 6) the upper computer selects a message sending FPGA computing board card from each FPGA computing board card and sends the operation data to a core computing module of the message sending FPGA computing board card;

step 7) in the message sending FPGA computing board card, the core computing module sends the operation result and the corresponding connection number to the cache unit, and the cache unit stores the operation result in a cache space and sends a data sending request to the session unit;

step 8) in the message sending FPGA computing board card, the session unit receives the data sending request and returns a response, then the cache unit sends the operation result and the connection number to the session unit, the session unit searches the message header information in the lookup table of the session unit according to the connection number, and then the operation result is used as a load and the message header information and the load are sent to the packet editing unit;

step 9) in the message sending FPGA computing board card, the packet editing unit edits the message header information and the load into a complete message according to a TCP/IP protocol after receiving the message header information and the load, and sends the message to the medium access control unit;

step 10) in the message sending FPGA computing board card, after the medium access control unit receives the message, caching the message and packaging the message into a data packet according to IEEE802.3 standard, then sending the data packet to a network switch, simultaneously starting a timer, if the data packet response message sent by the message receiving FPGA computing board card is not received after the preset time, returning to the step 8) to start to repeatedly send the data message sent this time until the message receiving FPGA computing board card sends the data message response message;

step 11) the switch forwards the received data packet to a message receiving FPGA computing board card according to the message header information;

step 12) in the message receiving FPGA computing board card, the media access control unit analyzes the received data packet in the data stream conforming to the IEEE802.3 standard into a complete message and sends the message to the packet analysis unit;

step 13) in the message receiving FPGA computing board card, after the packet analysis unit receives the message, firstly, the message is subjected to validity check, and then message header information and load are extracted and sent to a session unit;

step 14) in the message receiving FPGA computing board card, after receiving message header information, the session unit judges whether the message is an error message or not and whether the message is a message sent to the equipment or not according to the message header information, if the message is the error message or not, the message is discarded and returned to the step 12), if the message is not the error message and is the message sent to the equipment, the connection number is searched in a search table of the session unit according to the received message header information, then the connection number and the received load are sent to the cache unit, and meanwhile, a data message response message is sent to the message sending FPGA computing board card;

step 15) in the message receiving FPGA computing board card, the cache unit stores the data load into a cache space after receiving the data load, sends a data sending request to the core computing module, and takes the load out of the cache after receiving the feedback of the core computing module and sends the load and the connection number to the core computing module;

step 16) in the message receiving FPGA computing board card, the core computing module performs operation after receiving the data load to obtain an operation result, whether the operation result needs to be sent to other FPGA computing board cards for further computation is judged according to the received connection number and the configuration of the upper computer, if so, the current message receiving FPGA computing board card is used as a message sending FPGA computing board card and returns to the step 7), and if not, the operation result and the operation completion notice are sent to the upper computer and enter the step 17);

and step 17) after receiving the operation result and the operation completion notification, the upper computer sends a connection cancellation notification to each pair of FPGA computing boards.

Further, the step 4) specifically comprises the following steps:

step 4.1) selecting one FPGA calculation board card as a client side, and selecting another FPGA calculation board card as a server side;

step 4.2) the upper computer generates configuration parameters of the client and the server;

step 4.3) the upper computer sends a connection establishing instruction to the client, the client initiates a connection establishing request to the server, the server responds to the request, the client and the server respectively carry out validity check, if the connection is not established, the client returns a connection success report after establishing new connection and sends a connection number to the upper computer; if the connection is existed, the client returns the report of the connection to the upper computer; if the server does not respond in the specified time, the client returns a report of connection failure to the upper computer;

and 4.4) returning to the step 4.1) until connection is established between every two FPGA computing board cards and a connection number is generated.

Further, step 4.3) includes a step of client internal processing, which specifically includes:

step 4.3.1 a) after acquiring the connection establishing instruction, matching the message header information configured by the upper computer with the lookup table, and returning a connection existing report to the upper computer if a matching result exists; if the matching result does not exist, establishing a new lookup table item, setting a successful establishment identifier, updating other information of the table item, constructing a synchronous message with the type of establishing a connection request, sending the synchronous message to a server side, and starting a retransmission timer;

step 4.3.2 a) waiting for the data sent by the server, and if the data sent by the server is not received after the preset time, sending the synchronous message to the server again; if the retrieval number sent by the server is received within the preset time period, the matching result of the lookup table is obtained according to the retrieval number, then the existing report is returned to the upper computer, and the operation is finished and quit; if the message sent by the server is received within the preset time period, entering the step 4.3.3 a); if the message sent by the server is not received within the preset time period, returning a connection failure report to the upper computer, ending and exiting;

step 4.3.3 a) analyzing the message, judging whether the message type is a connection establishment response message, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step 4.3.2 a), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step 4.3.2 a), if so, updating the lookup table, setting the table state to be valid, updating the queue number, the response number and the window size, starting a keep-alive timer and sending a connection establishment confirmation message to the server;

step 4.3.4 a) waiting for the keep alive timer to reset, if the keep alive timer is reset, generating a connection number corresponding to the connection establishment between the client and the server, returning a report of successful connection and sending the connection number to the upper computer, if a connection establishment response message sent by the server is received, sending a connection establishment confirmation message to the server again and then continuing waiting, and after the number of times of receiving the connection establishment response message sent by the server reaches a first threshold value, returning a report of connection failure to the upper computer, ending and exiting.

Further, step 4.3) includes a step of internal processing of the server, which specifically includes:

step 4.3.1 b) waiting for the message sent by the client, entering step 4.3.2 b) if the message sent by the client is received within the preset time period, if the message sent by the client is not received within the preset time period, returning a connection failure report to the upper computer, ending and exiting;

step 4.3.2 b) analyzing the message, judging whether the message type is a synchronous message of a connection establishment request, if so, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message and returning to the step 4.3.1 b), if so, matching the lookup table according to the message header information, if so, discarding the message and outputting a matching result with the minimum address in the lookup table to a client as a retrieval number, if not, newly establishing a lookup table entry, setting the state of the entry as established, updating the number of queues, the number of answers and the size of a window, and sending a connection establishment response message;

step 4.3.3 b) waiting for the message sent by the client, entering the next step after receiving the message sent by the client, if the message sent by the client is not received within the first preset time, sending a connection establishment response message to the client at intervals of second preset time, and if the sending times reach the first threshold value, still not receiving the message sent by the client, ending and exiting;

step 4.3.4 b) analyzing the message, judging whether the message type is a connection establishment confirmation message, if yes, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message and returning to step 4.3.3 b), if not, matching the lookup table according to the message header information, if not, discarding the message and returning to step 4.3.3 b), if there is a matching result and the number of message queues is the number of table entry answers, the number of message answers is the number of next table entry queue, the role mark of the table entry is the service end, updating the lookup table, setting the state of the table entry to be valid, and resetting the keep-alive timer.

Further, step 4.3.4 b) is preceded by a step of starting a duration timer, specifically comprising: analyzing the message, if the window size of the message is 0, starting a continuous timer, wherein the time initial value of the continuous timer is the same as that of the retransmission timer, the time maximum value of the continuous timer is smaller than a preset second threshold value, if the message sent by the client is not received within the time of the continuous timer, sending a connection establishment response message to the client, doubling the time value of the continuous timer and resetting until the message sent by the client is received within the time of the continuous timer and the window size of the message is larger than 0.

Further, step 17) is followed by a step of revoking the connection by the client, which specifically includes the following steps:

A1) receiving a connection revocation notification issued by the upper computer, matching a connection number in the connection revocation notification with the lookup table, and returning a revocation failure result to the upper computer if no matching result exists; if the matching result exists, setting the connection state of the lookup table to be a semi-closed state, updating other information of the table entry, constructing an end message with the type of canceling the connection request, sending the end message to a corresponding server side, and starting a retransmission timer;

A2) waiting for the message sent by the server, if the message sent by the server is not received within the preset time, sending the finished message to the server again, and entering the next step after receiving the message;

A3) analyzing the message type, judging whether the message is a cancel connection response message, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step A2), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step A2), if the matching result exists, the connection state of the lookup table is equal to a semi-closed state, the role identification is a client, and meanwhile, the response count is equal to the queue count plus one, and then, updating the queue number, the response number and the window size;

A4) waiting for a message sent by a server, and entering the next step after receiving the message;

A5) analyzing the message type, judging whether the message is a connection request message cancelled by the server, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step A4), if so, matching a lookup table according to the message header information, and if not, discarding the message and returning to the step A4), if matching results exist and the connection state of the lookup table is equal to a semi-closed state, the role identification is a client, and meanwhile, the response count is equal to the queue count plus one, updating the queue number, the response number and the window size, sending a response message to the server, and starting a continuous timer;

A6) and when the time of the continuous timer is up, updating the connection state of the lookup table into a closing state.

Further, step 17) is followed by a step of revoking the connection by the server, which specifically includes the following steps:

B1) waiting for a message sent by the client, and entering the next step after receiving the message;

B2) analyzing the message type, judging whether the message type is a connection canceling request, if so, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message, if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step B1), if so, setting the connection state of the lookup table to be a semi-closed state, updating the queue number, the response number and the window size, and sending a connection canceling response message;

B3) after the connection cancellation response message is sent, sending a server side connection cancellation request message to the client side;

B4) waiting for a message sent by the client, if the message sent by the client is not received within a preset time, sending a connection canceling request message of the server to the client again, and entering the next step after receiving the message;

B5) analyzing message types, judging whether the messages are response messages or not, if so, judging whether the destination port information in the messages is the same as the destination port in the configuration parameters or not, if not, discarding the messages and returning to the step B4), if so, matching the lookup table according to the message header information, if not, discarding the messages and returning to the step B4), if matching results exist and the connection state of the lookup table is equal to a semi-closed state, and if the role identifier is a service end, updating the connection state of the lookup table to be a closed state, and updating the number of queues, the number of responses and the size of a window.

Compared with the prior art, the invention has the advantages that:

in the system, the FPGA computing board card comprises a network interface module and a core computing module which are connected with each other, the network interface module has the basic function of a TCP/IP protocol, high-speed network data transmission is realized by utilizing the bandwidth of the FPGA, the problem of large data volume transmission among system operation devices is solved, and therefore data transmission delay is reduced.

The method realizes data transmission between the upper computer and the FPGA computing board card and data forwarding between the FPGA computing board cards, and in the data forwarding process, each FPGA computing board card in the preset data transmission direction performs data processing before a final result is obtained, and the upper computer is only used for transmitting initial data to the FPGA computing board card and receiving final data from the FPGA computing board card and configuring the FPGA computing board card and controlling the connection state between the FPGA computing board cards, so that the intervention of the upper computer on the computing process is reduced.

Drawings

Fig. 1 is a schematic connection diagram of each device in an FPGA-based high-speed network data transmission system according to an embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating connection between an FPGA computing board and a network switch according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of connection relationships and data transmission of units in the FPGA computing board network interface module according to the embodiment of the present invention.

Fig. 4 is a functional block diagram of a FPGA computing board session unit according to an embodiment of the present invention.

Fig. 5 is a flowchart of a method for transmitting high-speed network data based on an FPGA according to an embodiment of the present invention.

Illustration of the drawings: 1-an upper computer; a 2-PCIe switch; 3-a network switch; and 4-FPGA calculation board card.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 1, the high-speed network data transmission system based on the FPGA of the present invention includes an upper computer 1, a PCIe switch 2, a network switch 3, and at least two FPGA computing boards 4 installed on the PCIe switch 2, the upper computer 1 is connected to each FPGA computing board 4 through the PCIe switch 2, as shown in fig. 2, the FPGA computing boards 4 are connected to each other through the network switch 3, as shown in fig. 3, the FPGA computing boards 4 include a network interface module and a core computing module that are connected to each other, the network interface module includes a media access control unit, a packet parsing unit, a packet editing unit, a session unit, and a cache unit, the network switch 3, the media access control unit, the session unit, the cache unit, the core computing module, and the upper computer 1 are sequentially connected in a bidirectional manner, the packet parsing unit is disposed between an output end of the media access control unit and an input end of the session unit in a data transmission direction from the, the package editing unit is arranged between the input end of the medium access control unit and the output end of the session unit in the data transmission direction from the upper computer to the network switch, wherein:

According to the FPGA-based high-speed network data transmission system, the FPGA calculation board card 4 connected with each other is used for carrying out data calculation and data transmission to obtain a final calculation result, the high-speed network data transmission is realized by utilizing the bandwidth of the FPGA, the problem of large data volume transmission among system operation devices is solved, and the data transmission delay is reduced.

In this embodiment, the upper computer 1 is only used for transmitting initial data to the FPGA computing board 4 and receiving final data from the FPGA computing board 4, and configuring the FPGA computing board 4 and controlling the connection state between the FPGA computing board 4, and the FPGA computing board 4 computes data and realizes data transmission between different FPGA computing boards 4 according to the configuration of the upper computer, thereby reducing the intervention of the upper computer on the computing process.

In this embodiment, the cache unit is connected to the core computing module through the AXI-Stream interface, so as to facilitate data transceiving after being docked with the core computing module.

As shown in fig. 4, the session unit in this embodiment includes a session checker, a session maintainer and a lookup table, the session checker is connected with the session maintainer in two ways through the lookup table, the packet parsing unit is connected with the cache unit through the session checker, and the packet editing unit is connected with the cache unit through the session maintainer, where:

As shown in fig. 5, the present invention further provides a high-speed network data transmission method based on FPGA, which is applied to the high-speed network data transmission system based on FPGA, and includes the following steps:

step 1), each FPGA calculation board card 4 is respectively electrified to be ready;

step 2), the upper computer 1 restarts and identifies each FPGA computing board card;

step 3) the upper computer 1 respectively configures network interface parameters of each FPGA computing board card;

step 4), connection is established between every two FPGA computing board cards 4, connection numbers are generated, and the connection numbers of each pair of FPGA computing board cards 4 are sent to the upper computer 1 respectively;

step 5) the upper computer 1 configures the data transmission direction between the FPGA computing board cards 4 according to the connection number, and in the embodiment, the upper computer 1 generates a data transmission table comprising the connection number after determining the data transmission direction between the FPGA computing board cards 4;

step 6) the upper computer 1 selects a message sending FPGA calculation board card from the FPGA calculation board cards 4 and sends operation data to a core calculation module of the message sending FPGA calculation board card;

step 7), in the message sending FPGA calculation board card, the core calculation module sends the calculation result and the corresponding connection number in the data transmission table to the cache unit, and the cache unit stores the calculation result in a cache space and sends a data sending request to the session unit;

step 13) in the message receiving FPGA computing board card, after the packet analysis unit receives the message, firstly, the message is subjected to validity check, and then message header information and data load are extracted and sent to a session unit;

step 16) in the message receiving FPGA computing board, the core computing module performs operation after receiving the data load to obtain an operation result, judges whether the operation result needs to be sent to other FPGA computing boards 4 for further computation according to the received connection number and the configuration of the upper computer 1, if so, the current message receiving FPGA computing board is used as a message sending FPGA computing board and returns to the step 7), otherwise, the operation result and the operation completion notice are sent to the upper computer 1 and enter the step 17), as can be known from FIG. 3, the FPGA computing board 4 in the embodiment can be used as a data receiving end and a data sending end at the same time, so the FPGA computing board 4 corresponds to at least 2 connection numbers, the message receiving FPGA computing board matches all the connection numbers corresponding to the message receiving FPGA computing board with a data transmission table, if the matching result except the received connection numbers exists, the computation is performed, and the current message receiving FPGA computing board is used as a message sending FPGA computing board, determining the next message receiving FPGA computing board card according to the matching result except the received connection number and returning to the step 7);

and step 17) after the upper computer 1 receives the operation result and the operation completion notification, the data transmission is finished, and the work of the FPGA calculation board cards 4 can be stopped, so that the connection cancellation notification is sent to each pair of FPGA calculation board cards 4.

In this embodiment, the simplest TCP/IP protocol is used, so that the message can be forwarded to different FPGA computing boards 4 through the switch, and data transmission is further implemented. The simplified IP message of TCP carried by the TCP/IP protocol is not fragmented, so that the maximum transmission unit meets 1500 Byte. The header of the second layer has the size of 14 bytes, does not need to support the virtual local area network, but needs to be superposed with the cyclic redundancy check of 4 bytes. The IP message header has the size of 20 bytes, the band option is not required to be supported, and the maximum length of all data fields has 1024 bytes. The TCP header has a size of 20 bytes, session establishment is supported with options, data transmission is without options, and the protocol specified options field is 8 bytes.

According to the above embodiment, in order to achieve a 100G rate, in this embodiment, a Xilinx100G hard CMAC core needs to be used on the FPGA computing board 4, a data bit width of the mac unit is 512 bits at 322.266MHz, and the 512 bits are connected in a 250MHz clock domain, because 100Gbps can be provided only by running at a frequency of about 195MHz, in step 3 of this embodiment, the upper computer 1 sets a clock frequency of all network interface modules of the FPGA computing board 4 to 200MHz, and the data bit width is 512 bits. The PCIe switch 3 uses the Xilinx hardmac, and uses the supporting driver development control software. The control software and the PCIe driver run on the upper computer 1 and mainly realize the functions of configuring and controlling a network interface module and a core computing module of the FPGA computing board 4, issuing the computing data and receiving the computing result.

In this embodiment, the cache unit can simultaneously cache 128 (number of connections) × 2 (number of packets) × 1024B equal to 2048Kb, and the size of the data storage space is 256 Kb. Because the data bus bit width is 512 bit/8 equals 64B, the depth of the data storage space can be calculated as 256KB/64B equals 2^ k, k is 12. Suppose the cell size of the data storage space is 8B × 2^5, which is exactly an integral multiple of the load, i.e. the data size of 4 storage cells is enough to be one load, so that the total storage cell number of the data cache space is 256KB/(32 × 8B) equal to 1K. The next-hop address cache space corresponding to the storage unit is realized by using a true dual-port RAM, the depth is 10 bits, the width is 10 bits, the head pointer and the tail pointer are also realized by using the true dual-port RAM, the depth is 7 bits, and the width is 10 bits. Each link only has one head pointer and one tail pointer, 128 positions are needed for storing the head pointer and the tail pointer of 128 links, and 128 RAMs with the depth of 7 bits can just store 128. Since the number of connections is assumed to be 128, the efficient mapping of the corresponding head and tail pointers is implemented using a 128-bit wide register. The mapping of the idle pointers is also realized by using a true dual-port RAM, the depth is 10 bits, the width is 10 bits, all the connections share the pointers of the whole cache space, and the data storage space of all the connection sharing cache units is also realized.

In this embodiment, step 4) specifically includes the following steps:

step 4.1) selecting one FPGA calculation board card 4 as a client, and selecting another FPGA calculation board card 4 as a server;

step 4.2) the upper computer 1 provides configuration parameters of a client and a server respectively, different FPGA computing board cards 4 are configured with different MAC addresses and IP addresses respectively, the upper computer provides a source MAC, a source IP and a source port of the client, and provides a destination MAC, a destination IP and a destination port of the server at the same time;

step 4.3) the upper computer 1 sends a connection establishing instruction to the client, the client initiates a connection establishing request to the server, the server responds to the request, the client and the server respectively carry out validity check, namely whether a destination IP address, a source port and a destination port in the message header information have matching results in the lookup table, if no matching result exists, the client returns a connection success report after establishing new connection and sends a connection number to the upper computer 1; if the matching result shows that the connection exists, the client returns a report that the connection exists to the upper computer 1; if the server does not respond in the specified time, the client returns a report of connection failure to the upper computer;

In step 4.3) of this embodiment, the client and the server both start a retransmission timer, a duration timer, and a keep-alive timer to maintain different states, where:

the retransmission timer is used for starting after sending data, if the acknowledgement is not received after a plurality of times, the data is retransmitted, and the time interval of the retransmission timer can be adjusted through configuration;

the continuous timer is used for starting after receiving a confirmation that the window size is 0, regularly inquiring whether the window is updated or not, wherein the initial value of the continuous timer is the same as that of the retransmission timer, if the response from the opposite side is not received, the detection message segment is sent, the value of the continuous timer is doubled and reset until the value of the continuous timer is increased to the threshold value, and then the message is sent to the opposite side by taking the threshold value as a time interval until the window is opened again;

the keep-alive timer is used for resetting the server side every time the server side receives the data of the client side within a preset first time interval; if the server side does not receive the data of the client side in the first time interval, the server side sends a detection message to the client side in the second time interval, if the server side still does not receive the response of the client side after the continuous sending times reach the threshold value, the server considers that the client side has a fault, and the upper computer can send an instruction to terminate the connection.

In this embodiment, the client and the server establish a connection through three-way handshake, and step 4.3 includes a step of internal processing of the client and a step of internal processing of the server, where:

the internal processing of the client specifically comprises the following steps:

step 4.3.1 a) after acquiring the connection establishing instruction, matching the message header information configured by the upper computer with the lookup table, and returning a connection existing report to the upper computer if a matching result exists; if the matching result does not exist, establishing a lookup table entry, setting a successful establishment identifier, updating other information of the entry, and establishing a synchronous message with the type of establishing a connection request to be sent to the server and starting a retransmission timer, in the embodiment, a session maintainer in a session unit of the client sends a link establishment instruction and configures link establishment information by an upper computer, message header information comes from the upper computer during first handshake, except that the message during the first handshake is configured by the instruction sent by the upper computer 1, other response messages of the client are all initiated by a session checker in the session unit, and the message establishment information is obtained by inquiring the lookup table;

step 4.3.3 a) analyzing the message, judging whether the message type is a connection establishment response message, if so, judging whether the source port information in the message is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step 4.3.2 a), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step 4.3.2 a), if the matching result exists and a message ack _ num = a table item seq _ num +1, the meaning of the program language is that the message answer number is the next queue number of the table item, and meanwhile, the table item is a service end identifier, updating the lookup table, setting the state of the table item to be valid, updating the queue number, answer number and window size, starting a keep timer and triggering a session maintainer in a session unit to send a connection establishment confirmation message to the service end;

step 4.3.4 a) waiting for the keep alive timer to reset, if the keep alive timer is reset, generating a connection number corresponding to the connection establishment between the client and the server, returning a report of successful connection and sending the connection number to the upper computer, if a connection establishment response message sent by the server is received, sending a connection establishment confirmation message to the server again and then continuing waiting, and after the number of times of receiving the connection establishment response message sent by the server reaches a first threshold value, returning a report of connection failure to the upper computer, ending and exiting;

the internal processing of the server specifically comprises the following steps:

step 4.3.4 b) analyzing the message, judging whether the message type is a connection establishment confirmation message, if yes, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message and returning to the step 4.3.3 b), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step 4.3.3 b), and if so,:

the message seq _ num = the entry ack _ num;

the message ack _ num = the table entry seq _ num + 1;

table entry role _ flag =1 (server);

the meaning of the above program language is: and when the conditions are met, updating the lookup table, setting the table entry state to be effective, resetting the keep-alive timer, and establishing connection at the moment.

In this embodiment, step 4.3.4 b) further includes a step of starting a persistent timer, which specifically includes: analyzing the message, if the window size of the message is 0, starting a continuous timer, wherein the time initial value of the continuous timer is the same as that of the retransmission timer, the time maximum value of the continuous timer is smaller than a preset second threshold value, if the message sent by the client is not received within the time of the continuous timer, sending a connection establishment response message to the client, doubling the time value of the continuous timer and resetting until the message sent by the client is received within the time of the continuous timer and the window size of the message is larger than 0.

As shown in fig. 3 to fig. 5, after the connection is established, the upper computer 1 can obtain the connection number of each pair of FPGA computing boards 4, that is, it is known whether the link establishment between the FPGA computing boards 4 is completed, and if the link establishment between two FPGA computing boards 4 is completed, data transmission can be performed, so that the upper computer 1 can control the data transmission between the FPGA computing boards 4. Initial data calculated by a core calculation module of the FPGA calculation board 4 at the message sending end needs to be sent by an upper computer through PCIe, and a result generated by the core calculation module through calculation is transmitted to a cache unit through an AXI-Stream interface. When the core computing module sends data to the cache unit, the connection number obtained by matching the data transmission table informs the cache module of which connection the data needs to be sent, and the core computing module also specifies to which FPGA computing board 4 the data needs to be sent. After receiving the data, the cache unit sends a data sending request. The session unit judges whether the data can be sent or not according to the request signal and the connection number, and if the data can be sent, a confirmation message is sent to the cache unit to acquire the data. If the data of the cache unit is sufficient, the data size of the maximum load of the data message, namely the data of 1024 bytes, is obtained at one time, and then the message header information and the load are sent to the packet editing unit. The packet editing unit edits the received message header information and load into a complete data message and sends the complete data message to the medium access control unit. The media access control unit stores, deserializes and processes the data packet into a packaged data packet and then sends the data packet to the network switch 3 through the optical fiber, and the network switch 3 forwards the data packet to the FPGA computing board 4 of the message receiving end according to the message header information. The FPGA computing board 4 at the message receiving end receives the data packet, processes the data packet into a message through the medium access control unit and sends the message to the packet analysis unit, the packet analysis unit analyzes the key field of the message to be encapsulated again, the legality of the message is checked, the analyzed load is stored in the FIFO, and then the new combined field and the analyzed load are sent to the session unit. And the session unit performs table lookup and verification according to the analyzed message header information, if the message has no error and is sent to the FPGA computing board 4 of the message receiving end, the load is sent to the cache unit, and a confirmation message is replied to the FPGA computing board 4 of the message sending end, otherwise, the message header information and the data are discarded, the confirmation message is not replied, and the next message is waited to be received. And finally, the buffer unit can sequentially send the received load to a core calculation module of the FPGA calculation board 4 at the message receiving end, so that data transmission among different FPGA calculation board 4 is realized. If the FPGA computing board 4 of the message sending end does not receive the confirmation message and the retransmission timer reaches the time required for retransmission, the session unit of the FPGA computing board 4 of the message sending end will send the message to the FPGA computing board 4 of the message receiving end again.

In this embodiment, step 17) is followed by a step of revoking the connection by the FPGA computing board, where the connection revoking process is completed according to a standard four-way handshake, and in this embodiment, the step of revoking the connection by the FPGA computing board includes a step of revoking the connection by the client and a step of revoking the connection by the server, where:

the client connection revocation specifically comprises the following steps:

A1) receiving a connection revocation notification issued by the upper computer 1, matching a connection number in the connection revocation notification with a lookup table, and returning a revocation failure result to the upper computer if no matching result exists; if the matching result exists, setting the connection state of the lookup table to be a semi-closed state, updating other information of the table entry by using a corresponding program with the language of bitmap = 2' b11 (half _ closed), constructing an end message with the type of canceling the connection request, sending the end message to a corresponding server, and starting a retransmission timer;

A3) analyzing the message type, judging whether the message type is a connection cancellation response message, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step A2), if so, matching a lookup table according to the message header information, if not, discarding the message and returning to the step A2), if the matching result exists and there are bitmap = 2' b11& & role _ flag =0 (client) & & ack _ num = u +1, the program language meaning is that the connection state of the lookup table is equal to a semi-closed state, the role is identified as the client, meanwhile, the response count is equal to the queue count plus one, if the above conditions are met, the queue number, the response number and the window size are updated, and at this time, the client completes one-way connection cancellation;

A5) analyzing the message type, judging whether the message is a service terminal connection withdrawal request message, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step A4), if so, matching a lookup table according to the message header information, if not, discarding the message and returning to the step A4), if so, matching results are provided, and bitmap = 2' b11& & role _ flag =0 (client) & _ ack _ num = u +1 is provided, the program language meaning is that the lookup table connection state is equal to a semi-closed state, the role identification is a client, meanwhile, the response count is equal to the queue count plus one, if the conditions are met, the queue number, the response number and the window size are updated, and a response message is sent to the service terminal and a continuous timer is started;

A6) and when the time of the continuous timer is up, updating the connection state of the lookup table to be a closed state, wherein the corresponding program is in a language of bitmap = 2' b00, and at the moment, the bidirectional withdrawal connection between the client and the server is completed.

The connection revocation of the server specifically comprises the following steps:

B2) analyzing the message type, judging whether the message type is a connection cancellation request, if so, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message, if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step B1), if so, setting the connection state of the lookup table to be a semi-closed state, and if the corresponding program is a language of bitmap = 2' B11 (half _ closed), updating the queue number, the response number and the window size, and sending a connection cancellation response message;

B5) analyzing the message type, judging whether the message type is a response message, if so, judging whether the destination port information in the message is the same as the destination port in the configuration parameters, if not, discarding the message and returning to the step B4), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step B4), if the matching result exists and there is bitmap =2 'B11 & & role _ flag =1(server) & & seq = u +1& & ack _ num = w +1, the meaning of the program language is that the connection state of the lookup table is equal to a semi-closed state, the role identifier is a service end, if the above conditions are met, the connection state in the lookup table is updated to be a closed state, the corresponding program is that the language is bitmap = 2' B00, and meanwhile, the queue number, the response number and the window size are updated.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims

1. The high-speed network data transmission system based on the FPGA is characterized by comprising an upper computer (1), a PCIe (peripheral component interconnect express) switch (2), a network switch (3) and at least two FPGA computing board cards (4) arranged on the PCIe switch (2), wherein the upper computer (1) is connected with each FPGA computing board card (4) through the PCIe switch (2), the FPGA computing board cards (4) are mutually connected through the network switch (3), the FPGA computing board cards (4) comprise a network interface module and a core computing module which are mutually connected, the network interface module comprises a medium access control unit, a packet analyzing unit, a packet editing unit, a session unit and a cache unit, the network switch (3), the medium access control unit, the session unit, the cache unit, the core computing module and the upper computer (1) are sequentially and bidirectionally connected, and the packet analyzing unit is arranged in the data transmission direction from the network switch (3) to the upper computer (1) Between access control unit's output and session unit's input, the package editor unit sets up in host computer (1) to network switch (3) data transmission direction on between medium access control unit's input and session unit's output, wherein:

2. The FPGA-based high-speed network data transmission system of claim 1, wherein said cache units are connected to said core computation module via an AXI-Stream interface.

3. The FPGA-based high-speed network data transmission system of claim 1 wherein said session unit comprises a session checker, a session maintainer and a lookup table, said session checker being bidirectionally coupled through said lookup table and said session maintainer, said packet parsing unit being coupled through said session checker and said caching unit, said packet editing unit being coupled through said session maintainer and said caching unit, wherein:

the session maintainer is used for executing the initiation of establishing a connection request or canceling the connection request according to the configuration of the upper computer (1), executing the acquisition and the sending of the data load in the cache unit, and also used for completing the message response according to the TCP/IP protocol.

4. An FPGA-based high-speed network data transmission method applied to the FPGA-based high-speed network data transmission system according to any one of claims 1 to 3 is characterized by comprising the following steps of:

step 1), each FPGA computing board card (4) is respectively electrified to be ready;

step 2), restarting the upper computer (1) and identifying each FPGA computing board card (4);

step 3) the upper computer (1) configures network interface parameters of each FPGA computing board card (4) respectively;

step 4), connection is established between every two FPGA calculation board cards (4) to generate connection numbers, and the connection numbers of each pair of FPGA calculation board cards (4) are respectively sent to the upper computer (1);

step 5), the upper computer (1) configures the data transmission direction between the FPGA computing board cards (4) according to the connection number;

step 6) the upper computer (1) selects a message sending FPGA calculation board card from the FPGA calculation board cards (4) and sends operation data to a core calculation module of the message sending FPGA calculation board card;

step 10) in the message sending FPGA computing board card, after the media access control unit receives the message, caching the message and packaging the message into a data packet according to the IEEE802.3 standard, then sending the data packet to a network switch (3), simultaneously starting a timer, if the data packet response message sent by the message receiving FPGA computing board card is not received after the preset time, returning to the step 8) to start to repeatedly send the data message sent this time until the message is received and the data message response message sent by the FPGA computing board card is received;

step 11), the network switch (3) forwards the received data packet to the message receiving FPGA computing board card according to the message header information;

step 15) in the message receiving FPGA computing board card, the cache unit stores the received load into a cache space and sends a data sending request to the core computing module, and after the response of the core computing module is received, the load is taken out from the cache and sent to the core computing module together with the connection number;

step 16) in the message receiving FPGA calculation board card, the core calculation module performs calculation after receiving the load to obtain a calculation result, whether the calculation result needs to be sent to other FPGA calculation board cards for further calculation is judged according to the received connection number and the configuration of the upper computer (1), if yes, the current message receiving FPGA calculation board card is used as the message sending FPGA calculation board card and returns to the step 7), and if not, the calculation result and the calculation completion notice are sent to the upper computer (1) and the step 17 is entered;

and step 17) after receiving the operation result and the operation completion notification, the upper computer (1) sends a connection cancellation notification to each pair of FPGA computing boards.

5. The FPGA-based high-speed network data transmission method according to claim 4, wherein the step 4) specifically comprises the following steps:

step 4.1), selecting one FPGA calculation board card (4) as a client, and selecting the other FPGA calculation board card (4) as a server;

step 4.2) the upper computer (1) generates configuration parameters of the client and the server;

step 4.3) the upper computer (1) sends a connection establishing instruction to the client, the client initiates a connection establishing request to the server, the server responds to the request, the client and the server respectively carry out validity check, if the connection is not established, the client returns a connection success report after establishing new connection and sends a connection number to the upper computer (1); if the connection is existed, the client returns the report that the connection is existed to the upper computer (1); if the server does not respond in the specified time, the client returns a report of connection failure to the upper computer (1);

and 4.4) returning to the step 4.1) until connection is established between every two FPGA computing board cards (4) and a connection number is generated.

6. The FPGA-based high-speed network data transmission method according to claim 5, wherein the step 4.3) includes a step of client internal processing, which specifically includes:

step 4.3.1 a) after acquiring the connection establishing instruction, extracting message header information in the configuration parameters and matching the lookup table, and if a matching result exists, returning a report of the connection to the upper computer (1); if the matching result does not exist, establishing a new lookup table item, setting a successful establishment identifier, updating other information of the table item, constructing a synchronous message with the type of establishing a connection request, sending the synchronous message to a server side, and starting a retransmission timer;

step 4.3.2 a) waiting for the data sent by the server, and if the data sent by the server is not received after the preset time, sending the synchronous message to the server again; if the retrieval number sent by the server is received within the preset time period, the matching result of the lookup table is obtained according to the retrieval number, then the existing report is returned to be connected to the upper computer (1), and the operation is finished and quitted; if the message sent by the server is received within the preset time period, entering the step 4.3.3 a); if the message sent by the server is not received within the preset time period, returning a connection failure report to the upper computer (1), ending and exiting;

step 4.3.4 a) waiting for the keep alive timer to reset, if the keep alive timer is reset, generating a connection number corresponding to the connection establishment between the client and the server, returning a report of successful connection and sending the connection number to the upper computer (1), if receiving a connection establishment response message sent by the server, sending a connection establishment confirmation message to the server again and then continuing waiting, and after the number of times of receiving the connection establishment response message sent by the server reaches a first threshold, returning a report of connection failure to the upper computer (1), ending and exiting.

7. The FPGA-based high-speed network data transmission method according to claim 5, wherein the step 4.3) includes a step of server-side internal processing, which specifically includes:

step 4.3.1 b) waiting for the message sent by the client, entering step 4.3.2b if the message sent by the client is received within a preset time period, if the message sent by the client is not received within the preset time period, returning a connection failure report to the upper computer (1), ending and exiting;

8. The FPGA-based high-speed network data transmission method according to claim 7, further comprising a step of starting a duration timer before step 4.3.4 b), specifically comprising: analyzing the message, if the window size of the message is 0, starting a continuous timer, wherein the time initial value of the continuous timer is the same as that of the retransmission timer, the time maximum value of the continuous timer is smaller than a preset second threshold value, if the message sent by the client is not received within the time of the continuous timer, sending a connection establishment response message to the client, doubling the time value of the continuous timer and resetting until the message sent by the client is received within the time of the continuous timer and the window size of the message is larger than 0.

9. The FPGA-based high-speed network data transmission method according to claim 5, further comprising a step of the client disconnecting after the step 17), and specifically comprising the steps of:

A1) receiving a connection revocation notification issued by the upper computer (1), matching a connection number in the connection revocation notification with the lookup table, and returning a revocation failure result to the upper computer (1) if no matching result exists; if the matching result exists, setting the connection state of the lookup table to be a semi-closed state, updating other information of the table entry, constructing an end message with the type of canceling the connection request, sending the end message to a corresponding server side, and starting a retransmission timer;

A5) analyzing the message type, judging whether the message is a connection request message cancelled by a server side, if so, judging whether the source port information in the message header information is the same as the source port in the configuration parameters, if not, discarding the message and returning to the step A4), if so, matching a lookup table according to the message header information, and if not, discarding the message and returning to the step A4), if so, matching results and the connection state of the lookup table is equal to a semi-closed state, the role identification is a client side, and meanwhile, the response count is equal to the queue count plus one, updating the queue number, the response number and the window size, sending a response message to a message sending FPGA computing board card, and starting a persistence timer;

A6) and when the time of the continuous timer is up, updating the connection state of the corresponding table entry in the lookup table to be in a closed state.

10. The FPGA-based high-speed network data transmission method according to claim 5, further comprising a step of the server disconnecting after the step 17), and specifically comprising the following steps:

B2) analyzing the message type, judging whether the message type is a connection canceling request, if so, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message, if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step B4), if so, setting the connection state of the lookup table to be a semi-closed state, updating the queue number, the response number and the window size, and sending a connection canceling response message;

B5) analyzing the message type, judging whether the message is a response message, if so, judging whether the destination port information in the message header information is the same as the destination port in the configuration parameters, if not, discarding the message and returning to the step B4), if so, matching the lookup table according to the message header information, if not, discarding the message and returning to the step B4), if the matching result exists, the connection state of the lookup table is equal to a semi-closed state, and the role identifier is a service end, updating the connection state of the lookup table to be a closed state, and updating the number of queues, the number of responses and the size of the window.