CN111736453A - Method and circuit structure for controlling abnormal instruction output - Google Patents
Method and circuit structure for controlling abnormal instruction output Download PDFInfo
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- CN111736453A CN111736453A CN202010560595.1A CN202010560595A CN111736453A CN 111736453 A CN111736453 A CN 111736453A CN 202010560595 A CN202010560595 A CN 202010560595A CN 111736453 A CN111736453 A CN 111736453A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
A method and a circuit structure for controlling abnormal instruction output comprise a reset circuit, a partition time sequence power supply circuit, an instruction generating latch circuit and a redundant signal control instruction driving circuit. A redundant latch circuit is adopted as an instruction generating circuit, a plurality of latches respectively generate pulse control signals to form multi-pulse control signals, and instructions can be output only when the multi-pulse control signals are effective; the independent power supply unit is used for separately supplying power to the instruction generating circuit and the instruction driving circuit, the power supply of the instruction driving circuit is controlled by a reset signal, the instruction driving circuit is powered on after the instruction generating circuit is powered on, and abnormal instruction output in the power-on process is forbidden; the voltage of a power supply of the subarea is monitored in real time, a reset signal is generated when the voltage is lower than a normal power supply range to power off the instruction driving circuit, so that abnormal fluctuation of the voltage is lower than a normal value or the instruction driving circuit is powered off in the power-off and power-down process, and abnormal instruction output is avoided. The invention can effectively improve the reliability of instruction output.
Description
Technical Field
The invention relates to a computer technology, in particular to a method and a circuit structure for controlling abnormal instruction output.
Background
Under the strong support of the country, China is rapidly developed in the aerospace field, such as missions of 'shenzhou' airship, 'sky palace' and 'big dipper', and the like, the spacecrafts and the satellites are required to be provided with a plurality of expensive aerospace computer devices.
The circuit structure of the traditional aerospace computer instruction generation and output functional unit is shown in fig. 1, and mainly comprises a single latch instruction generation circuit (54AC273) and an instruction driving circuit (double KG25 or single B9179T) controlled by redundant signals; meanwhile, a system reset circuit (JR706RD) provides a reset pulse signal of 200 milliseconds when the system reset circuit is powered on, the power is down to be below a threshold value (2.93V) or an external reset signal is effective (less than 1.25V), and the reset pulse signal resets and clears the latch; the circuits are provided with a single power supply conversion circuit (LS883) for converting a power supply providing + 5V; when an output instruction needs to be generated, software sets the corresponding bit of the latch to be high fixed instruction pulse time, then clears the corresponding bit of the latch, thereby generating a control instruction pulse with fixed time pulse width, and then controlling the instruction driving circuit to output the instruction. Therefore, the traditional circuit is simple in structure, the latch generates a single control signal to control the instruction driving circuit, but the latch is easily influenced by space single particles, and the electromagnetic interference triggers and overturns the latch position to generate an output abnormal instruction; meanwhile, the latch is easy to generate an output abnormal instruction due to incomplete synchronization in the power-on process and the power-off process; under the normal power-on condition, the output abnormal command can be generated due to the fluctuation of the power supply voltage, the reliability of the space navigation computer is reduced under the conditions, the flight mission can be failed due to abnormal action, and the great economic loss is caused.
Disclosure of Invention
The present invention aims to provide a method and a circuit structure for controlling abnormal instruction output, which can avoid abnormal instruction output and effectively improve reliability, aiming at the problem of insufficient reliability of computer instruction generation and output in the prior art.
In order to achieve the purpose, the invention has the following technical scheme:
a method of controlling exception instruction output, comprising:
using a redundant latch circuit as a command generating circuit, generating pulse control signals by a plurality of latches respectively to form multi-pulse control signals, wherein the command can be output only when the multi-pulse control signals are all valid;
-separate power supply is provided to the command generation circuit and the command driving circuit by an independent power supply unit, the power supply of the command driving circuit is controlled by a reset signal, the command driving circuit is powered on after the command generation circuit is powered on, and abnormal command output in the power-on process is forbidden;
and monitoring the voltage of the power supply of the subarea in real time, and generating a reset signal to power off the command driving circuit when the voltage is lower than a normal power supply range so as to enable abnormal fluctuation of the voltage to be lower than a normal value or power off the command driving circuit in the power-off and power-down process to power off the command driving circuit, thereby avoiding abnormal command output.
Preferably, the control command driving circuit is 200ms later than the power-on time of the command generating circuit.
Preferably, the threshold value of the normal power supply range of the processor is 4.5V, and the voltage threshold value of the reset signal is 2.63V.
A circuit arrangement for controlling exception instruction output, comprising:
the reset circuit has a power-on or power-off reset function, a watchdog reset function and a power supply partition voltage monitoring function;
the power supply circuit comprises two power supply units, wherein one power supply unit supplies power to a reset circuit and a command generation circuit and is powered on or off along with the power-on or power-off of a system power supply, the other power supply unit supplies power to a command driving circuit, a control end is connected with a reset signal, the power-on is delayed under the control of the reset signal, and the power is firstly turned off in the abnormal fluctuation and power-off processes of the system power supply;
the generating instruction latch circuit is built by adopting redundant latches, all the latches are cleared by reset signals, and an independent processor writes in signals to carry out latch setting and clearing, and the redundant latches respectively output redundant instruction control signals;
the redundant signal controls the command driving circuit, and the control signals of the command driving circuit are respectively connected with the outputs of different latches.
As a preferred scheme, the reset circuit is built by adopting a JR706RD chip with aerospace quality grade, the reset voltage threshold is 2.63V, the reset time is 200ms, the watchdog time is 1.6s, the power supply partition voltage monitoring threshold is 1.25V, PFO pins and WDO pins are connected/MR pins through an AND-gate chip, when the abnormal fluctuation of the system power supply voltage is lower than the normal power supply voltage of a processor by 4.5V and higher than the reset voltage threshold in an interval of 2.63V, the reset circuit does not generate a system reset signal, resistors R1 and 49.9K omega with 1% precision are divided by a resistor R2 with 1% precision to generate a voltage lower than the input voltage monitoring threshold of a PFI pin by 1.25V, the output of the PFO pin is low level, the chip/MR pin signal is triggered to generate the system processor to reset, the command drive circuit is immediately powered off, and the latch is still in a normal working state.
As a preferred scheme, the partition time sequence power supply circuit adopts two power supply conversion chips LS883 with space navigation quality grades to build two power supply units, wherein one power supply unit provides a 5V power supply for a reset circuit, an AND gate chip and a latch, the control end of the power supply conversion chip is connected with a system power supply, the other power supply unit provides a 5V power supply for an instruction driving circuit, the control end of the power supply conversion chip is connected with the control of a reset signal, 200ms power-on is delayed under the control of the reset signal, and when the abnormal fluctuation of the system power supply is lower than a normal value of 4.5V and the power-off process is carried out, the power-off.
Preferably, the command-generating latch circuit is built using two redundant latch chips 54AC273, each set to a 1K Ω resistor pull-down to avoid floating indeterminate states.
As a preferable scheme, the redundant signal control instruction driving circuit is built by adopting a double-KG 25 chip or a single LB8169T chip with a redundant control signal end, and two control signals are respectively connected with the outputs of two latches to form a command output of redundant control.
Compared with the prior art, the invention has the following beneficial effects: the independent power supply unit is used for supplying power to the instruction generating circuit and the instruction driving circuit separately, the instruction generating circuit is directly electrified along with a system power supply, and the instruction driving circuit is used for supplying power and controlling late electrification by using the reset signal, so that in the electrifying process before the system power supply voltage does not reach the normal voltage, the instruction generating circuit can prohibit abnormal instruction output because the instruction driving circuit is not electrified and is in a closed state, and the output of the error instruction in the electrifying process is realized. By monitoring the power supply voltage of the power supply subarea of the system processor in real time, when the abnormal fluctuation of the system power supply voltage is lower than a normal value or the power-off and power-down processes, the instruction driving circuit is immediately powered off, so that the abnormal instruction output generated by the mistakenly-set latch due to program runaway is avoided when the processor is in the abnormal power supply voltage power-down condition or the system power-off process. The invention adopts the redundant latch circuit as the instruction generating circuit and the instruction driving circuit of the redundant control signal, the processor software adopts the two-time setting latch to generate the corresponding double-instruction pulse control signal, and the instruction can be output only when the two control pulse signals are effective at the same time, thereby greatly reducing the possibility of generating abnormal instructions due to interference and having very high control reliability.
Drawings
FIG. 1 is a schematic diagram of a conventional command generation circuit;
fig. 2 is a schematic diagram of the circuit configuration of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Compared with the figure 1 and the figure 2, along with the development of deep space exploration application in China, the aerospace computer with the instruction output functional unit must prohibit the output of abnormal instructions, on the basis of the traditional instruction generation and output functional unit circuit, the invention adopts a method that an instruction generation circuit and a driving circuit are partitioned and power is supplied and disconnected according to time sequence, monitors the power supply voltage of a system in real time, and adopts the technology that redundant double latches are adopted to generate instructions, so that the abnormal instructions of the aerospace computer can be completely prohibited from being generated and output, and the reliability of the aerospace computer is greatly improved. Compared with the traditional circuit, the redundancy latch circuit 54AC273 is adopted to generate the double-pulse control signal, and the two latches are respectively used for generating the double-pulse control signal, so that the corresponding double-pulse control signal is effective and can be output, and the circuit reliability is greatly improved compared with the traditional single latch; the power supply of the instruction generating circuit and the power supply of the instruction driving circuit are separately and independently powered, and the power supply circuit of the instruction driving interface circuit is controlled by a reset signal, so that the instruction driving circuit can be powered on about 200ms after the instruction generating circuit is powered on, and abnormal instruction output in the power-on process of the aerospace computer can be forbidden; and thirdly, the real-time monitoring of the power supply voltage of the power supply subarea of the system processor is added, and the voltage is lower than the normal power supply range of the processor by 4.5V and immediately generates a reset signal to power off the instruction driving circuit, so that the power-off function of the instruction output circuit can be realized in the process that the abnormal fluctuation of the voltage is lower than the normal value or the power-off and power-down processes are carried out, and the abnormal instruction output is avoided.
The method for controlling abnormal instruction output comprises the following steps: a redundant latch circuit is adopted as an instruction generating circuit, a plurality of latches respectively generate pulse control signals to form multi-pulse control signals, and instructions can be output only when the multi-pulse control signals are effective; the independent power supply unit is used for supplying power to the instruction generating circuit and the instruction driving circuit separately, the power supply of the instruction driving circuit is controlled by a reset signal, the instruction driving circuit is controlled to be 200ms later than the power-on time of the instruction generating circuit, and abnormal instruction output in the power-on process is forbidden; the voltage of a power supply of a subarea is monitored in real time, a reset signal is generated when the voltage is lower than a normal power supply range to power off the instruction driving circuit, the threshold value of the normal power supply range of the processor is 4.5V, and the voltage threshold value of the reset signal is 2.63V, so that the abnormal fluctuation of the voltage is lower than a normal value or the instruction driving circuit is powered off in the power-off and power-down processes, and the output of abnormal instructions is avoided.
The invention also provides a circuit structure for controlling abnormal instruction output, which comprises:
the reset circuit has a power-on or power-off reset function, a watchdog reset function and a power supply partition voltage monitoring function; the aerospace quality grade JR706RD chip is adopted for construction, the reset voltage threshold is 2.63V, the reset time is about 200ms, the watchdog time is 1.6s, the power supply partition voltage monitoring threshold is 1.25V, PFO pins and WDO pins are connected with the AND gate chip/MR pins, and the AND gate chip is 54AC 08. When the abnormal fluctuation of the system power supply voltage is lower than the normal power supply voltage of the processor by 4.5V and is higher than the reset voltage threshold value within the range of 2.63V, the reset circuit does not generate a system reset signal, the system reset signal is generated by dividing voltage of a resistor R2 with the precision of 1% through resistors R1 and 49.9K omega with the precision of 130K omega, the input voltage of a PFI pin is lower than the monitoring threshold value of the input voltage of a PFI pin by 1.25V, the output of the PFO pin is low level, a chip/MR pin signal is triggered to generate the reset of the system processor, the instruction driving circuit is immediately powered off, and the latch is still in.
The power supply circuit comprises two power supply units, wherein one power supply unit supplies power to a reset circuit and a command generation circuit and is powered on or off along with the power-on or power-off of a system power supply, the other power supply unit supplies power to a command driving circuit, a control end is connected with a reset signal, the power-on is delayed under the control of the reset signal, and the power is firstly turned off in the abnormal fluctuation and power-off processes of the system power supply; the partition time sequence power supply circuit adopts two power supply conversion chips LS883 with space navigation quality grades to build two power supply units, wherein one power supply unit provides a 5V power supply for a reset circuit, an AND gate chip and a latch, the control end of the power supply conversion chip is connected with a system power supply, the other power supply unit provides a 5V power supply for an instruction driving circuit, the control end of the power supply conversion chip is connected with a reset signal for control, 200ms power-on is delayed under the control of the reset signal, and when the abnormal fluctuation of the system power supply is lower than a normal value of 4.5V and the power-off process is carried out, the power.
And an instruction latch circuit is generated, two redundant latch chips 54AC273 are adopted for building, the two redundant latch chips are all cleared by a reset signal, an independent processor writing signal is provided for setting and clearing the latches, the redundant latches respectively output redundant instruction control signals, and 1K omega of resistance pull-down is arranged to avoid floating uncertain states.
The redundant signal control instruction driving circuit is built by adopting a double KG25 chip or a single LB8169T chip with a redundant control signal end, and the two control signals are respectively connected with the output of the two latches to form redundant control instruction output.
The invention relates to a method and a circuit structure for controlling abnormal instruction output, which can prohibit abnormal instruction output in the power-on process, abnormal voltage fluctuation and power-off process of a system by adopting a partition time sequence power supply technology, a real-time detection system power supply voltage technology, a redundant instruction control signal generating circuit and a redundant control signal driving circuit; meanwhile, all circuits are high-reliability components with aerospace quality grade in flight experience, the space high-energy ion irradiation influence resistance of the components is very strong, abnormal instruction output can be completely forbidden, the reliability is high, and the requirement of satellite detection in China on space environment adaptability can be met.
The Hall electric propulsion is a new generation electric propulsion technology adopted by satellites in China, a geostationary satellite can adopt the propulsion technology, and a Hall electric propulsion power conversion unit digital controller is key control equipment of the Hall electric propulsion power conversion unit digital controller. The method for controlling the output of the abnormal instruction, which is developed based on aerospace-level components with flight experience, can completely forbid the output of the abnormal instruction, has very high reliability, can be widely applied to space, and has important reference value for other high-reliability control equipment with instruction output such as aviation and ground.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the technical solution of the present invention, and it should be understood by those skilled in the art that the technical solution can be modified and replaced by a plurality of simple modifications and replacements without departing from the spirit and principle of the present invention, and the modifications and replacements also fall within the protection scope covered by the claims.
Claims (8)
1. A method of controlling exception instruction output, comprising:
using a redundant latch circuit as a command generating circuit, generating pulse control signals by a plurality of latches respectively to form multi-pulse control signals, wherein the command can be output only when the multi-pulse control signals are all valid;
-separate power supply is provided to the command generation circuit and the command driving circuit by an independent power supply unit, the power supply of the command driving circuit is controlled by a reset signal, the command driving circuit is powered on after the command generation circuit is powered on, and abnormal command output in the power-on process is forbidden;
and monitoring the voltage of the power supply of the subarea in real time, and generating a reset signal to power off the command driving circuit when the voltage is lower than a normal power supply range so as to enable abnormal fluctuation of the voltage to be lower than a normal value or power off the command driving circuit in the power-off and power-down process to power off the command driving circuit, thereby avoiding abnormal command output.
2. The method of controlling an abnormal instruction output according to claim 1, wherein:
the control command driving circuit is 200ms later than the power-on time of the command generating circuit.
3. The method of controlling an abnormal instruction output according to claim 1, wherein:
the threshold value of the normal power supply range of the processor is 4.5V, and the voltage threshold value of the reset signal is 2.63V.
4. A circuit arrangement for controlling output of an exception instruction, comprising:
the reset circuit has a power-on or power-off reset function, a watchdog reset function and a power supply partition voltage monitoring function;
the power supply circuit comprises two power supply units, wherein one power supply unit supplies power to a reset circuit and a command generation circuit and is powered on or off along with the power-on or power-off of a system power supply, the other power supply unit supplies power to a command driving circuit, a control end is connected with a reset signal, the power-on is delayed under the control of the reset signal, and the power is firstly turned off in the abnormal fluctuation and power-off processes of the system power supply;
the generating instruction latch circuit is built by adopting redundant latches, all the latches are cleared by reset signals, and an independent processor writes in signals to carry out latch setting and clearing, and the redundant latches respectively output redundant instruction control signals;
the redundant signal controls the command driving circuit, and the control signals of the command driving circuit are respectively connected with the outputs of different latches.
5. The circuit arrangement for controlling an abnormal instruction output according to claim 4, wherein: the reset circuit is built by adopting a JR706RD chip with space navigation quality grade, the reset voltage threshold is 2.63V, the reset time is 200ms, the watchdog time is 1.6s, the power supply partition voltage monitoring threshold is 1.25V, PFO pins and WDO pins are connected with an AND gate chip/MR pins, when the abnormal fluctuation of the system power supply voltage is lower than the normal power supply voltage of a processor by 4.5V and higher than the reset voltage threshold in the range of 2.63V, the reset circuit does not generate a system reset signal, through 130K omega, resistors R1 and 49.9K omega with the precision of 1 percent, the voltage division of a resistor R2 with the precision of 1 percent generates the voltage lower than the PFI pin input voltage monitoring threshold by 1.25V, the PFO pin output is low level, the chip/MR pin signal is triggered to generate the reset of the system processor, the command drive circuit is immediately powered off, and the latch is still in the normal working state.
6. The circuit arrangement for controlling an abnormal instruction output according to claim 5, wherein: the partition time sequence power supply circuit adopts two power supply conversion chips LS883 with space navigation quality grades to build two power supply units, wherein one power supply unit provides a 5V power supply for a reset circuit, an AND gate chip and a latch, the control end of the power supply conversion chip is connected with a system power supply, the other power supply unit provides a 5V power supply for an instruction driving circuit, the control end of the power supply conversion chip is connected with a reset signal for control, 200ms power-on is delayed under the control of the reset signal, and when the abnormal fluctuation of the system power supply is lower than a normal value of 4.5V and the power-off process is carried out, the power-off.
7. The circuit arrangement for controlling an abnormal instruction output according to claim 4, wherein: the generate instruction latch circuit is built with two redundant latch chips 54AC273, each set to a resistance pull down of 1K Ω to avoid floating indeterminate states.
8. The circuit arrangement for controlling an abnormal instruction output according to claim 4, wherein:
the redundant signal control instruction driving circuit is built by adopting a double KG25 chip or a single LB8169T chip with a redundant control signal end, and two control signals are respectively connected with the output of two latches to form redundant control instruction output.
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Cited By (1)
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| CN113380167A (en) * | 2021-06-15 | 2021-09-10 | 西安微电子技术研究所 | Aerospace-grade nixie tube display driving circuit and application thereof |
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