CN111736059A - Chip testing method, testing equipment and testing system - Google Patents
Chip testing method, testing equipment and testing system Download PDFInfo
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- CN111736059A CN111736059A CN202010628049.7A CN202010628049A CN111736059A CN 111736059 A CN111736059 A CN 111736059A CN 202010628049 A CN202010628049 A CN 202010628049A CN 111736059 A CN111736059 A CN 111736059A
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Abstract
The present disclosure relates to a test method, a test apparatus, and a test system for a chip. The test method comprises the following steps: measuring a first current in a state where each core is supplied with a power supply voltage but is not supplied with data and a clock; measuring a second current in a state where each of the cores is supplied with the power supply voltage but not with the data, and at least a first part of the cores are also supplied with the clock having the first frequency; measuring a third current in a state where each of the cores is supplied with the power supply voltage but not with the data, and at least the cores of the first portion are also supplied with the clock having the second frequency; measuring a fourth current in a state where each of the cores is supplied with the power supply voltage, at least the first portion of the cores are also supplied with the clock having the second frequency but not with the data, and the second portion of the cores are also supplied with the data and the clock having the second frequency; and determining an estimated current of the chip in a case where the plurality of cores are supplied with the power supply voltage, the data, and the clock having the third frequency, based on at least the measurement result of the above step.
Description
Technical Field
The present disclosure relates to a chip testing method, a testing apparatus, and a testing system.
Background
At present, the packaged chip is usually tested (pass/fail Test) by using a Test Pattern (Test Pattern) generated based on Automatic Test Pattern Generation (ATPG), and the yield is calculated. Often, the "mining" chips for virtual currency also employ this test vector based final test method.
However, the inventors of the present application have found in practice that ATPG testing has its limitations, particularly for ore mining chips. At present, a plurality of cores (cores) with the same function are often integrated in a mining chip. ATPG testing is not sufficient to fully test the performance of an ore core chip. In practice, the differences between the performance exhibited by different mining machines in operation remain large, affecting the mining machine yield. The yield cannot be accurately expected, and the operation and the sale are influenced.
Therefore, a new chip testing method, testing apparatus and testing system are required.
Disclosure of Invention
According to an embodiment of the present disclosure, the following items are provided.
each of the one or more chips includes a plurality of cores, each core capable of being supplied with a supply voltage, data, and a clock,
the method comprises the following steps:
for each chip, the following steps are performed:
(A) measuring a first current (I) in a first stateleakage(V)) in the first state, each of the plurality of cores is supplied with a supply voltage but does not supply data and clocks;
(B) measuring a second current (I) in a second statestdby_osc_partial) In the second state, each of the plurality of cores is supplied with a supply voltage but not with data, and at least a first portion of the plurality of cores is also supplied with a first frequency (F)osc) The clock of (2);
(C) measuring a third current (I) in a third stateidle_partial) In the third state, each of the plurality of cores is supplied with the supply voltage but not with the data, and the cores of the at least first portion of the plurality of cores are also supplied with (F) having the second frequencyidle) Clock, theThe second frequency is higher than the first frequency;
(D) measuring a fourth current (I) in a fourth statecore_partial) In the fourth state, each of the plurality of cores is supplied with a supply voltage, the at least a first portion of the cores is also supplied with a clock having a second frequency but not with data, a second portion of the plurality of cores is also supplied with data and a clock having the second frequency, wherein the second portion is at least a part of the at least a first portion; and
(E) determining an estimated current of the chip with the plurality of cores supplied with the power supply voltage, the data, and the clock having a third frequency higher than the second frequency based at least on the measurement results of the above steps (a) to (D).
Item 2 the test method of item 1, wherein determining an estimated current of the chip with the plurality of cores supplied with power, data, and a clock having a third frequency from the results of the measuring comprises:
fitting is performed based on the results of the measurements to determine an estimated current of the chip with all of the plurality of cores supplied with power, data, and a clock having a third frequency.
Item 3, the test method of item 1, further comprising:
(F) based on the classification of each chip, the operating parameters thereof are determined.
Item 4, the test method of item 1, further comprising:
(G) performing the steps (A) - (E) at a first supply voltage;
(H) performing said steps (A) - (E) at different second power supply voltages;
(I) determining an estimated current of the chip in a case where the plurality of cores are supplied with different third power supply voltages, data, and clocks having a third frequency, based on at least the determination results of the above steps (G) to (H), wherein the third power supply voltage is higher than the first and second power supply voltages.
for each of the chips, the chip is,
(J) and calculating the index of the chip according to the estimated current.
Item 6, the test method of item 5, further comprising:
(K) classifying the one or more chips based on the indicator.
Item 7, the test method of any one of items 1 to 4, wherein at least one of:
the plurality of cores are identical to each other;
the plurality of cores are capable of performing the same operation on the same data;
the calculation of the respective received data by the plurality of cores is based on the same algorithm; and/or
The calculation of the plurality of checks on the respective received data is performed based on the same algorithm for the virtual money.
Item 8, the test method of any one of items 1 to 4,
the chip also has a reference frequency and a phase-locked loop based on the reference frequency,
wherein the first frequency is the reference frequency,
the second frequency is a multiple of the reference frequency,
the third frequency is the frequency output by the phase locked loop.
Item 9, the test method of any one of items 1 to 4, the one or more chips comprising a plurality of chips, the plurality of chips being powered in series.
Item 10, the test method of any one of items 1 to 4, each core in the chip comprising a data path to receive data and a clock path to transmit a clock signal, the data path comprising logic circuitry, the clock path comprising an inverter.
Item 12, the test method of item 5, wherein the indicator comprises a power consumption calculation ratio.
a test station configured to carry and test one or more chips to obtain parameters associated with the one or more chips, wherein each of the chips comprises a plurality of cores, each core capable of being supplied with a supply voltage, data, and a clock; and
a control device communicatively coupled to the test station configured to:
for each of the one or more chips:
(A) measuring a first current (I) in a first stateleakage(V)) in the first state, each of the plurality of cores is supplied with a supply voltage but does not supply data and clocks;
(B) measuring a second current (I) in a second statestdby_osc_partial) In the second state, each of the plurality of cores is supplied with a supply voltage but not with data, and at least a first portion of the plurality of cores is also supplied with a first frequency (F)osc) The clock of (2);
(C) measuring a third current (I) in a third stateidle_partial) In the third state, each of the plurality of cores is supplied with the supply voltage but not with the data, and the cores of the at least first portion of the plurality of cores are also supplied with (F) having the second frequencyidle) A clock, the second frequency being higher than the first frequency;
(D) measuring a fourth current (I) in a fourth statecore_partial) In the fourth state, each of the plurality of cores is supplied with a supply voltage, the at least a first portion of the cores is also supplied with a clock having a second frequency but not with data, a second portion of the plurality of cores is also supplied with data and a clock having the second frequency, wherein the second portion is at least a part of the at least a first portion; and
(E) determining an estimated current of the chip with the plurality of cores supplied with the power supply voltage, the data, and the clock having a third frequency higher than the second frequency based at least on the measurement results of the above steps (a) to (D).
Item 14, the test apparatus of item 13, wherein determining an estimated current of the chip with the plurality of cores supplied with power, data, and a clock having a third frequency from the results of the measuring comprises:
fitting is performed based on the results of the measurements to determine an estimated current of the chip with all of the plurality of cores supplied with power, data, and a clock having a third frequency.
Item 15, the test apparatus of item 13, the control device further configured to:
(F) based on the classification of each chip, the operating parameters thereof are determined.
(G) performing the steps (A) - (E) at a first supply voltage;
(H) performing said steps (A) - (E) at different second power supply voltages;
(I) determining an estimated current of the chip in a case where the plurality of cores are supplied with different third power supply voltages, data, and clocks having a third frequency, based on at least the determination results of the above steps (G) to (H), wherein the third power supply voltage is higher than the first and second power supply voltages.
for each of one or more of the chips,
(J) and calculating the power consumption calculation force ratio of the chip according to the estimated current.
Item 19, the test apparatus of item 18, further comprising:
(K) classifying the one or more chips based on the power consumption calculation ratio.
Item 20, the test device of any one of items 13-16, wherein at least one of:
the plurality of cores are identical to each other;
the plurality of cores are capable of performing the same operation on the same data;
the calculation of the respective received data by the plurality of cores is based on the same algorithm; and/or
The calculation of the plurality of checks on the respective received data is performed based on the same algorithm for the virtual money.
Item 21, the test device of any one of items 13-16,
the chip also has a reference frequency and a phase-locked loop based on the reference frequency,
wherein the first frequency is the reference frequency,
the second frequency is a multiple of the reference frequency,
the third frequency is the frequency output by the phase locked loop.
Item 22, the test apparatus of any one of items 13-16, the one or more chips comprising a plurality of chips, the plurality of chips being powered in series.
Item 23, the test apparatus of any one of items 13-16, each core in the chip comprising a data path to receive data and a clock path to transmit a clock signal, the data path comprising logic circuitry, the clock path comprising an inverter.
Item 24, the test apparatus of item 1, wherein in steps (B) and (C), the at least a first portion of the cores of the plurality of cores includes all of the plurality of cores.
Item 25, a test system comprising a computing device, the computing device comprising:
a processor; and
a storage device having code stored therein, the code when executed by the processor performing the method of any of items 1-12.
Item 26, the test system of item 25, further comprising: a test station configured to carry and test one or more chips to obtain parameters associated with the one or more chips,
the processor is communicatively coupled to the test station.
Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.
The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
FIG. 1 schematically illustrates partial pressure conditions of multiple core pieces (or nuclei) of an ore machine;
fig. 2 schematically shows the voltage division of chips with similar standby currents (internal resistances);
FIG. 3 shows a block diagram of a chip according to an example embodiment of the present disclosure;
FIG. 4 illustrates logic on the clock path of each core in a chip according to an example embodiment of the present disclosure;
FIG. 5 illustrates logic on the data path of each core in a chip according to an example embodiment of the present disclosure;
fig. 6 is a scatter diagram and a horizontal/vertical direction projection histogram illustrating leakage currents at different voltages for a plurality of chips according to an exemplary embodiment of the present disclosure;
fig. 7 is a scatter diagram and a horizontal/vertical direction projection histogram illustrating leakage currents at different frequencies for a plurality of chips according to an exemplary embodiment of the present disclosure;
FIG. 8 is a scatter plot and a horizontal/vertical projection histogram illustrating logic flip currents on clock paths of multiple chips at different frequencies according to an example embodiment of the present disclosure;
FIG. 9 is a scatter plot and horizontal/vertical projection histogram illustrating logic flip currents on clock paths of multiple chips at different frequencies according to an example embodiment of the present disclosure;
FIG. 10 is a scatter plot and a horizontal/vertical projection histogram illustrating logical flip currents on data paths at different frequencies for multiple chips according to an example embodiment of the present disclosure;
FIG. 11 is a scatter plot and a horizontal/vertical projection histogram illustrating logical flip currents on data paths at different frequencies for multiple chips according to an example embodiment of the present disclosure;
FIG. 12 shows a flow diagram of a method according to an embodiment of the present disclosure;
FIG. 13 illustrates sorting of one or more chips based on power consumption algorithm ratio according to an example embodiment of the present disclosure; and
FIG. 14 illustrates another classification of one or more chips based on power consumption effort ratio according to an example embodiment of the present disclosure.
Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.
For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise. Additionally, techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification as appropriate.
It should be appreciated that the following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the disclosure, its application, or uses. It should also be understood that any implementation exemplarily described herein does not necessarily represent that it is preferred or advantageous over other implementations. This disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.
In addition, certain terminology may also be used in the following description for the purpose of reference only, and thus is not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless clearly indicated by the context.
It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 schematically illustrates partial pressure conditions of multiple chips (or cores) of an ore machine. As shown in fig. 1, chip 00, chip 01, chip 02, and chip 03 in an ore machine are schematically illustrated. It should be understood that although a chip is described herein as an example, a chip may be replaced with a core. The chips 00 to 03 respectively have different internal resistances R0、R1、R2、R3，VsourceIs the sum of the voltages of the chips. Since a plurality of chips in a mining machine are generally supplied with power in series, the voltage V obtained by dividing the chip 00 into the chip 030、V1、V2、V3Not the same. Partial pressure conditions of different chips can affect the startup/operation of the mining machine. Suppose the core in FIG. 1Internal resistance R of the sheet 022Much smaller than the internal resistance of the other chips, and the current through the chip 02 is determined by all the chips connected in series, so that the voltage V obtained by the chip 022It is less than the minimum voltage at which it can operate properly, resulting in its failure to operate properly. Therefore, in order to enable each chip to work normally, the standby current of each chip needs to be measured during the final test.
Fig. 2 schematically shows the voltage division of the chips with similar standby currents (internal resistances). As shown in FIG. 2, the standby currents (internal resistances) are similar or equal for chips 00 to 03, so that the same voltage (V) is used in the final test0＝V1＝V2＝V3) And carrying out a standby current test. If standby currents of the chips 00 to 03 are similar, when the chips are powered in series, the working voltages of the chips are relatively close, and the ore machine yield is improved.
On the other hand, when testing a chip, it is often difficult for the testing equipment to accurately restore the operating environment of the chip (e.g., temperature differences, power supply capabilities, testing time requirements, etc.). Furthermore, since mining machine chips often have multiple cores therein (e.g., tens or even hundreds), it is difficult for the testing device to test the performance or parameters of the chip under real operating conditions, which may even be out of range of the testing device, making testing impossible.
In view of this, the inventors of the present application propose the technology disclosed herein.
Fig. 3 shows a block diagram of a chip according to an exemplary embodiment of the present disclosure. Chip 300 shown in FIG. 3 includes a plurality of cores, such as core 00-core 3N shown in the figure. The plurality of cores may be arranged in a matrix form; but the present disclosure is not limited thereto. It should be understood that the number of cores is merely exemplary, and chips according to the present disclosure may include more or fewer chips. According to various embodiments, chip 300 may also include communication/control logic. The communication/control logic module may communicate with the cores to communicate instructions, addresses, data, and the like. In some implementations, each core may also be designed with enable/disable control functionality. For example, activation/deactivation of each core may be controlled by a communication/control logic module.
In some embodiments, the plurality of cores are identical to each other. For example, the structures of the plurality of cores in the chip may be identical to each other. In some embodiments, the multiple cores are capable of performing the same operation on the same data. In some embodiments, multiple cores in the chip perform computations on the respective received data based on the same algorithm, e.g., based on the same algorithm for virtual currency.
In some embodiments, the communication/control logic module may operate in a different voltage domain than the plurality of cores in the chip. Thus, in such embodiments, the analysis of the chip current may be without regard to the communication/control logic module, as will be described below. In other cases, the communication/control logic module may be considered an additional core of the chip to perform similar analysis, if desired.
Next, the current composition of each core in the chip will be described with reference to fig. 4 and 5.
FIG. 4 illustrates logic on the clock path of each core in a chip according to an example embodiment of the present disclosure. FIG. 5 illustrates logic on the data path of each core in a chip according to an example embodiment of the present disclosure. As shown in fig. 4 and 5, the core may include data circuitry and clock circuitry. Here, the data circuit is schematically shown as a logic circuit (e.g., a combination of D flip-flops connected to each other (fig. 4), a combination of D flip-flops and inverters, and the like (fig. 5)); it is to be understood that this is merely exemplary to illustrate the principles of the invention. The present disclosure is not so limited. The data circuit receives data (e.g., 0 or 1 in the figure) and a clock CP. The clock circuit may provide a clock CP to the data circuit as needed. The clock circuit may transmit or process a clock signal such as, but not limited to, delay, inversion, and the like. Therefore, here, a path where data is transmitted and processed is also referred to as a data path, and a path where a clock is transmitted and processed is also referred to as a clock path.
As an example, the current of each core in a chip may include mainly the following three types: leakage current, logic flip current on the clock path (hereinafter also referred to as clock current), and logic flip current on the data path (hereinafter also referred to as logic current). Here, it is easily understood by those skilled in the art that the current of the digital circuit mainly occurs at the time of logic inversion (or logic level transition), for example, the logic is changed from logic high (1) to logic low (0) or from logic low to logic high, that is, the logic level is changed from high to low or from low to high. Although positive logic is generally described herein as an example, the present invention may be equally or adaptively applied to negative logic.
FIG. 4 shows logic flips on a clock path of one core in a chip. For example, when a core is not enabled, the core does not provide data although it is provided with a power supply voltage and a clock. In this case, since there is no logic flip on the data path of a core, there is a logic flip or inversion of the clock signal level (e.g., corresponding to its rising or falling edge) on its clock path. As shown in the clock path in fig. 4, the clock signal is inverted at the inverter, thereby logically inverting, producing a logically inverted current (here, a clock current). The current measured for the core may be considered to include the leakage current of the core and the clock current of the core. The leakage current of the core may be due to leakage currents of devices within the core.
The current measured in this case is referred to herein as the standby current of the core, i.e., the standby current is the sum of the leakage current and the clock current.
Accordingly, for a chip including a plurality of cores, the sum of the clock current of each core is referred to as the clock current of the chip, and the sum of the drain current and the clock current of each core is referred to as the standby current of the chip. Here, it should be noted that a chip may include circuits or modules other than the plurality of cores, and those skilled in the art will readily understand that the principles and techniques taught by the present invention may also be equally or adaptively applied to additional circuits or modules, as desired. For example, the additional circuitry or modules may be treated as one core.
Here, it is also understood that leakage current may be difficult to obtain directly in the case of a chip or core in operation. Thus, it is contemplated herein that the current at which a core is supplied with a supply voltage but not with a clock and data may be referred to as a leakage current of the core. The leakage current in this case is close to that in the aforementioned case (i.e., the case where the core is supplied with no data although the power supply voltage and clock) and differs only in the leakage current of the device involved in the logic in which the inversion occurs. And the difference is substantially negligible when considered.
FIG. 5 also shows logic flips on the data path for each core in the chip. As shown in fig. 5, data 1 is supplied to the leftmost D flip-flop in the logic path, so that the output Q of the D flip-flop changes from 0 to 1. The output of the downstream inverter is changed from 1 to 0. While the output Q of the D flip-flop on the right remains 1. Thus, a current due to logic inversion is generated in the data path. This current is also referred to as the core's logic current. Correspondingly, the sum of the logic currents of the cores is referred to as the logic current of the chip.
As such, when each of a plurality of cores in a chip is supplied with a supply voltage, a clock, and data, the current of the chip (which may be measured or estimated) may be considered to include a leakage current of the chip, a clock current of the chip, and a logic current of the chip. Thus, it can be expressed as:
here, it should be understood that in the context of the present disclosure, the leakage current of the chip, the clock current of the chip, and the logic current of the chip are primarily considered for the plurality of cores of the chip.
Next, the relationship between the leakage current of the chip and the voltage and frequency will be described first with reference to fig. 6 and 7.
Fig. 6 is a scatter plot of the leakage current measured at 345mV and 375mV supply voltages for 98650(25 x 3946) chips, respectively, and a horizontal/vertical projection histogram for observing the scatter density. According to various embodiments, the supply voltage may be provided to the respective cores as a supply voltage.
In this figure, the X-axis is the leakage current measured at 375mV and the Y-axis is the leakage current measured at 345 mV.
For a chip, it will measure a leakage current value at a supply voltage of 345mV and will also measure a leakage current value at a supply voltage of 375mV, thus defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. Similarly, the histogram at the upper end indicates the number of chips corresponding to the current of the X-axis.
As can be seen from the histogram in fig. 6, the chips are distributed intensively around the peak, and the corresponding amount decreases as the current increases or decreases. As can be seen from the scatter data in fig. 6, the leakage current exhibits a distinct linear relationship at two different voltages. Fitting the scatter data of fig. 6 can result in a linear relationship: y ═ 0.985X + (-8.526).
Fig. 7 is a scatter diagram of leakage currents measured at clock frequencies of 120MHz and 168MHz, respectively, for 98650 chips, and a horizontal/vertical direction projection histogram for observing scatter density. Where the X-axis is the leakage current measured at 168MHz and the Y-axis is the leakage current measured at 120 MHz.
Similarly, for a chip, it will measure a leakage current value at a clock frequency of 120MHz, and will also measure a leakage current value at a clock frequency of 168MHz, thereby defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. The histogram at the upper end indicates the number of chips corresponding to the current of the X-axis. As can be seen from the histogram in fig. 7, the chips are distributed intensively around the peak, and the corresponding amount decreases as the current increases or decreases.
The linear relationship fitted to the data shown in FIG. 7 by linear regression is:
y is 0.998X + 99.20. The slope fit is 0.998, which can be approximated as 1. It can thus be seen that the frequency has substantially no effect on the leakage current.
Next, the relationship between the clock current and the frequency of the chip will be described with reference to fig. 8 and 9.
FIG. 8 is a scattergram of clock currents measured at clock frequencies of 120MHz and 168MHz, respectively, for 98650 chips, and a horizontal/vertical projection histogram for observing the scatter density. Where the X-axis is the clock current measured at a clock frequency of 168MHz and the Y-axis is the clock current measured at a clock frequency of 120 MHz. Although clock current is used as an example here, in different implementations the aforementioned standby current may also be utilized.
Similarly, for a chip, it will measure a clock current (or standby current as well) value at a clock frequency of 120MHz, and will also measure a clock current (or standby current) value at a clock frequency of 168MHz, thereby defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. The histogram at the upper end indicates the number of chips corresponding to the current of the X-axis. As can be seen from the histogram in fig. 8, the chips are distributed intensively around the peak, and the corresponding amount decreases rapidly as the current increases or decreases.
The linear relationship fitted to the data shown in fig. 8 by linear regression is:
y ═ 0.733X + (-99.074). The linear regression fit of fig. 8 gave a slope of 0.733. Here 168MHz × 0.733 — 123.144MHz confirms the accuracy of the fit.
FIG. 9 is a scatter plot of (and a horizontal/vertical projection histogram for observing scatter density at) clock currents measured at 144MHz and 168MHz, respectively, for 98650 chips, where the X-axis is the clock current measured at the clock frequency of 168MHz and the Y-axis is the clock current measured at the clock frequency of 144 MHz.
Similarly, for a chip, it will measure a clock current (or standby current as well) value at a clock frequency of 144MHz, and will also measure a clock current (or standby current) value at a clock frequency of 168MHz, thereby defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. The histogram at the upper end indicates the number of chips corresponding to the current of the X-axis. As can be seen from the histogram in fig. 9, the chips are distributed intensively around the peak, and the corresponding amount is rapidly decreased as the current is increased or decreased.
The linear relationship fitted to the data shown in fig. 9 by linear regression is: y ═ 0.865X + (-47.701). The linear regression fit of fig. 9 gave a slope of 0.865. Here 168MHz × 0.865 ═ 145.32MHz, the accuracy of the fit was confirmed.
The slope ratio from both fig. 8 and 9 is very close to the frequency ratio, thus demonstrating that the clock current is a linear function of its frequency.
Next, the relationship between the logic current and the frequency of the chip will be described with reference to fig. 10 and 11.
FIG. 10 is a scatter plot of the logic currents measured at clock frequencies of 120MHz and 168MHz, respectively, for 98650 chips, and a horizontal/vertical projection histogram for observing scatter density. Where the X-axis is the logic current measured at 168MHz and the Y-axis is the logic current measured at 120 MHz.
Similarly, for a chip, it will measure a logic current value at a clock frequency of 120MHz and will also measure a logic current value at a clock frequency of 168MHz, thereby defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. The histogram at the upper end indicates the number of chips corresponding to the current of the X-axis. As can be seen from the histogram in fig. 10, the chips are distributed intensively around the peak, and the corresponding amount decreases rapidly as the current increases or decreases.
FIG. 11 is a scatter plot of the logic currents measured at 144MHz and 168MHz for 98650 chips, respectively, and a horizontal/vertical projection histogram for observing the scatter density, where the X-axis is the logic current measured at 168MHz and the Y-axis is the logic current measured at 144 MHz.
Similarly, for a chip, it will measure a clock current (or standby current) value at a clock frequency of 144MHz and will also measure a clock current (or standby current) value at a clock frequency of 168MHz, thereby defining a point in the graph. The histogram on the right side indicates the number of chips corresponding to the Y-axis current. The histogram at the upper end indicates the number of chips corresponding to the current of the X-axis. As can be seen from the histogram in fig. 11, the chips are distributed intensively around the peak, and the corresponding amount decreases as the current increases or decreases.
The linear regression fit of FIG. 10 yields a linear relationship: y ═ 0.732X + (-29.952). The slope was 0.732. Here, 168MHz × 0.732 ═ 122.976MHz, the accuracy of the fitting was confirmed. The linear regression fit of FIG. 11 yields a linear relationship: y ═ 0.865X + -12.925. The slope is 0.865. Here, 168MHz × 0.865 ═ 145.32MHz confirms the accuracy of the fitting. The slope ratio of both is very close to the frequency ratio, thus proving that the logic current is a linear function of the frequency.
In summary, it can be demonstrated that the parts of the current of each core in the chip have the following characteristics:
leakage current is a function of voltage only;
the logic flip current on the clock path is a linear function of its frequency at a given voltage;
the logic flip current on the data path is a linear function of its frequency at a given voltage.
Based on the above features, during the final test, one supply voltage can first be fixed and then the current of the chip in each case can be measured and recorded by changing the state and frequency of each of the cores of each chip. An estimated operating current (estimated current) of the chip is calculated from the measurement result, and then a performance parameter of the chip, such as a power consumption calculation ratio, is calculated based on the estimated current. The chips are finally classified based on power consumption algorithm ratio and chips in each class are expected to have close operating currents.
Power consumption computation power ratio refers to the ratio of the power consumption of a chip to its computational power. For example, for an ore-machine chip for virtual currency, the power consumption computation rate may be characterized as the ratio of its operating power consumption to its number of hash computations per unit time.
Next, the chip test method of the present disclosure will be described in detail with reference to specific examples.
The chip may include a plurality of cores. Each of the plurality of cores can be supplied with a supply voltage, data, and a clock. In some embodiments, multiple chips may be powered in series.
Here, the definition is as follows:
Vbinrepresents a supply voltage, e.g. for a particular class (Bin).
FoscRepresents a first frequency, which may be a reference frequency, such as a default frequency (e.g., without limitation, the frequency of a crystal oscillator) at chip start-up, such as 24 MHz.
FidleRepresenting a second frequency. The second frequency is configured to be higher than the first frequency. For example, FidleMay be a default frequency provided when a Phase Locked Loop (PLL) in the chip is not configured. For example, it may be a multiple of the reference frequency, such as 120MHz, 144MHz or 168MHz as described previously. In some implementations, the PLL may be in a different voltage domain than the plurality of cores, in which case, only the voltage domain in which the plurality of cores are located may be considered for the chip, regardless of the PLL and its voltage domain.
FbinRepresenting a third frequency. The third frequency is configured to be higher than the second frequency. The third frequency may be a frequency output by the phase-locked loop PLL. FbinFrequencies for a particular category may be represented, such as frequencies of 600MHz or lower or higher.
NcoreRepresents the number of all cores in the chip, and Ncore_partialIndicates the number of cores of at least a first part of the plurality of cores (to be described later in more detail).
NenRepresenting the number of cores in the chip that are enabled (or may also be referred to as enabled). The enabled cores will be provided with data, such as test codes. In some cases, N, as will be explained belowenIs also used to indicate the number of cores of the second portion of the plurality of cores. Here, in an example explained later, NenThe individual cores may be said Ncore_partialAt least a part of a core, and Ncore_partialThe individual cores may be said NcoreAt least a portion of each core.
Furthermore, the clock current of a single core is a linear function of its operating frequency at a given voltage, which is defined as:
the logic current of a single core is a linear function of its operating frequency at a given voltage, defined as:
the leakage current of the entire chip is a function of its voltage, which is defined as: i isleakage(V). Here, f denotes frequency, and V denotes voltage.
FIG. 12 shows a flow diagram of a method according to an embodiment of the present disclosure.
In step S1201, a first current of the chip in the first state is determined. In some implementations, it may be measured that each core of a plurality of cores of a chip is provided with a supply voltage V (e.g., V)bin) But does not provide current in the data and clock states. The measured current can be regarded as the leakage current I of the whole chipleakage(V) (e.g., I)leakage(Vbin))。
In step S1203, a second current of the chip in the second state is determined. In some implementations, measurements are made at the plurality (e.g., N)coreCore(s) are all supplied with a supply voltage (e.g., V)bin) But does not provide data, and at least a portion (e.g., N) of the plurality of corescore_partialCore(s) is also provided having a first frequency (e.g., F)osc) The second current in the state of the clock. The measured current may be represented as Istdby_osc_partialIt is defined as follows:
here, alternatively, in some implementations, in the second state, each of the plurality of cores (i.e., N) may also be pairedcore_partial＝Ncore) All provide a first frequency (e.g., F)osc) Thereby measuring the second current.
In step S1205, a third current (I) of the chip in a third state is determinedidle_partial). In some implementations, measurements are made at the plurality (e.g., N)coreCore is supplied with a supply voltage (e.g., V)bin) But does not provide data, and the cores of the at least first portion of the plurality of cores (e.g., the N)core_partialCore) is also provided with a second frequency (e.g., F)idle) Current in the state of the clock. The measured current may be represented as Iidle_partialIt may be defined as follows:
here, alternatively, in some implementations, N may be setcore_partial＝Ncore。
In step S1207, a fourth current (I) of the chip in a fourth state is determinedcore_partial). In some implementations, measurements are made at the plurality (e.g., N)coreCore(s) are supplied with a supply voltage, the cores of the at least first portion (e.g., the N)core_partialCore) is also provided with a second frequency (e.g., F)idle) But does not provide data, and a second portion of the plurality of cores (e.g., N)enCore) is also provided with data and has a second frequency (e.g., F)idle) Current in the state of the clock. The measured current may be represented as Icore_partialIt may be defined as follows:
similarly, in some cases, the N isenThe individual cores may be said Ncore_partialAt least a portion of each core. In addition, in some cases, Ncore_partialThe individual cores may be said NcoreAt least a portion of each core.
In step S1209, an estimated current of the chip is determined based on at least the measurement results of the above steps. For example, an estimated current of the chip in a case where the plurality of cores are supplied with the power supply voltage, the data, and the clock having the third frequency may be determined based at least on the measurement results of the above steps. The third frequency may be configured to be higher than the second frequency; the present disclosure is not so limited.
For example, by solving equations (1) - (3) simultaneously, the following results can be obtained:
here:
Note that when N iscore_partialIs equal to NcoreThen, the above results can be simplified as:
wherein, Istdby_oscIs NcoreThe cores are supplied with a supply voltage VbinAnd has a first frequency FoscCurrent measured in the state of clock without data supply, IidleIs NcoreThe cores are supplied with a supply voltage VbinAnd has a second frequency FidleThe measured current in the state of not providing data, and IcoreIs NcoreThe cores are supplied with a supply voltage and have a second frequency FidleIs not providing data, and NenThe cores are also provided with data and have a second frequency FidleThe measured current in the state of the clock.
In some embodiments, a fit may be made based on the results of the measurements to determine an estimated current of the chip with all of the plurality of cores supplied with power, data, and a clock having a third frequency.
In addition, it is easily understood that the above measurement may be performed at different power supply voltages, respectively, as long as the power supply voltage can operate each of the plurality of cores.
For example, the above steps may be performed at the first power supply voltage. Thereafter, the above steps may be performed again at a different second power supply voltage. Determining an estimated current of the chip in a case where the plurality of cores are supplied with different third power supply voltages, data, and clocks having a third frequency, based on at least a determination result of performing the above steps at the first and second power supply voltages, wherein the third power supply voltage is higher than the first and second power supply voltages.
According to some embodiments of the present disclosure, the current I may also be estimated for each chip according tochipSome indexes of the chip are calculated. For example, the power consumption computation ratio of a chip can be calculated as follows:
according to some embodiments of the present disclosure, chips may also be classified based on the current through the chip measured or calculated/estimated as described above. As shown in table 1 below, the chips were classified into different gear positions (bins) at intervals of 100mA for their standby currents.
Table 1
In further embodiments of the present disclosure, the chips may be classified based on power consumption algorithm ratio. In some embodiments, the chips may be further classified based on the power consumption calculation ratio for each chip in the same standby current range based on table 1. In practice, a plurality of standby current gears can be combined, and then the chip can be divided into new gears according to the power consumption calculation ratio. According to some embodiments of the present disclosure, the corresponding operating parameters of the chip may also be determined according to the classification of the chip.
FIG. 13 shows a classification of chips based on power consumption computation force ratio. In fig. 13, the standby currents for each of the three current steps are combined and then classified according to the power consumption calculation ratio. For example, for the combined standby current gear 0mA-700mA, the chips may be further classified as A, B, C gears according to the power consumption calculation force ratio being less than 45.5, the power consumption calculation force ratio being greater than 45.5 and less than 46, and the power consumption calculation force ratio being greater than 46, as shown in fig. 13.
For example, when the following test conditions are employed during the final test: n is a radical ofcore＝348，Nen＝174，Fosc＝24MHz，Fidle＝128MHz，Vbin＝370mV，F bin600 MHz. The measured current values were: i isstdby_osc＝964.58mA，Iidle＝2078.9mA，Icore4194.81 mA. From this, it can be calculated: i ischip26972.88mA, PH 47.797. The chip can be classified into the G range according to the classification shown in fig. 13.
FIG. 14 shows another classification of chips based on power consumption algorithm force ratio. In fig. 14, the standby currents of every two current gears are combined first, and then classified according to the power consumption calculation ratio, for example, for the combined standby currents 0mA to 600mA, the chips can be further classified into gears 1_ a and 2_ B according to the power consumption calculation ratio smaller than 46 and the power consumption calculation ratio larger than 46.
According to the embodiment of the disclosure, the chip with relatively consistent standby current and/or normal operating current can be obtained, and then the chip with stable power consumption calculation force can be obtained. Such chips may be configured in the same device to work in concert. Different parameters can be distributed to chips of different classifications, different peripheral circuits can be matched, different selling prices can be made, and the like.
The present disclosure also contemplates a test apparatus. The test equipment comprises a test bench and a control device. The test station is used for carrying and testing one or more chips so as to obtain parameters related to the one or more chips. The control device is configured to be communicatively coupled to the test stand for controlling testing of the chip. Those skilled in the art will appreciate that a wide variety of suitable test stations known in the art or commercially available or developed in the future may be used herein. Each of the chips may include a plurality of cores. Each core can be supplied with a supply voltage, data and a clock.
The control means may be configured to, for each of the one or more chips:
(A) measuring a first current (I) in a first stateleakage(V)) in the first state, each of the plurality of cores is supplied with a supply voltage but does not supply data and clocks;
(B) measuring a second current (I) in a second statestdby_osc_partial) In the second state, each of the plurality of cores is supplied with a supply voltage but not with data, and at least a first portion of the plurality of cores is also supplied with a first frequency (F)osc) The clock of (2);
(C) measuring a third current (I) in a third stateidle_partial) In the third state, each of the plurality of cores is supplied with the supply voltage but not with the data, and the cores of the at least first portion of the plurality of cores are also supplied with (F) having the second frequencyidle) A clock, the second frequency being higher than the first frequency;
(D) measuring a fourth current (I) in a fourth statecore_partial) In the fourth state, each of the plurality of cores is supplied with a supply voltage, the at least a first portion of the cores is also supplied with a clock having a second frequency but not with data, a second portion of the plurality of cores is also supplied with data and a clock having the second frequency, wherein the second portion is at least a part of the at least a first portion; and
(E) determining an estimated current of the chip with the plurality of cores supplied with the power supply voltage, the data, and the clock having a third frequency higher than the second frequency based at least on the measurement results of the above steps (a) to (D).
In some embodiments, determining an estimated current of the chip with the plurality of cores all supplied with the power, the data, and the clock having the third frequency according to the result of the measurement includes: fitting is performed based on the results of the measurements to determine an estimated current of the chip with all of the plurality of cores supplied with power, data, and a clock having a third frequency.
In some embodiments, the control apparatus is further configured to: (F) based on the classification of each chip, the operating parameters thereof are determined.
In some embodiments, the control apparatus is further configured to: (G) performing the steps (A) - (E) at a first supply voltage; (H) performing said steps (A) - (E) at different second power supply voltages; (I) determining an estimated current of the chip in a case where the plurality of cores are supplied with different third power supply voltages, data, and clocks having a third frequency, based on at least the determination results of the above steps (G) to (H), wherein the third power supply voltage is higher than the first and second power supply voltages.
In some embodiments, the control apparatus is further configured to: for each of one or more of said chips, (J) calculating a power consumption calculation ratio for that chip based on said estimated current.
In some embodiments, the test apparatus further comprises: (K) classifying the one or more chips based on the power consumption calculation ratio.
In some embodiments: the plurality of cores are identical to each other; the plurality of cores are capable of performing the same operation on the same data; the calculation of the respective received data by the plurality of cores is based on the same algorithm; and/or the calculation of the respective received data by the plurality of checks is performed based on the same algorithm for virtual money.
In some embodiments, the chip also has a reference frequency and a phase-locked loop based on the reference frequency. In some embodiments, the first frequency is the reference frequency, the second frequency is a multiple of the reference frequency, and the third frequency is a frequency output by a phase-locked loop.
In some embodiments, the one or more chips comprise a plurality of chips, the plurality of chips being powered in series.
In some embodiments, each core in the chip includes a data path to receive data and a clock path to transmit a clock signal, the data path including logic circuitry, the clock path including an inverter.
In some embodiments, in steps (B) and (C), the at least a first portion of the cores of the plurality of cores includes all of the cores of the plurality of cores.
The present disclosure also contemplates a test system that includes a computing device. The computing device may include: a processor; and a storage device having code stored therein. The code, when executed by the processor, performs a method according to any of the embodiments of the present disclosure.
In some embodiments, the test system further comprises a test station configured to carry and test one or more chips to obtain parameters associated with the one or more chips. The processor may be communicatively coupled to the test station, for example, to control the test station or to provide information to or obtain information from the test station.
Those skilled in the art will appreciate that the boundaries between the operations (or steps) described in the above embodiments are merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A method of testing one or more chips,
each of the one or more chips includes a plurality of cores, each core capable of being supplied with a supply voltage, data, and a clock,
the method comprises the following steps:
for each chip, the following steps are performed:
(A) measuring a first current (I) in a first stateleakage(V)) in the first state, each of the plurality of cores is supplied with a supply voltage but does not supply data and clocks;
(B) measuring a second current (I) in a second statestdby_osc_partial) In the second state, each of the plurality of cores is supplied with a supply voltage but not with data, and at least a first portion of the plurality of cores is also supplied with a first frequency (F)osc) The clock of (2);
(C) measuring a third current (I) in a third stateidle_partial) At a placeThe third state, each of the plurality of cores being supplied with the power supply voltage but not with the data, the cores of the at least first portion of the plurality of cores being further supplied with (F) having the second frequencyidle) A clock, the second frequency being higher than the first frequency;
(D) measuring a fourth current (I) in a fourth statecore_partial) In the fourth state, each of the plurality of cores is supplied with a supply voltage, the at least a first portion of the cores is also supplied with a clock having a second frequency but not with data, a second portion of the plurality of cores is also supplied with data and a clock having the second frequency, wherein the second portion is at least a part of the at least a first portion; and
(E) determining an estimated current of the chip with the plurality of cores supplied with the power supply voltage, the data, and the clock having a third frequency higher than the second frequency based at least on the measurement results of the above steps (a) to (D).
2. The method of claim 1, wherein determining an estimated current of the chip with the plurality of cores all supplied with power, data, and a clock having a third frequency based on the results of the measuring comprises:
fitting is performed based on the results of the measurements to determine an estimated current of the chip with all of the plurality of cores supplied with power, data, and a clock having a third frequency.
3. The test method of claim 1, further comprising:
(F) based on the classification of each chip, the operating parameters thereof are determined.
4. The test method of claim 1, further comprising:
(G) performing the steps (A) - (E) at a first supply voltage;
(H) performing said steps (A) - (E) at different second power supply voltages;
(I) determining an estimated current of the chip in a case where the plurality of cores are supplied with different third power supply voltages, data, and clocks having a third frequency, based on at least the determination results of the above steps (G) to (H), wherein the third power supply voltage is higher than the first and second power supply voltages.
5. The test method of any one of claims 1-4, further comprising:
for each of the chips, the chip is,
(J) and calculating the index of the chip according to the estimated current.
6. The test method of claim 5, further comprising:
(K) classifying the one or more chips based on the indicator.
7. The test method according to any one of claims 1-4, characterized by at least one of the following:
the plurality of cores are identical to each other;
the plurality of cores are capable of performing the same operation on the same data;
the calculation of the respective received data by the plurality of cores is based on the same algorithm; and/or
The calculation of the plurality of checks on the respective received data is performed based on the same algorithm for the virtual money.
8. The test method according to any one of claims 1 to 4,
the chip also has a reference frequency and a phase-locked loop based on the reference frequency,
wherein the first frequency is the reference frequency,
the second frequency is a multiple of the reference frequency,
the third frequency is the frequency output by the phase locked loop.
9. A test apparatus, comprising:
a test station configured to carry and test one or more chips to obtain parameters associated with the one or more chips, wherein each of the chips comprises a plurality of cores, each core capable of being supplied with a supply voltage, data, and a clock; and
a control device communicatively coupled to the test station configured to:
for each of the one or more chips:
(A) measuring a first current (I) in a first stateleakage(V)) in the first state, each of the plurality of cores is supplied with a supply voltage but does not supply data and clocks;
(B) measuring a second current (I) in a second statestdby_osc_partial) In the second state, each of the plurality of cores is supplied with a supply voltage but not with data, and at least a first portion of the plurality of cores is also supplied with a first frequency (F)osc) The clock of (2);
(C) measuring a third current (I) in a third stateidle_partial) In the third state, each of the plurality of cores is supplied with the supply voltage but not with the data, and the cores of the at least first portion of the plurality of cores are also supplied with (F) having the second frequencyidle) A clock, the second frequency being higher than the first frequency;
(D) measuring a fourth current (I) in a fourth statecore_partial) In the fourth state, each of the plurality of cores is supplied with a supply voltage, the at least a first portion of the cores is also supplied with a clock having a second frequency but not with data, a second portion of the plurality of cores is also supplied with data and a clock having the second frequency, wherein the second portion is at least a part of the at least a first portion; and
(E) determining an estimated current of the chip with the plurality of cores supplied with the power supply voltage, the data, and the clock having a third frequency higher than the second frequency based at least on the measurement results of the above steps (a) to (D).
10. A test system comprising a computing device, the computing device comprising:
a processor; and
storage device having code stored therein, which when executed by the processor performs the method of any of claims 1-8.
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