CN111726111A - Bus driver module with control circuit - Google Patents
Bus driver module with control circuit Download PDFInfo
- Publication number
- CN111726111A CN111726111A CN202010512220.8A CN202010512220A CN111726111A CN 111726111 A CN111726111 A CN 111726111A CN 202010512220 A CN202010512220 A CN 202010512220A CN 111726111 A CN111726111 A CN 111726111A
- Authority
- CN
- China
- Prior art keywords
- control unit
- driver module
- path control
- voltage
- bus driver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007704 transition Effects 0.000 claims abstract description 62
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 238000009499 grossing Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004576 sand Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/06—Modifications for ensuring a fully conducting state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses a bus driver module with a control circuit, which is connected with a controller local area network bus and generates a high-voltage end output or a low-voltage end output. The transition area control circuit generates a switching voltage at one end and comprises a first path control unit and a second path control unit which are arranged in parallel. The output driver is connected in series with the transition region control circuit, and the receiving end switches the voltage to correspondingly generate an output bus signal. The first path control unit and the second path control unit respectively comprise a plurality of switch elements and can control whether the switch elements are started or not according to input signals. The invention controls the on and off of the switch elements in the first path control unit and the second path control unit in sequence, so that the end switching voltage has a smooth phase transition area, lower common mode noise and better electromagnetic protection capability.
Description
Technical Field
The present invention relates to a control circuit, and more particularly, to a transition region control circuit suitable for a controller area network bus application system and capable of achieving an accelerated transition between multiple phases and smoothness of a phase transition region thereof.
Background
Controller Area Network (CAN) is a standard established in the early 1990 s and standardized in 1993 (ISO 11898-1), and is widely used in various vehicles and electronic devices. Generally, a Controller Area Network (CAN) includes a serial bus that provides high security and efficient real-time control, and further provides error detection and priority discrimination mechanisms to make the transmission of network information more reliable and efficient. In view of the current development, the conventional controller area network not only has high flexible adjustment capability, but also can add stations in the existing network without performing modification and adjustment operations on software and hardware.
Referring to fig. 1, an architecture diagram of a prior art controller area network bus Transmitter (TX) is disclosed, in which an input voltage V is providedinIs processed by a front driver 11 and an output driver 12 at a high voltage end to generate an output voltage VoutThe CANH is output as the high voltage terminal. Likewise, the input voltage VinIs processed by a low-voltage end front driver 21 and an output driver 22 to generate an output voltage VoutCANL is output as a low voltage terminal.
Referring to fig. 2, a waveform diagram of a transmitting end architecture of the conventional can lan bus according to fig. 1 is disclosed, as shown in fig. 2, a high side output CANH and a low side output CANL are used to provide a set of differential signals. According to the present digital logic design, for example, as shown in FIG. 2, when CANH at the high side and CANL at the low side are both 2.5V (assuming that the supply voltage is 5V), it represents that a logic signal of "high level" is sent by the transmitter. Conversely, when the high-side output CANH rises to 3.5V (assuming a supply voltage of 5V) and the low-side output CANL falls to 1.5V (assuming a supply voltage of 5V), it indicates that the transmitter sends a logic signal of "low level". Therefore, in order to maintain excellent EMI (Electromagnetic Interference) protection performance, it is important to design a circuit well and maintain the DC stability of the high voltage side output CANH and the low voltage side output CANL.
Furthermore, for high-speed controller area networks (HS-CAN), the transmitter architecture is further required to provide both high data rate and low EMI performance. In the transition region of bus transition from the recessive mode (dominant mode) (output driver is OFF to ON) or from the dominant mode to the recessive mode (output driver is ON to OFF), the voltage slew rates (slew rates) of the bus signals CANH and CANL generated by the transmitter must be within a limited range to maintain low common mode noise, thereby optimizing the electromagnetic shielding capability. Similarly, the voltage levels of the bus signals CANH and CANL must reach their respective stable states within a short bit time (a short bit time). It follows that in order to achieve efficient control, the pre-driver in the transmitter architecture must have multiple phases to control its bus driver. In the prior art, although related technologies for multi-phase accelerated transition (multi-phase accelerated transition) are mentioned, none of the related technologies discloses a technology for smoothing a phase transition region thereof. In other words, in the prior art, when the transition region of the bus bar transition is involved, the turning point of the transition region is too sharp (sharp), which results in poor EMI performance.
Furthermore, in U.S. Pat. No. 6,154,061, the transistors in the circuit structure used therein are highly likely to enter into the saturation region (saturation region), and the output signal inevitably loses symmetry due to the process variation of the transistors. In view of the above, in order to overcome the above-mentioned drawbacks, it is obvious that those skilled in the art are eagerly required to develop a new and innovative bus driving control circuit structure capable of effectively solving the above-mentioned problems and having both novelty and creativity to ensure that the accelerated transition between multiple phases and the smoothness of the phase transition region thereof in the controller area network bus application can be realized.
Disclosure of Invention
To overcome the above-mentioned shortcomings, it is an object of the present invention to provide a novel transition region control circuit, which can successfully overcome the shortcomings of the prior art and has the capability of precisely controlling the output DC voltage level, so as to not only achieve the accelerated transition between multiple phases in the lan bus application system, but also achieve the smooth phase transition region.
Another objective of the present invention is to provide an innovative bus driver module with a control circuit, which can apply the disclosed transition region control circuit to the bus driver module, and integrate the transition region control circuit in the traditional front driver architecture, so that the front driver circuit of the novel transmitter has multi-phase characteristics, and the output driver has smooth and fast switching characteristics in the transition region, so as to achieve the effect of effectively controlling the bus driver.
It is still another object of the present invention to provide a bus driver module with a control circuit and a transition region control circuit thereof, wherein the disclosed novel front driver architecture not only has multiple phases for controlling the bus driver, but also can generate a smooth transition region output in the transition region between at least two phases. Meanwhile, the front driver architecture disclosed in the present invention not only enables the output signals CANH and CANL to reach steady state within a short bit time, but also has been verified to have low common mode noise and better EMI protection performance.
In order to achieve the above object, the present invention discloses a transition area control circuit, which is electrically connected to an input end and includes a first path control unit and a second path control unit, wherein the first path control unit is disposed in parallel to the second path control unit to generate a switching voltage, and the first path control unit and the second path control unit respectively include a plurality of switching elements.
And the output driver is electrically connected in series with the transition region control circuit to receive the end switching voltage and correspondingly generate an output bus signal suitable for the controller area network bus system. According to the present disclosure, the output bus signal may be a high side output (CANH) or a low side output (CANL) of the can bus.
An input signal can be input through the input end, so that one of the first path control unit or the second path control unit is conducted, and the plurality of switch elements in the first path control unit or the second path control unit are sequentially switched on, so that the end switching voltage has a smooth phase transition region.
According to a preferred embodiment of the present invention, the first path control unit and the second path control unit respectively include a main switch element and a plurality of auxiliary switch elements connected in parallel. The main switch element and the auxiliary switch element can be respectively connected with an impedance element. According to whether the input signal is at a high voltage level or a low voltage level, the main switch element of the first path control unit and the main switch element of the second path control unit can control any one of the first path control unit and the second path control unit to be conducted. After one of the first and second path control units is turned on based on the turning on of its main switching element, the plurality of auxiliary switching elements connected thereto are then sequentially turned on so that the voltage value of the end switching voltage is changed in a first phase state.
Then, the plurality of auxiliary switch elements are sequentially turned off, so that the voltage value of the end switching voltage is changed from the first phase state to the second phase state, and a phase transition region between the first phase state and the second phase state is smooth.
In another aspect, the at least one switch control circuit is configured to generate a plurality of control signals, and the control signals are used to control the auxiliary switch elements to be turned on and off sequentially. The switch control circuit can be connected between the input end and the first path control unit, so that the generated control signals can be transmitted to the auxiliary switch elements in the first path control unit, and the on-off state of each auxiliary switch element in the first path control unit is determined by each control signal. Similarly, another switch control circuit may be connected between the input terminal and the second path control unit, so that the generated control signal may be transmitted to the auxiliary switch element in the second path control unit, and each control signal is used to determine the on/off state of each auxiliary switch element in the second path control unit.
By such a design, the present invention can precisely control the plurality of auxiliary switching elements in the first path control unit or the second path control unit, thereby allowing the terminal switching voltage to have a smooth phase transition region.
According to an embodiment of the present invention, the switch control circuit comprises a pulse generator and a pulse train delay circuit connected in series with the pulse generator. The pulse generator receives an input signal and generates a pulse signal, and the pulse sequence delay circuit receives the pulse signal and generates a control signal for controlling the plurality of auxiliary switch elements.
In one embodiment, the pulse train delay circuit includes a plurality of delay units, and each delay unit is configured to generate a control signal to control a corresponding one of the auxiliary switch elements. For example, the delay unit may be a buffer.
In summary, the present invention provides a bus driver module with a control circuit and a transition area control circuit thereof, which are novel and novel through precise design. The novel circuit design can be integrated into a pre-driver architecture, not only can control the bus driver in multiple phase states, but also can realize smooth transition output of the pre-driver in the transition between two phase states. Meanwhile, the front-driver architecture proposed by the present invention has been further confirmed to have lower common mode noise and better EMI protection performance. Accordingly, it is believed that the present invention provides superior control stability for the CANH and CANL voltage signal outputs at the system level of the circuit, while maintaining accurate control of the dc output voltage level.
The objects of the present invention will be realized and attained by those skilled in the art in view of the following detailed description of the preferred embodiment of the invention.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention claimed. The purpose, technical content, features and effects of the present invention will be more readily understood by the following detailed description of the embodiments taken in conjunction with the accompanying drawings.
Drawings
Fig. 1 is a diagram illustrating a prior art architecture of a transmit side (TX) of a conventional controller area network bus.
Fig. 2 is a waveform diagram of a transmitting end architecture of the conventional can lan bus according to fig. 1.
Fig. 3 is a block diagram of a bus driver module with a control circuit according to an embodiment of the invention.
Fig. 4 is a detailed circuit diagram of the bus driver module having the control circuit shown in fig. 3 according to the present invention.
Fig. 5 is a schematic diagram of a bus driver module with a control circuit according to the present invention controlled by at least one switch control circuit.
Fig. 6 is a detailed circuit diagram of a switch control circuit according to an embodiment of the invention.
Fig. 7 is a waveform diagram disclosing the switching control circuit module shown in fig. 6, wherein the voltage signal when n is 4.
Fig. 8 is a circuit diagram of a bus driver module having a control circuit according to another embodiment of the invention, in which the first path control unit and the second path control unit respectively have only a single first auxiliary switch device and a single second auxiliary switch device.
FIG. 9 shows the output bus signal V of the transistor in the circuit configuration of FIG. 8 when the transistor has a process variationoutThe waveform diagram comprises a high-voltage end output CANH and a low-voltage end output CANL.
FIG. 10 is a waveform diagram illustrating the sum of the high-side output CANH and the low-side output CANL according to the process variation in FIG. 9.
FIG. 11 shows the circuit configuration shown in FIGS. 4 and 8 with the terminal switching voltage VsA comparative graph of (a).
FIG. 12 shows the circuit configuration shown in FIGS. 4 and 8, in which the bus signal V is outputtedoutThe comparison graph comprises a high-voltage end output CANH and a low-voltage end output CANL.
Description of reference numerals: 10-a transition region control circuit; 11-an input terminal; 11-a front actuator; 12-an output driver; 20-an output driver; 21-a front actuator; 22-an output driver; 100-a first path control unit; 200-a second path control unit; 500 a-a switch control circuit; 500 b-a switch control circuit; 52-a pulse generator; 521-an inverter; 523-capacitance; 525-a comparator; 527-AND gate; 54-a pulse train delay circuit; 541-a delay unit; SW1a — first primary switching element; SW1b, SW1c, SW1 n-first auxiliary switching element; SW2a — second main switching element; SW2b, SW2c, SW2 n-second auxiliary switching element; z1a, Z1b, Z1c, Z1 n-impedance element; z2a, Z2b, Z2c, Z2 n-impedance element.
Detailed Description
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In which the same reference numerals are used throughout the drawings and the description to refer to the same or like parts.
The following description of the embodiments of the present invention is provided to illustrate the technical features and characteristics of the present invention and to enable those skilled in the art to understand, make and use the present invention. It should be noted that the embodiments are not intended to limit the scope of the claims. In other words, any equivalent modified examples or variations based on the spirit of the present invention should also be included in the scope of the present invention, which is described in the first specification.
Referring to fig. 3, which is a block diagram of a BUS driver module with a control circuit according to an embodiment of the present invention, the BUS driver module with a control circuit disclosed in the present invention is electrically connected to a controller area network BUS (CAN BUS) and provides its outputOutgoing bus signal VoutAn output bus signal V of the controller LAN busoutComprises a group of differential signals of a high-voltage end output CANH and a low-voltage end output CANL.
According to an embodiment of the present invention, the bus driver module disclosed in the present invention mainly includes a transition controlled circuit (10) and an output driver (20), wherein the transition controlled circuit (10) is electrically connected to an input terminal (11) and includes a first path control unit (100) and a second path control unit (200) disposed in parallel. The connection point of the first path control unit 100 and the second path control unit 200 outputs a terminal switching voltage Vs。
Wherein, the first path control unit 100 is connected to the input end 11 and the end switching voltage VsAnd between the ground GND. The second path control unit 200 is connected to the supply voltage VccInput terminal 11 and terminal switching voltage VsIn the meantime.
According to the embodiment of the present invention, when an input signal is input through the input terminal 11, the first path control unit 100 or the second path control unit 200 is turned on alternatively according to a rising edge (rising edge) or a falling edge (falling edge) of the input signal and/or a high voltage level or a low voltage level thereof. For example, when the input signal is at a high voltage level, the first path control unit 100 is turned on, and the second path control unit 200 is turned off; on the contrary, when the input signal is at the low voltage level, the first path control unit 100 is turned off, and the second path control unit 200 is turned on. In order to further understand the technical features of the circuit architecture proposed by the present invention, please refer to fig. 4, which will be described in detail below.
Fig. 4 is a detailed circuit diagram of the bus driver module having the control circuit shown in fig. 3 according to the present invention. As shown, the first path control unit 100 is connected to the input terminal 11 and the terminal switching voltage VsAnd a ground GND, and includes at least a first main switch element SW1a and a plurality of first auxiliary switch elements SW1b, SW1c …, SW1n connected in parallel.
In one embodiment, the first main switch element SW1a and the first auxiliary switch elements SW1b, SW1c … SW1n are respectively connected to an impedance element Z1a, Z1b, Z1c … Z1 n. The impedance elements Z1a, Z1b, Z1c … Z1n may be selectively configured as passive load elements, such as RLC circuits or current source loads.
Similarly, the second path control unit 200 is connected to the supply voltage VccInput terminal 11 and terminal switching voltage VsAnd includes at least a second main switch element SW2a and a plurality of second auxiliary switch elements SW2b, SW2c …, SW2n connected in parallel.
The second main switch element SW2a and the second auxiliary switch elements SW2b and SW2c … SW2n are respectively connected with an impedance element Z2a, Z2b and Z2c … Z2 n. According to an embodiment of the present invention, the impedance devices Z2a, Z2b, Z2c … Z2n are similar to the impedance devices Z1a, Z1b, Z1c … Z1n, which can be selectively configured with passive load devices, such as RLC circuits or current source loads.
It is believed that those skilled in the art, having ordinary knowledge and an understanding of the present invention and the technical background, will be able to make appropriate modifications and variations to the kind of impedance elements disclosed herein and the number of switching elements provided in the constituent circuits. It will be apparent to those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.
An output driver 20 is connected in series with the transition region control circuit 10 and receives an end switching voltage VsTo correspondingly generate the output bus signal VoutI.e. high voltage side output CANH or low voltage side output CANL.
To achieve the objective of the present invention, according to the embodiments of the present invention, the present invention precisely designs the plurality of switching elements in the first path control unit 100, i.e., SW1b, SW1c … SW1n, or the plurality of switching elements in the second path control unit 200, i.e., SW2b, SW2c … SW2n, to be sequentially turned on and then sequentially turned off. So as to pass through the designTerminal switching voltage VsHas multiple phases, and the transition region (phase transition) between the phases is smoothed (smooth).
Referring to fig. 5, which is a schematic diagram illustrating a bus driver module with a control circuit according to the present invention, which is controlled by at least one switch control circuit, it can be clearly understood how to effectively control the plurality of first auxiliary switch elements SW1b, SW1c … SW1n and the plurality of second auxiliary switch elements SW2b, SW2c … SW2n, referring to fig. 4 and 5.
As shown, a switch control circuit 500a is electrically connected between the input terminal 11 and the first path control unit 100. The switch control circuit 500a is composed of a pulse generator 52 and a pulse train delay circuit 54, wherein the pulse train delay circuit 54 is connected in series with the pulse generator 52. The pulse generator receives an input signal V via an input terminal 11inAnd generates a pulse signal Vp. The pulse train delay circuit 54 receives the pulse signal VpAnd generates a plurality of first control signals SW _ d1 and SW _ d2 … SW _ dn, which are used for respectively determining and controlling the on/off of the first auxiliary switch devices SW1b and SW1c … SW1 n.
For example, the first control signal SW _ d1 is connected to the first auxiliary switch element SW1b and controls the first auxiliary switch element SW1 b; the first control signal SW _ d2 is connected to the first auxiliary switch element SW1c and controls the first auxiliary switch element SW1 c; … the first control signal SW _ dn is connected to the first auxiliary switch element SW1n and controls the first auxiliary switch element SW1 n.
Similarly, the switch control circuit 500b is electrically connected between the input terminal 11 and the second path control unit 200. The switch control circuit 500b is composed of a pulse generator 52 and a pulse train delay circuit 54, wherein the pulse train delay circuit 54 is connected in series with the pulse generator 52. The pulse generator receives an input signal V via an input terminal 11inAnd generates a pulse signal Vp. The pulse train delay circuit 54 receives the pulse signal VpAnd generates a plurality of second control signals sw _ u1, sw _ u2 … sw _ un, which are connected to the first control signal busThe second control signals SW _ u1 and SW _ u2 … SW _ un are used for respectively determining and controlling the on/off of the second auxiliary switch elements SW2b and SW2c … SW2 n.
For example, the second control signal SW _ u1 is connected to the second auxiliary switch element SW2b and controls the second auxiliary switch element SW2 b; the second control signal SW _ u2 is connected to the second auxiliary switch element SW2c and controls the second auxiliary switch element SW2 c; … the second control signal SW _ un is connected to the second auxiliary switch element SW2n and controls the second auxiliary switch element SW2 n.
Basically, since the switch control circuits 500a and 500b are similar in principle, the present invention briefly takes one of them, namely the switch control circuit 500a, as an exemplary embodiment explained further below. Fig. 6 is a detailed circuit diagram of a switch control circuit 500a according to an embodiment of the invention. As shown, the pulse generator 52 includes an inverter 521, a capacitor 523, a comparator 525 AND an AND gate 527, wherein a first end of the inverter 521 is electrically connected to the input end 11 AND receives the input signal Vin. A second terminal of the inverter 521 is electrically connected to the capacitor 523. Two input contacts of the comparator 525 are connected to the capacitor 523 and a reference voltage V, respectivelyrefAND its output contact is connected to AND gate 527. The other input contact of the AND gate 527 is directly connected to the input terminal 11 for receiving the input signal Vin. By so setting, when the input signal VinAt a high voltage level, the inverter 521 will slowly discharge the capacitor 523 until its voltage charge becomes lower than the reference voltage VrefThereby causing the output of comparator 525 to transition from a high level to a low level. At this time, the output of the comparator is again compared with the input signal VinAre transmitted to an AND gate 527 in parallel to generate the pulse signal Vp。
Furthermore, since the pulse train delay circuit 54 is composed of a plurality of delay units 541, each of the delay units 541 can be a buffer, the pulse signal V is generatedpAfter being generated and transmitted to the pulse train delay circuit 54, each of the delay units 541 outputs a first control signal sw _ d1, swLd 2 … or SW dn to control the corresponding first auxiliary switching elements SW1b, SW1c …, SW1n, respectively.
In other words, the first control signal SW _ d1 is connected to the first auxiliary switch element SW1b and controls the first auxiliary switch element SW1 b; the first control signal SW _ d2 is connected to the first auxiliary switch element SW1c and controls the first auxiliary switch element SW1 c; … the first control signal SW _ dn is connected to the first auxiliary switch element SW1n and controls the first auxiliary switch element SW1 n.
Similarly, the switch control circuit 500b is composed of the pulse generator 52 and the pulse train delay circuit 54, so that the pulse generator 52 generates the pulse signal VpAfter the signals are transmitted to the pulse train delay circuit 54, each of the delay units 541 can also correspondingly output a second control signal SW _ u1, SW _ u2 … or SW _ un to control the corresponding second auxiliary switch devices SW2b and SW2c … SW2n, respectively.
That is, the generated second control signal SW _ u1 is connected to the second auxiliary switch element SW2b and controls the second auxiliary switch element SW2 b; the generated second control signal SW _ u2 is connected to the second auxiliary switch element SW2c and controls the second auxiliary switch element SW2 c; … is connected to the second slave switch element SW2n and controls the second slave switch element SW2 n.
Please refer to fig. 7, which is a diagram illustrating waveforms of the voltage signals of the switch control circuit module shown in fig. 6 according to the present invention when n is 4. As shown in fig. 7, it is obvious that, when the switch control circuit architecture disclosed by the present invention is applied, the input signal V is inputinAt a high voltage level, based on the functions of the pulse generator 52 and the plurality of delay units 541, a sequence of first control signals SW _ d1, SW _ d2, SW _ d3 and SW _ d4 are generated, which sequentially turn on the first auxiliary switch elements SW1b, SW1c, SW1d and SW1 e. After a period of time, the first auxiliary switch elements SW1b, SW1c, SW1d and SW1e are turned off sequentially.
Therefore, please refer to FIG. 4 together, when the input signal V is inputtedinWhen input via the input terminal 11 and has a high voltage level, i.e. when the input is atSignal VinWhen the logic 0 is changed to the logic 1, the first main switch element SW1a is turned on (the second main switch element SW2a is turned off), so that the first path control unit 100 in the transition region control circuit is turned on.
Thereafter, as disclosed in the foregoing fig. 7, based on the generation of the plurality of first control signals SW _ d1, SW _ d2 … SW _ dn, the first auxiliary switch elements SW1b, SW1c … SW1n are turned on, and the terminal switching voltage V is enabledsWill be from VccStarts to drop significantly, this time defined as the first phase state. Subsequently, as shown in the waveform diagram of fig. 7, since the first auxiliary switching elements SW1b and SW1c … SW1n are sequentially turned off again, the end-switching voltage V is mainly a single current path formed by the first main switching element SW1a and the impedance element Z1a thereofsThe voltage level of the first phase state is continuously decreased to the ground voltage with a slower voltage drop difference, and the first phase state is converted into the second phase state.
On the other hand, when the signal V is inputtedinIs input via an input terminal 11 and is converted from a high voltage level to a low voltage level, i.e. when the input signal V isinWhen the logic 1 is changed to logic 0, in this case, the second main switch element SW2a is turned on (at this time, the first main switch element SW1a is turned off), so that the second path control unit 200 in the transition region control circuit is turned on.
Similar to the operation principle of the first path control unit 100, the second subsidiary switching elements SW2b, SW2c …, SW2n are turned on based on the plurality of second control signals SW _ u1, SW _ u2 … SW _ un generated by the switch control circuit 500b, and in this case, the end-switch voltage V is turned onsWill ramp significantly from ground voltage, which is defined as the first phase state. Subsequently, the second subsidiary switch elements SW2b, SW2c …, SW2n are sequentially turned off again, so that the end-switching voltage V is mainly only the single current path formed by the second main switch element SW2a and the impedance element Z2a thereofsThe voltage level of (1) will continue to rise with a slower voltage and return to VccLevel of the same phase from the first phase stateTo a second phase state. From this point of view, the circuit architecture disclosed in the present invention is applied to switch the voltage VsUndergoes two phase states and forms a phase transition region between the two phase states.
In the following description, the present invention will verify that, by applying the technical solution disclosed in the present invention, a better smoothing (smoothening) can be achieved in the phase transition region (phasetransition) between the first phase state and the second phase state.
Fig. 8 is a circuit diagram of a bus driver module with a control circuit according to another embodiment of the invention. Compared with the circuit diagram of fig. 4 in which a plurality of auxiliary switch elements are provided, in fig. 8, only a single first auxiliary switch element SW1b and a single second auxiliary switch element SW2b are provided in the first path control unit and the second path control unit, respectively, as an embodiment, the simulation results are provided as follows.
As shown in fig. 8, when only one auxiliary switching element is provided in each of the first path control unit and the second path control unit during the switching of the first phase state and the second phase state, it can be understood that if the gate voltage of the transistor of the auxiliary switching element can be effectively controlled by a slope control mechanism, for example, a slowly increasing and slowly decreasing gate input signal, a smooth phase transition can be successfully achieved. It is noted, however, that if the transistor of the auxiliary switching element has a process variation, such as: when the operation window of the MOSFET is changed from T-T to F-S or S-F, the symmetry of the output signals CANH and CANL is greatly affected. Please refer to fig. 9 and 10, which are schematic diagrams illustrating the circuit structure of fig. 8, wherein the bus signal V is outputtedoutThe waveform diagram includes a high-voltage terminal CANH and a low-voltage terminal CANL, wherein the mosfet of the auxiliary switch device in fig. 8 has the above-mentioned process variation. In the experimental simulation results, the process parameters (MOSFETs) of the MOSFET are shown by solid lines in the T-T interval; and is shown in dotted lineThe process parameters of the MOSFET fall within the F-S interval. From these experimental simulation results, it can be seen that when the MOSFET enters the F-S region based on the process variation, a large and unavoidable common mode noise (common mode noise) is generated as seen by the square region in fig. 10.
On the other hand, FIG. 11 shows the terminal switching voltage V in the circuit architectures shown in FIG. 4 and FIG. 8sA comparative graph of (a). FIG. 12 shows the circuit configuration shown in FIGS. 4 and 8, in which the bus signal V is outputtedoutThe comparison graph comprises a high-voltage end output CANH and a low-voltage end output CANL. The voltage waveform results of fig. 4 (with multiple auxiliary switch devices SW1b, SW1c … SW1n and SW2b, SW2c … SW2n) are shown by solid lines, and the voltage waveform results of fig. 8 (with only a single first auxiliary switch device SW1b and a single second auxiliary switch device SW2b) are shown by dashed lines.
From these simulation results, it is obvious that when only a single auxiliary switching element is provided in the circuit configuration during switching of the first and second phase states, the transition point of the transition will be generally too sharp as indicated by the dashed line. In addition, a bus signal V is outputoutThe voltage signals including the high-voltage terminal CANH and the low-voltage terminal CANL cannot be smoothed, which may cause electrical loss and/or excessive common mode noise.
On the contrary, if a plurality of auxiliary switching elements are provided in the circuit structure, the transition point of the transition can be greatly smoothed during the switching process of the first and second phase states, as shown by the solid lines in fig. 11 and 12. And outputs a bus signal VoutThe controller local area network bus application system comprises a high-voltage end outputting CANH and a low-voltage end outputting CANL, and can also be smooth in a transition region, so that the controller local area network bus application system is quite helpful for accelerating transition among multiple phases and smoothing a phase transition region. It is therefore an object of the present invention that the DC levels of the high side output CANH and the low side output CANL can be successfully controlled to achieve the precise control thereof, and the object of the present invention is achieved.
In view of at least one of the above teachings, it is believed that the transition region control circuit disclosed herein is characterized by providing a plurality of auxiliary switching elements and precisely controlling the sequential on and off of the auxiliary switching elements, thereby controlling the voltage of the output signal to transition from the first phase state to the second phase state, and smoothing the phase transition region. Under the circumstances, it is obvious that the present invention not only can realize the smoothing of the transition region, but also can achieve lower common mode noise and better EMI protection performance. Therefore, by adopting the circuit architecture disclosed by the invention, the direct-current voltage level of the output voltage can be effectively and stably controlled, and the circuit architecture can be widely applied to a controller area network bus and other industrial application systems, so that the circuit architecture provides an excellent transition region control circuit architecture when switching between a main mode and a recessive mode of circuit operation.
According to the circuit architecture disclosed by the invention, the circuit architecture can be applied to a high-voltage end to generate a high-voltage end output CANH; or can be applied to a low voltage terminal to generate the low voltage terminal output CANL.
The present invention thus demonstrates the disclosed circuit architecture with superior performance compared to conventional techniques, as compared to prior designs. Moreover, it is believed that, according to the technical features disclosed in the present invention, a more direct, effective and highly competitive technical solution is provided for the application fields of various chip designs and industrial developments in the future, and the present invention has remarkable industrial applicability and market competitiveness for the industrial development in the future.
From the foregoing, it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (20)
1. A bus driver module with a control circuit electrically connected to a controller area network bus and generating an output bus signal, comprising:
the transition area control circuit is electrically connected with an input end and comprises a first path control unit and a second path control unit, wherein the first path control unit and the second path control unit are arranged in parallel to generate one-end switching voltage, and the first path control unit and the second path control unit respectively comprise a plurality of switch elements; and
an output driver connected in series with the transition region control circuit and receiving the end switching voltage to output the output bus signal correspondingly;
when an input signal is input through the input end, the first path control unit or the second path control unit is selectively conducted, and the plurality of switch elements in the first path control unit or the second path control unit are sequentially turned on and off, so that the end switching voltage has a smooth phase transition region.
2. The bus driver module as claimed in claim 1, wherein the first path control unit is connected between the input terminal, the terminal switching voltage and a ground terminal, and comprises at least a first main switch element and a plurality of first auxiliary switch elements, the plurality of first auxiliary switch elements being connected in parallel.
3. The bus driver module with control circuit of claim 2, wherein the first main switching element and each of the first auxiliary switching elements are respectively connected to an impedance element.
4. The bus driver module as claimed in claim 2, wherein when the input signal is converted from logic 0 to logic 1, the first main switch element is turned on first to turn on the first path control unit, and then the plurality of first auxiliary switch elements are sequentially turned on again to change the voltage value of the end switching voltage in a first phase state.
5. The bus driver module of claim 4, wherein after the first phase state, the plurality of first auxiliary switching elements are sequentially turned off such that the voltage value of the end-switching voltage changes from the first phase state to a second phase state, and the phase transition region between the first phase state and the second phase state is smooth.
6. The bus driver module of claim 1, wherein the second path control unit is connected between a supply voltage, the input terminal and the terminal switching voltage and includes at least a second main switching element and a plurality of second auxiliary switching elements, the plurality of second auxiliary switching elements being connected in parallel with each other.
7. The bus driver module of claim 6, wherein the second main switching element and each of the second auxiliary switching elements are respectively connected to an impedance element.
8. The bus driver module as claimed in claim 6, wherein when the input signal is converted from logic 1 to logic 0, the second main switch element is turned on first, so that the second path control unit is turned on, and then the plurality of second auxiliary switch elements in the second path control unit are sequentially turned on again, so that the voltage value of the end switching voltage is changed in a first phase state.
9. The bus driver module as claimed in claim 8, wherein after the first phase state, the plurality of second auxiliary switching elements in the second path control unit are sequentially turned off such that the voltage value of the end switching voltage is changed from the first phase state to a second phase state, and the phase transition region between the first phase state and the second phase state is smooth.
10. The bus driver module of claim 1, wherein the output bus signal for the CAN bus is a high side output or a low side output.
11. The bus driver module of claim 2, further comprising at least one switch control circuit connected between the input terminal and the first path control unit, the switch control circuit generating a plurality of first control signals, each first control signal determining an on and off state of a corresponding first auxiliary switch element.
12. The bus driver module as claimed in claim 11, wherein the switch control circuit comprises a pulse generator and a pulse train delay circuit connected in series with the pulse generator, the pulse generator receives the input signal and generates a pulse signal, and the pulse train delay circuit receives the pulse signal and outputs the first control signals for controlling the first auxiliary switch elements.
13. The bus driver module of claim 12, wherein the pulse train delay circuit comprises a plurality of delay units, each of which generates a first control signal to control its corresponding first auxiliary switching element.
14. The bus driver module with control circuit of claim 13, wherein the delay unit is a buffer.
15. The bus driver module with control circuitry of claim 12, wherein the pulse generator comprises:
an inverter having a first terminal and a second terminal electrically connected to the input terminal;
a capacitor connected between the second end of the inverter and the ground terminal;
a comparator having an output node and two input nodes, wherein the two input nodes are respectively connected to the second end of the inverter and a reference voltage; and
an AND gate having two input contacts respectively connected to the output contact AND the input terminal of the comparator for generating the pulse signal.
16. The bus driver module of claim 6, further comprising at least one switch control circuit connected between the input terminal and the second path control unit, the switch control circuit generating a plurality of second control signals, each second control signal determining the on and off states of a corresponding second auxiliary switch element.
17. The bus driver module of claim 16, wherein the switch control circuit comprises a pulse generator and a pulse train delay circuit connected in series with the pulse generator, the pulse generator receiving the input signal and generating a pulse signal, the pulse train delay circuit receiving the pulse signal and outputting the second control signals for controlling the second plurality of auxiliary switching elements.
18. The bus driver module of claim 17, wherein the pulse train delay circuit comprises a plurality of delay units, each of which generates a second control signal to control its corresponding second auxiliary switching element.
19. The bus driver module with control circuitry of claim 18, wherein the delay element is a buffer.
20. The bus driver module with control circuitry of claim 17, wherein the pulse generator comprises:
an inverter having a first terminal and a second terminal electrically connected to the input terminal;
a capacitor connected between the second end of the inverter and the ground terminal;
a comparator having an output node and two input nodes, wherein the two input nodes are respectively connected to the second end of the inverter and a reference voltage; and
an AND gate having two input contacts respectively connected to the output contact AND the input terminal of the comparator for generating the pulse signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/794,453 US10892759B1 (en) | 2020-02-19 | 2020-02-19 | Bus driver module with controlled circuit and transition controlled circuit thereof |
| US16/794,453 | 2020-02-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111726111A true CN111726111A (en) | 2020-09-29 |
| CN111726111B CN111726111B (en) | 2024-03-22 |
Family
ID=72566243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010512220.8A Active CN111726111B (en) | 2020-02-19 | 2020-06-08 | Bus driver module with control circuit |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10892759B1 (en) |
| CN (1) | CN111726111B (en) |
| TW (1) | TWI752543B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770824B (en) * | 2020-12-07 | 2022-07-11 | 晶焱科技股份有限公司 | Bus driving device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102020127165A1 (en) * | 2020-10-15 | 2022-04-21 | Infineon Technologies Ag | FIELDBUS DRIVER CIRCUIT |
| US11853243B2 (en) * | 2021-11-05 | 2023-12-26 | Semiconductor Components Industries, Llc | Capacitively-coupled multi-domain distributed driver |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117614A (en) * | 1993-11-29 | 1996-02-28 | 富士通株式会社 | Electronic system, semiconductor integrated circuit and termination device |
| US5511229A (en) * | 1991-09-13 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths |
| CN1574639A (en) * | 2003-05-23 | 2005-02-02 | 株式会社瑞萨科技 | Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit |
| CN101789780A (en) * | 2009-01-23 | 2010-07-28 | 恩益禧电子股份有限公司 | Impedance adjusting circuit |
| US20150145563A1 (en) * | 2012-06-27 | 2015-05-28 | Freescale Semiconductor, Inc. | Differential line driver circuit and method therefor |
| CN104731742A (en) * | 2013-12-18 | 2015-06-24 | 英飞凌科技股份有限公司 | Bus driver circuit with improved transition speed |
| US20160196230A1 (en) * | 2015-01-07 | 2016-07-07 | Infineon Technologies Ag | System and Method for a Low Emission Network |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999057810A2 (en) | 1998-05-06 | 1999-11-11 | Koninklijke Philips Electronics N.V. | Can bus driver with symmetrical differential output signals |
| TW440767B (en) * | 1998-06-02 | 2001-06-16 | Fujitsu Ltd | Method of and apparatus for correctly transmitting signals at high speed without waveform distortion |
| US6570931B1 (en) * | 1999-12-31 | 2003-05-27 | Intel Corporation | Switched voltage adaptive slew rate control and spectrum shaping transmitter for high speed digital transmission |
| US6597233B2 (en) * | 2001-05-25 | 2003-07-22 | International Business Machines Corporation | Differential SCSI driver rise time and amplitude control circuit |
| DE60206146T2 (en) * | 2002-06-28 | 2006-01-26 | Freescale Semiconductor, Inc., Austin | A communication device having a driver for controlling a communication line using a switched signal at a controlled slew rate |
| US7595674B1 (en) * | 2005-05-09 | 2009-09-29 | Cypress Semiconductor Corporation | Universal serial bus (USB) driver circuit, system, and method |
| US7253655B2 (en) * | 2005-09-01 | 2007-08-07 | Micron Technology, Inc. | Output driver robust to data dependent noise |
| US7307447B2 (en) * | 2005-10-27 | 2007-12-11 | International Business Machines Corporation | Self series terminated serial link transmitter having segmentation for amplitude, pre-emphasis, and slew rate control and voltage regulation for amplitude accuracy and high voltage protection |
| US7902875B2 (en) * | 2006-11-03 | 2011-03-08 | Micron Technology, Inc. | Output slew rate control |
| CN102177687B (en) | 2008-10-09 | 2014-04-23 | Nxp股份有限公司 | Bus driver circuit |
| DE102009000697B4 (en) * | 2009-02-06 | 2012-12-06 | Infineon Technologies Ag | Driver circuit for a two-wire line and method for generating two output currents for a two-wire line |
| US8742814B2 (en) * | 2009-07-15 | 2014-06-03 | Yehuda Binder | Sequentially operated modules |
| US9559779B2 (en) * | 2014-02-10 | 2017-01-31 | Elenion Technologies, Llc | Distributed traveling-wave mach-zehnder modulator driver |
| US9467303B2 (en) * | 2014-09-26 | 2016-10-11 | Linear Technology Corporation | Controller area network bus transmitter with complementary source follower driver |
| DE102018104732B3 (en) * | 2018-03-01 | 2019-02-21 | Infineon Technologies Ag | BUS DRIVER CIRCUIT |
-
2020
- 2020-02-19 US US16/794,453 patent/US10892759B1/en active Active
- 2020-06-08 CN CN202010512220.8A patent/CN111726111B/en active Active
- 2020-07-03 TW TW109122666A patent/TWI752543B/en active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5511229A (en) * | 1991-09-13 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths |
| CN1117614A (en) * | 1993-11-29 | 1996-02-28 | 富士通株式会社 | Electronic system, semiconductor integrated circuit and termination device |
| CN1574639A (en) * | 2003-05-23 | 2005-02-02 | 株式会社瑞萨科技 | Clock generation circuit capable of setting or controlling duty ratio of clock signal and system including clock generation circuit |
| CN101789780A (en) * | 2009-01-23 | 2010-07-28 | 恩益禧电子股份有限公司 | Impedance adjusting circuit |
| US20100188116A1 (en) * | 2009-01-23 | 2010-07-29 | Nec Electronics Corporation | Impedance adjusting circuit |
| US20150145563A1 (en) * | 2012-06-27 | 2015-05-28 | Freescale Semiconductor, Inc. | Differential line driver circuit and method therefor |
| CN104731742A (en) * | 2013-12-18 | 2015-06-24 | 英飞凌科技股份有限公司 | Bus driver circuit with improved transition speed |
| US20160196230A1 (en) * | 2015-01-07 | 2016-07-07 | Infineon Technologies Ag | System and Method for a Low Emission Network |
Non-Patent Citations (1)
| Title |
|---|
| 唐兴刚;贺克军;王丽;李传南;: "一款CAN总线收发器芯片的电路设计", 微电子学与计算机, no. 05, pages 131 - 135 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI770824B (en) * | 2020-12-07 | 2022-07-11 | 晶焱科技股份有限公司 | Bus driving device |
| US11462900B2 (en) | 2020-12-07 | 2022-10-04 | Amazing Microelectronic Corp. | Bus driving device |
Also Published As
| Publication number | Publication date |
|---|---|
| US10892759B1 (en) | 2021-01-12 |
| TWI752543B (en) | 2022-01-11 |
| CN111726111B (en) | 2024-03-22 |
| TW202133554A (en) | 2021-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111726111B (en) | Bus driver module with control circuit | |
| CN110224951B (en) | Bus driver circuit | |
| EP3001564B1 (en) | Controller area network bus transmitter with complementary source follower driver | |
| CN108023798B (en) | CAN module and method thereof | |
| US8324935B2 (en) | Bus driver circuit | |
| CN102763387B (en) | Signal transmission device | |
| JP6337110B2 (en) | Bus system subscriber station and method for reducing radiation associated with conductors in a bus system | |
| JPH08223014A (en) | Comparator circuit decreasing through current of power switch | |
| JP7042899B2 (en) | Vibration reduction units for bus systems and methods to reduce vibration tendencies during transitions between different bit states | |
| US8624655B2 (en) | Level shifter circuit and gate driver circuit including the same | |
| JP2021013143A (en) | Differential signal transmission circuit | |
| US7005891B2 (en) | Data transmission circuit for universal serial bus system | |
| US20150295738A1 (en) | Communication system | |
| US6657460B2 (en) | Spatially filtered data bus drivers and receivers and method of operating same | |
| US20230412431A1 (en) | Multi-channel digital isolator with integrated configurable pulse width modulation interlock protection | |
| JP3850470B2 (en) | Slew rate control drive circuit | |
| EP0980144B1 (en) | Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage and temperature | |
| EP2487795A2 (en) | Output circuit, system including output circuit, and method of controlling output circuit | |
| CN111771335A (en) | Level shifter circuit | |
| KR19990008121A (en) | BTL output amplifier | |
| US6366125B1 (en) | Digital output circuit | |
| US11515876B2 (en) | Driver for a shared bus, in particular a LIN bus | |
| EP0518625A2 (en) | Waveform synthesizing circuit | |
| US6329834B1 (en) | Reduction of switching noise in integrated circuits | |
| JP2010130504A (en) | Terminating resistor device, semiconductor device, and method for controlling terminating resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |