CN111726052A - Drive control circuit and air conditioner - Google Patents
Drive control circuit and air conditioner Download PDFInfo
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- CN111726052A CN111726052A CN201910213335.4A CN201910213335A CN111726052A CN 111726052 A CN111726052 A CN 111726052A CN 201910213335 A CN201910213335 A CN 201910213335A CN 111726052 A CN111726052 A CN 111726052A
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- 238000012545 processing Methods 0.000 claims abstract description 194
- 238000000034 method Methods 0.000 claims abstract description 57
- 230000008569 process Effects 0.000 claims abstract description 50
- 238000012937 correction Methods 0.000 claims abstract description 48
- 230000004044 response Effects 0.000 claims abstract description 22
- 230000015654 memory Effects 0.000 claims description 62
- 230000006870 function Effects 0.000 claims description 44
- 238000001514 detection method Methods 0.000 claims description 24
- 230000004907 flux Effects 0.000 claims description 9
- 230000002159 abnormal effect Effects 0.000 claims description 5
- 230000001960 triggered effect Effects 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000005347 demagnetization Effects 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 238000000638 solvent extraction Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
- H02P29/02—Providing protection against overload without automatic interruption of supply
- H02P29/024—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P29/00—Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors
- H02P29/02—Providing protection against overload without automatic interruption of supply
- H02P29/024—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load
- H02P29/027—Detecting a fault condition, e.g. short circuit, locked rotor, open circuit or loss of load the fault being an over-current
Abstract
The invention provides a drive control circuit and an air conditioner, wherein the drive control circuit comprises: a first processing core configured to perform drive control of the motor assembly; a second processing core; the second processing core is configured to drive and control the power factor correction module, and the processing process of the first processing core is independent of the processing process of the second processing core; and the internal pin is coupled and connected to the first processing core and the second processing core, wherein if the first processing core detects the motor assembly fault, the internal pin is enabled, the internal pin in the enabled state triggers the second processing core to execute an interrupt process, and the interrupt process is configured as an emergency stop power factor correction module. Through the technical scheme of the invention, the operation processing efficiency of the drive control circuit is improved, the reliability of the protection of the motor assembly is also improved, and the response time of the emergency stop power factor correction module is shortened.
Description
Technical Field
The invention relates to the technical field of drive control circuits, in particular to a drive control circuit and an air conditioner.
Background
At present, a microcontroller commonly used by a household variable frequency air conditioner is a single chip (processing core) or a double chip (processing core), the single chip (processing core) can complete all functions of the variable frequency air conditioner system, the double chip (processing core) jointly completes all functions of the variable frequency air conditioner system by two chips (processing cores), and the two chips (processing cores) transmit data through a communication protocol so as to cooperatively complete the functions of the variable frequency air conditioner system.
Wherein, each chip in the double-chip (processing core) can process the trouble respectively, and the trouble is transmitted through the communication between two chips, and then actions such as reporting an obstacle, clearing the trouble, shutting down and restarting are accomplished.
In the related art, for an inverter air conditioning system controlled by a dual chip (processing core), when a slave chip (processing core) fails, the failure is transmitted to a shared register, and then the master chip (processing core) reads the failure in the shared register, and then the master chip (processing core) responds to the failure, and this failure handling scheme has at least the following technical problems:
(1) various faults transmitted between the two chips (processing cores) need to be transferred through a shared register, and long transmission time and read-write time are needed, so that the processing efficiency of the double chips on the faults is low.
(2) When the compressor fails, the PFC (Power Factor Correction) module needs to be timely protected, and if the response time is long, the dc bus voltage rises rapidly, which may cause impact or damage to the PFC, which may seriously affect the reliability of the air conditioner.
Disclosure of Invention
The present invention has been made to solve at least one of the above-mentioned problems occurring in the prior art or the related art.
To this end, an object of the present invention is to provide a drive control circuit.
Another object of the present invention is to provide an air conditioner.
To achieve the above object, according to an embodiment of a first aspect of the present invention, there is provided a drive control circuit including: a first processing core configured to drive control a motor assembly; a second processing core; the second processing core is configured to drive and control the power factor correction module, and the processing process of the first processing core is independent of the processing process of the second processing core; an internal pin coupled to the first processing core and the second processing core, wherein if the first processing core detects the motor component failure, the internal pin is enabled, and the internal pin in an enabled state triggers the second processing core to execute an interrupt process, and the interrupt process is configured to scram the power factor correction module.
According to the drive control circuit provided by the embodiment of the invention, the internal pin is coupled and connected to the first processing core and the second processing core, and the main function is that if the first processing core detects that the motor component is in fault, the internal pin is enabled, the internal pin in the enabled state triggers the second processing core to execute an interrupt process, the interrupt process is configured to suddenly stop the power factor correction module, namely, the interrupt process is executed in micron-sized response time, if the first processing core detects that the motor component is in fault, the PFC can be suddenly stopped, and further, the impact of sudden stop of the motor component on the PFC is reduced, and in addition, the efficiency and the reliability of fault processing on an air conditioner are effectively improved while the operating efficiency and the isolation of the dual processing cores are ensured.
For the air conditioner device, after the second processing core is powered on to operate, the PFC and the capacitor element are controlled to be charged, and after the charging voltage of the capacitor element reaches the starting voltage, the first processing core is triggered to operate, and at this time, the first processing core can drive the motor assembly to operate, and the first processing core and the second processing core may be a processor, a controller, a logic operation device, an embedded device, and the like, but are not limited thereto.
Specifically, the processing cores are usually two-bit, four-bit, eight-bit, sixteen-bit, thirty-two-bit or sixty-four-bit, and therefore, if the first processing core notifies the second processing core of a fault through a general data reading and writing manner, the multi-bit fault data needs to be written into the shared memory first, and then read and respond by the second memory, so that the response time of two times of reading and writing is far longer than that of the internal pin scram power factor correction module, and further, the reliability of the PFC in the dual-processing core operation mode is improved.
The drive control circuit according to the above embodiment of the present invention optionally further includes: and a shared memory coupled to the first processing core and the second processor, wherein the data transmitted to the shared memory by the first processing core can be read by the second processor, and the data transmitted to the shared memory by the second processing core can be read by the first processor.
According to the drive control circuit of the embodiment of the invention, the first processor and the second processor perform data interaction through the shared memory, so that the first processor and the second processor can execute processes independently, data isolation is realized, and the first processor and the second processor can store and read and write data in a partitioning manner, thereby effectively improving the computational efficiency and reliability of a dual-core processing scheme.
According to the drive control circuit of the above embodiment of the present invention, optionally, the shared memory includes a nonvolatile memory.
According to the driving control circuit of the embodiment of the invention, the memory (internal memory) serves as an important bridge between the controller (i.e. the processing core) and the hard disk, which provides faster read/write performance, but if the memory is suddenly powered down, the data stored in the memory may be lost, so that, since the first processor and the second processor are both coupled to the shared memory, and the structure of the Nonvolatile memory is usually a "battery + memory chip", in case of power failure, the battery supplies power to the memory chip, and can keep the data in the memory chip for 72 hours, the Nonvolatile memory is adopted in the present application to overcome the problem of sudden power down, wherein the Nonvolatile memory (NVM) is divided into two types, namely block addressing and byte addressing, and in addition, the commonly used byte-addressed Nonvolatile memory mainly includes a phase change memory, and a phase change memory, Resistive random access memories, spin torque memories, and the like, but are not limited thereto.
According to the drive control circuit of the above embodiment of the present invention, optionally, the second processing core is further provided with a main control unit, and the main control unit can perform drive control on the motor assembly, and if the first processing core detects that the motor assembly is out of order, the motor assembly is controlled to stop operating or power off, and a fault type corresponding to the motor assembly is determined through analysis.
According to the drive control circuit provided by the embodiment of the invention, the main control unit is arranged in the second processing core, the main control unit is mainly used for controlling the operation of the PFC and triggering the operation of the first processing core, the operation capacity of the second processing core is usually stronger than that of the first processor, and when the first processing core is in a fault or is stopped, the main control unit can analyze the operation parameters and the fault reason of the first processing core and restart and initialize the first processing core.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the detection portion corresponding to the motor component, the first processing core generates a fault identifier corresponding to the fault type and transmits the fault identifier to the shared memory, and the second processing core can read the fault identifier from the shared memory.
According to the drive control circuit of the embodiment of the invention, by connecting the detection pin of the first processing core to the detection part of the motor assembly and generating the corresponding fault identifier, the second processing core can read the fault identifier through the shared memory, and further perform corresponding protection operations according to the fault identifier, such as cutting off an alternating current signal, controlling a power switch to be turned off, and performing operations such as surge absorption.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the coil of the motor assembly, and/or a sense pin of the first processing core is connected to a drive circuit of the motor assembly, when the first processing core runs the first interrupt function, if the fault type is determined to correspond to the hardware overcurrent fault through analysis, generating a first-level interrupt signal, enabling the internal pin by the first-level interrupt signal, triggering the second processing core to execute a corresponding interrupt process so as to scram the power factor correction module, the hardware overcurrent fault is determined by a load signal of a coil of the motor assembly or a driving signal of the motor assembly, and the numerical range of the response time of the power factor correction module is suddenly stopped by adopting the first interrupt function is 0.5 us-16 us.
According to the driving control circuit of the embodiment of the invention, when the first processing core runs a first interrupt function, if it is analytically determined that the fault type corresponds to a hardware overcurrent fault, a first-stage interrupt signal is generated, the first-stage interrupt signal enables the internal pin to trigger the second processing core to execute a corresponding interrupt process to scram the Power factor correction Module, wherein the hardware overcurrent fault is determined by a load signal of a coil of the motor assembly or a driving signal of the motor assembly, a response time for scramming the Power factor correction Module by using the first interrupt function is in a range of 0.5us to 16us, generally speaking, the overcurrent fault most easily causes circuit elements to be burned out, especially a PFC and an IPM (Intelligent Power Module), the first-stage interrupt signal can control the PFC or a Power switching device in the IPM to stop working within 0.5us to 16us, the method controls the PFC and the IPM to suddenly stop, so that the current impact of sudden stop of the motor assembly on the PFC and the IPM is reduced, and the reliability of the PFC and the IPM is improved.
The IPM integrates a power switch device and a high-voltage driving circuit, and is internally provided with fault detection circuits such as overvoltage, overcurrent and overheat, on one hand, the IPM receives a control signal sent by the first processing core to drive a subsequent circuit to work, and on the other hand, the IPM sends a state detection signal of the system back to the first processing core. Compared with the traditional discrete scheme, the IPM gains a bigger and bigger market with the advantages of high integration degree, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device in the fields of frequency conversion speed regulation, metallurgical machinery, electric traction, servo drive, frequency conversion household appliances and the like.
In summary, the hardware overcurrent fault is usually an IPM overcurrent fault or a demagnetization fault.
According to the drive control circuit in the foregoing embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the data pin of the main control unit, when the first processing core runs a second interrupt function, if it is determined through analysis that the fault type corresponds to a software fault, a second-level interrupt signal is generated, the second-level interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process, so as to scram the power factor correction module, where the software fault is a data signal in the running process of the main control unit, and a numerical range of response time for scramming the power factor correction module using the second interrupt function is 3us to 35 us.
According to the drive control circuit of the embodiment of the invention, when the first processing core runs the second interrupt function, if the fault type is determined to correspond to the software fault through analysis, the second-level interrupt signal is generated, the second-level interrupt signal enables the internal pin to trigger the second processing core to execute the corresponding interrupt process, so as to stop the power factor correction module urgently, wherein the software fault is a data signal in the running process of the main control unit, the numerical range of the response time of stopping the power factor correction module urgently by adopting the second interrupt function is 3 us-35 us, the software fault is a fault generated when the first processing core executes a software code process, the software code can realize torque compensation and/or rotating speed compensation on the motor component, calculate the phase current and calculate the demagnetization time of the motor component, detecting whether the motor assembly is over-temperature, calculating the operation pressure of the motor assembly, and the like, but not limited thereto, so that when a software fault occurs, the normal operation of the motor assembly may be affected, but the motor assembly is not affected in general, and therefore, the priority of the second-stage interrupt signal may be set to be lower than the priority of the first-stage interrupt signal.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the driving component of the motor assembly, when the first processing core runs a third interrupt function, if it is analytically determined that the fault type corresponds to an operation fault, a third-stage interrupt signal is generated, the third-stage interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process to scram the power factor correction module, wherein the operation fault includes at least one of a locked rotor fault, a flux fault, a phase failure fault, an overvoltage fault and an undervoltage fault, and a response time of the power factor correction module is scrammed in a range from 13us to 1013us by using the third interrupt function.
According to the drive control circuit of the embodiment of the invention, when the first processing core runs a third interrupt function, if the fault type is analytically determined to correspond to an operation fault, a third-stage interrupt signal is generated, the third-stage interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process so as to scram the power factor correction module, wherein the operation fault comprises at least one of a locked rotor fault, a magnetic flux fault, a phase failure fault, an overvoltage fault and an undervoltage fault, and the numerical range of response time for scramming the power factor correction module by using the third interrupt function is 13 us-1013 us.
When the motor winding is cooled to normal working condition temperature, a relay on the input side of a rectifier module is closed, but the motor cannot be started, so that the motor is locked, and the reason of locked rotor-thermal protection-locked rotor is generated.
In addition, flux failure mainly refers to abnormal magnetic flux of the coil of the motor assembly, which may cause overheating or insufficient power of the motor assembly.
In summary, the third level interrupt signal reflects abnormal operation of the motor assembly, and the third interrupt function includes a function in the main cycle, and the third level interrupt signal may have a lower priority than the second level interrupt signal.
According to an embodiment of the second aspect of the present invention, there is also provided an air conditioner including: the above any one of the above technical solutions defines a drive control circuit; and the motor assembly is connected to the drive control circuit, the drive control circuit is used for driving and controlling the motor assembly to operate, and the drive control circuit is also used for detecting whether the motor assembly has faults or not.
The air conditioner according to the embodiment of the present invention has all the technical effects of the above-mentioned driving control circuit, and will not be described herein again.
According to the drive control circuit of the above embodiment of the present invention, optionally, the motor assembly includes a fan and/or a compressor.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 shows a schematic block diagram of a drive control circuit according to one embodiment of the present invention;
FIG. 2 shows a schematic block diagram of a drive control circuit according to another embodiment of the present invention;
FIG. 3 illustrates a topological schematic of a bus circuit of the electric machine assembly according to another embodiment of the present invention;
fig. 4 shows a flow diagram of a method performed by the drive control circuit according to another embodiment of the invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.
A drive control circuit according to an embodiment of the present invention is specifically described below with reference to fig. 1 to 4.
Fig. 1 shows a schematic block diagram of a drive control circuit according to an embodiment of the present invention.
As shown in fig. 1, a drive control circuit according to an embodiment of the present invention includes: a first processing core configured to drive control a motor assembly; a second processing core; the second processing core is configured to drive and control the power factor correction module, and the processing process of the first processing core is independent of the processing process of the second processing core; an internal pin coupled to the first processing core and the second processing core, wherein if the first processing core detects the motor component failure, the internal pin is enabled, and the internal pin in an enabled state triggers the second processing core to execute an interrupt process, and the interrupt process is configured to scram the power factor correction module.
According to the drive control circuit provided by the embodiment of the invention, the internal pin is coupled and connected to the first processing core and the second processing core, and the main function is that if the first processing core detects that the motor component is in fault, the internal pin is enabled, the internal pin in the enabled state triggers the second processing core to execute an interrupt process, the interrupt process is configured to suddenly stop the power factor correction module, namely, the interrupt process is executed in micron-sized response time, if the first processing core detects that the motor component is in fault, the PFC can be suddenly stopped, and further, the impact of sudden stop of the motor component on the PFC is reduced, and in addition, the efficiency and the reliability of fault processing on an air conditioner are effectively improved while the operating efficiency and the isolation of the dual processing cores are ensured.
For the air conditioner device, after the second processing core is powered on to operate, the PFC and the capacitor element are controlled to be charged, and after the charging voltage of the capacitor element reaches the starting voltage, the first processing core is triggered to operate, and at this time, the first processing core can drive the motor assembly to operate, and the first processing core and the second processing core may be a processor, a controller, a logic operation device, an embedded device, and the like, but are not limited thereto.
Specifically, the processing cores are usually two-bit, four-bit, eight-bit, sixteen-bit, thirty-two-bit or sixty-four-bit, and therefore, if the first processing core notifies the second processing core of a fault through a general data reading and writing manner, the multi-bit fault data needs to be written into the shared memory first, and then read and respond by the second memory, so that the response time of two times of reading and writing is far longer than that of the internal pin scram power factor correction module, and further, the reliability of the PFC in the dual-processing core operation mode is improved.
The drive control circuit according to the above embodiment of the present invention optionally further includes: and a shared memory coupled to the first processing core and the second processor, wherein the data transmitted to the shared memory by the first processing core can be read by the second processor, and the data transmitted to the shared memory by the second processing core can be read by the first processor.
According to the drive control circuit of the embodiment of the invention, the first processor and the second processor perform data interaction through the shared memory, so that the first processor and the second processor can execute processes independently, data isolation is realized, and the first processor and the second processor can store and read and write data in a partitioning manner, thereby effectively improving the computational efficiency and reliability of a dual-core processing scheme.
According to the drive control circuit of the above embodiment of the present invention, optionally, the shared memory includes a nonvolatile memory.
According to the driving control circuit of the embodiment of the invention, the memory (internal memory) serves as an important bridge between the controller (i.e. the processing core) and the hard disk, which provides faster read/write performance, but if the memory is suddenly powered down, the data stored in the memory may be lost, so that, since the first processor and the second processor are both coupled to the shared memory, and the structure of the Nonvolatile memory is usually a "battery + memory chip", in case of power failure, the battery supplies power to the memory chip, and can keep the data in the memory chip for 72 hours, the Nonvolatile memory is adopted in the present application to overcome the problem of sudden power down, wherein the Nonvolatile memory (NVM) is divided into two types, namely block addressing and byte addressing, and in addition, the commonly used byte-addressed Nonvolatile memory mainly includes a phase change memory, and a phase change memory, Resistive random access memories, spin torque memories, and the like, but are not limited thereto.
According to the drive control circuit of the above embodiment of the present invention, optionally, the second processing core is further provided with a main control unit, and the main control unit can perform drive control on the motor assembly, and if the first processing core detects that the motor assembly is out of order, the motor assembly is controlled to stop operating or power off, and a fault type corresponding to the motor assembly is determined through analysis.
According to the drive control circuit provided by the embodiment of the invention, the main control unit is arranged in the second processing core, the main control unit is mainly used for controlling the operation of the PFC and triggering the operation of the first processing core, the operation capacity of the second processing core is usually stronger than that of the first processor, and when the first processing core is in a fault or is stopped, the main control unit can analyze the operation parameters and the fault reason of the first processing core and restart and initialize the first processing core.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the detection portion corresponding to the motor component, the first processing core generates a fault identifier corresponding to the fault type and transmits the fault identifier to the shared memory, and the second processing core can read the fault identifier from the shared memory.
According to the drive control circuit of the embodiment of the invention, by connecting the detection pin of the first processing core to the detection part of the motor assembly and generating the corresponding fault identifier, the second processing core can read the fault identifier through the shared memory, and further perform corresponding protection operations according to the fault identifier, such as cutting off an alternating current signal, controlling a power switch to be turned off, and performing operations such as surge absorption.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the coil of the motor assembly, and/or a sense pin of the first processing core is connected to a drive circuit of the motor assembly, when the first processing core runs the first interrupt function, if the fault type is determined to correspond to the hardware overcurrent fault through analysis, generating a first-level interrupt signal, enabling the internal pin by the first-level interrupt signal, triggering the second processing core to execute a corresponding interrupt process so as to scram the power factor correction module, the hardware overcurrent fault is determined by a load signal of a coil of the motor assembly or a driving signal of the motor assembly, and the numerical range of the response time of the power factor correction module is suddenly stopped by adopting the first interrupt function is 0.5 us-16 us.
According to the driving control circuit of the embodiment of the invention, when the first processing core runs a first interrupt function, if it is analytically determined that the fault type corresponds to a hardware overcurrent fault, a first-stage interrupt signal is generated, the first-stage interrupt signal enables the internal pin to trigger the second processing core to execute a corresponding interrupt process to scram the Power factor correction Module, wherein the hardware overcurrent fault is determined by a load signal of a coil of the motor assembly or a driving signal of the motor assembly, a response time for scramming the Power factor correction Module by using the first interrupt function is in a range of 0.5us to 16us, generally speaking, the overcurrent fault most easily causes circuit elements to be burned out, especially a PFC and an IPM (Intelligent Power Module), the first-stage interrupt signal can control the PFC or a Power switching device in the IPM to stop working within 0.5us to 16us, the method controls the PFC and the IPM to suddenly stop, so that the current impact of sudden stop of the motor assembly on the PFC and the IPM is reduced, and the reliability of the PFC and the IPM is improved.
The IPM integrates a power switch device and a high-voltage driving circuit, and is internally provided with fault detection circuits such as overvoltage, overcurrent and overheat, on one hand, the IPM receives a control signal sent by the first processing core to drive a subsequent circuit to work, and on the other hand, the IPM sends a state detection signal of the system back to the first processing core. Compared with the traditional discrete scheme, the IPM gains a bigger and bigger market with the advantages of high integration degree, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device in the fields of frequency conversion speed regulation, metallurgical machinery, electric traction, servo drive, frequency conversion household appliances and the like.
In summary, the hardware overcurrent fault is usually an IPM overcurrent fault or a demagnetization fault.
According to the drive control circuit in the foregoing embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the data pin of the main control unit, when the first processing core runs a second interrupt function, if it is determined through analysis that the fault type corresponds to a software fault, a second-level interrupt signal is generated, the second-level interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process, so as to scram the power factor correction module, where the software fault is a data signal in the running process of the main control unit, and a numerical range of response time for scramming the power factor correction module using the second interrupt function is 3us to 35 us.
According to the drive control circuit of the embodiment of the invention, when the first processing core runs the second interrupt function, if the fault type is determined to correspond to the software fault through analysis, the second-level interrupt signal is generated, the second-level interrupt signal enables the internal pin to trigger the second processing core to execute the corresponding interrupt process, so as to stop the power factor correction module urgently, wherein the software fault is a data signal in the running process of the main control unit, the numerical range of the response time of stopping the power factor correction module urgently by adopting the second interrupt function is 3 us-35 us, the software fault is a fault generated when the first processing core executes a software code process, the software code can realize torque compensation and/or rotating speed compensation on the motor component, calculate the phase current and calculate the demagnetization time of the motor component, detecting whether the motor assembly is over-temperature, calculating the operation pressure of the motor assembly, and the like, but not limited thereto, so that when a software fault occurs, the normal operation of the motor assembly may be affected, but the motor assembly is not affected in general, and therefore, the priority of the second-stage interrupt signal may be set to be lower than the priority of the first-stage interrupt signal.
According to the drive control circuit of the above embodiment of the present invention, optionally, the detection pin of the first processing core is connected to the driving component of the motor assembly, when the first processing core runs a third interrupt function, if it is analytically determined that the fault type corresponds to an operation fault, a third-stage interrupt signal is generated, the third-stage interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process to scram the power factor correction module, wherein the operation fault includes at least one of a locked rotor fault, a flux fault, a phase failure fault, an overvoltage fault and an undervoltage fault, and a response time of the power factor correction module is scrammed in a range from 13us to 1013us by using the third interrupt function.
According to the drive control circuit of the embodiment of the invention, when the first processing core runs a third interrupt function, if the fault type is analytically determined to correspond to an operation fault, a third-stage interrupt signal is generated, the third-stage interrupt signal enables the internal pin, and triggers the second processing core to execute a corresponding interrupt process so as to scram the power factor correction module, wherein the operation fault comprises at least one of a locked rotor fault, a magnetic flux fault, a phase failure fault, an overvoltage fault and an undervoltage fault, and the numerical range of response time for scramming the power factor correction module by using the third interrupt function is 13 us-1013 us.
When the motor winding is cooled to normal working condition temperature, a relay on the input side of a rectifier module is closed, but the motor cannot be started, so that the motor is locked, and the reason of locked rotor-thermal protection-locked rotor is generated.
In addition, flux failure mainly refers to abnormal magnetic flux of the coil of the motor assembly, which may cause overheating or insufficient power of the motor assembly.
In summary, the third level interrupt signal reflects abnormal operation of the motor assembly, and the third interrupt function includes a function in the main cycle, and the third level interrupt signal may have a lower priority than the second level interrupt signal.
Fig. 2 shows a schematic block diagram of an air conditioner according to another embodiment of the present invention.
As shown in fig. 2, an air conditioner according to another embodiment of the present invention includes: a drive control circuit as shown in fig. 1; and the motor assembly is connected to the drive control circuit, the drive control circuit is used for driving and controlling the motor assembly to operate, and the drive control circuit is also used for detecting whether the motor assembly has faults or not.
The air conditioner according to the embodiment of the present invention has all the technical effects of the above-mentioned driving control circuit, and will not be described herein again.
According to the drive control circuit of the above embodiment of the present invention, optionally, the motor assembly includes a fan and/or a compressor.
Fig. 3 shows a topological schematic of a bus circuit of the electrical machine assembly according to another embodiment of the invention.
As shown in fig. 3, a bus circuit of a motor assembly according to another embodiment of the present invention includes: the bus signal is a direct current power supply signal obtained by rectifying and filtering an Alternating Current (AC) signal through a rectifying module, the direct current power supply signal is continuously subjected to power factor correction through a Power Factor Correction (PFC), and then the direct current power supply signal is filtered through a capacitive element C and then input into an inverter bridge module, and the inverter bridge module is used for driving a three-phase inverter motor M to operate.
The PFC comprises an inductor L and a switch device, the control module is integrated in the first processing core, when the switch device is closed, the inductor L, the capacitor element C and the one-way conduction device D execute charging operation until the load voltage of the capacitor element reaches the starting voltage, and in addition, the control module detects the alternating current signal AC through the sampling resistance module.
Fig. 4 shows a flow diagram of a method performed by the drive control circuit according to another embodiment of the invention.
As shown in fig. 4, a method performed by a drive control circuit according to another embodiment of the present invention includes: s402, controlling the motor assembly to operate by the first processing core; s404, operating a first interrupt function, detecting whether a hardware overcurrent fault exists, if so, executing a step S410, and if not, executing a step S406; s406, operating a second interrupt function, detecting whether a software fault exists, if so, executing the step S412 and the step S410, and if not, executing the step S408; s408, running a third interrupt function (function in the main loop), detecting whether there is an operation failure, if yes, executing step S410 and step S412, and if no, executing step S402; s410, controlling the motor assembly to stop running so as to reduce the condition that the motor assembly is locked; s412, enabling the internal pin by the first processor; s414, triggering the second processing core to execute the interrupt process by the internal pin in the enabled state; and S416, controlling the PFC to stop running.
Steps S402 to S412 are performed by the first processing core, and steps S414 and S416 are performed by the second processing core.
The technical solution of the present invention is described in detail above with reference to the accompanying drawings, and in view of the technical problems in the related art, the present invention provides a driving control circuit and an air conditioner, the internal pins are coupled and connected to the first processing core and the second processing core, and the main function is that if the first processing core detects the motor component failure, enabling the internal pin, the internal pin in an enabled state triggering the second processing core to perform an interrupt process, the interrupt process is configured to scram the power factor correction module, that is, to execute the interrupt process with a response time on the order of micrometers, if the first processing core detects a failure of the motor assembly, the PFC can be stopped suddenly, so that the impact of sudden stop of the motor component on the PFC is reduced, and in addition, the efficiency and the reliability of fault processing of the air conditioner are effectively improved while the operating efficiency and the isolation of the double processing cores are ensured.
The steps in the method of the invention can be sequentially adjusted, combined and deleted according to actual needs.
The units in the device of the invention can be merged, divided and deleted according to actual needs.
It will be understood by those skilled in the art that all or part of the steps in the methods of the embodiments described above may be implemented by instructions associated with a program, which may be stored in a computer-readable storage medium, where the storage medium includes Read-Only Memory (ROM), Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), One-time Programmable Read-Only Memory (OTPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), compact disc-Read-Only Memory (CD-ROM), or other Memory, magnetic disk, magnetic tape, or magnetic tape, Or any other medium which can be used to carry or store data and which can be read by a computer.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A drive control circuit, comprising:
a first processing core configured to drive control a motor assembly;
a second processing core; the second processing core is configured to drive and control the power factor correction module, and the processing process of the first processing core is independent of the processing process of the second processing core;
an internal pin coupled to the first processing core and the second processing core,
if the first processing core detects that the motor assembly is in fault, enabling the internal pin, and triggering the second processing core to execute an interrupt process by the internal pin in an enabled state, wherein the interrupt process is configured to scram the power factor correction module.
2. The drive control circuit according to claim 1, further comprising:
a shared memory coupled to the first processing core and the second processor,
wherein the data transferred to the shared memory by the first processing core is readable by the second processor and the data transferred to the shared memory by the second processing core is readable by the first processor.
3. The drive control circuit according to claim 2,
the shared memory includes non-volatile memory.
4. The drive control circuit according to claim 2,
the second processing core is also provided with a main control unit which can drive and control the motor component,
and if the first processing core detects that the motor assembly is in fault, controlling the motor assembly to stop running or power off, and analyzing and determining the fault type corresponding to the motor assembly.
5. The drive control circuit according to claim 4,
the detection pin of the first processing core is connected to the detection part corresponding to the motor component,
and the first processing core generates a fault identifier corresponding to the fault type and transmits the fault identifier to the shared memory, and the second processing core can read the fault identifier from the shared memory.
6. The drive control circuit according to claim 4,
the detection pin of the first processing core is connected to the coil of the motor component, and/or the detection pin of the first processing core is connected to the driving circuit of the motor component,
when the first processing core runs a first interrupt function, if the fault type is determined to correspond to the hardware overcurrent fault through analysis, a first-stage interrupt signal is generated, the first-stage interrupt signal enables the internal pin, the second processing core is triggered to execute a corresponding interrupt process, and the power factor correction module is stopped urgently,
the hardware overcurrent fault is determined by a load signal of a coil of the motor assembly or a driving signal of the motor assembly, and the numerical range of the response time of the power factor correction module is suddenly stopped by adopting the first interrupt function is 0.5 us-16 us.
7. The drive control circuit according to claim 4, characterized by further comprising:
a detection pin of the first processing core is connected to a data pin of the master control unit,
when the first processing core runs a second interrupt function, if the fault type is determined to correspond to the software fault through analysis, a second-level interrupt signal is generated, the second-level interrupt signal enables the internal pin, the second processing core is triggered to execute a corresponding interrupt process, and the power factor correction module is stopped suddenly,
and the software fault is a fault of abnormal phase current detected by software, and the numerical range of the response time of the power factor correction module is suddenly stopped by adopting the second interrupt function and is 3-35 us.
8. The drive control circuit according to claim 7, characterized by further comprising:
the detection pin of the first processing core is connected to a driving part of the motor assembly,
when the first processing core runs a third interrupt function, if the fault type is determined to correspond to the bus running fault through analysis, a third-stage interrupt signal is generated, the third-stage interrupt signal enables the internal pin, the second processing core is triggered to execute a corresponding interrupt process, and the power factor correction module is suddenly stopped,
the operation faults comprise at least one of locked-rotor faults, magnetic flux faults, open-phase faults, overvoltage faults and undervoltage faults, and the numerical range of the response time of the power factor correction module is in the range of 13 us-1013 us when the power factor correction module is suddenly stopped by adopting the third interruption function.
9. An air conditioner, comprising:
the drive control circuit according to any one of claims 1 to 8;
and the motor assembly is connected to the drive control circuit, the drive control circuit is used for driving and controlling the motor assembly to operate, and the drive control circuit is also used for detecting whether the motor assembly has faults or not.
10. The air conditioner according to claim 9,
the motor assembly includes a fan and/or a compressor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910213335.4A CN111726052A (en) | 2019-03-20 | 2019-03-20 | Drive control circuit and air conditioner |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910213335.4A CN111726052A (en) | 2019-03-20 | 2019-03-20 | Drive control circuit and air conditioner |
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