CN111725623A

CN111725623A - Chip antenna module and electronic device

Info

Publication number: CN111725623A
Application number: CN202010086365.6A
Authority: CN
Inventors: 朴柱亨; 李杬澈; 安成庸; 韩奎范
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2019-03-20
Filing date: 2020-02-11
Publication date: 2020-09-29

Abstract

The present disclosure provides a chip antenna module and an electronic device, the chip antenna module including: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole; a second patch antenna pattern spaced apart from an upper surface of the first patch antenna pattern and having an area smaller than that of the first patch antenna pattern; a first feed via extending through the first dielectric layer and electrically connected to the first patch antenna pattern; a second feed via extending through the first dielectric layer and the through hole and electrically connected to the second patch antenna pattern; and a shielded via extending through the first dielectric layer, electrically connected to the first patch antenna pattern, and at least partially surrounding the second feed via.

Description

Chip antenna module and electronic device

This application claims the right of priority of korean patent application No. 10-2019-.

Technical Field

The following description relates to a chip antenna module and an electronic device including the same.

Background

Data traffic for mobile communications is rapidly increasing every year. Technological developments are ongoing to support such fast real-time data transmission in wireless networks. For example, applications of content such as internet of things (IoT) -based data, Augmented Reality (AR), Virtual Reality (VR), live VR/AR in conjunction with Social Networking Services (SNS), autonomous driving, synchronized windows (transmitting real-time images of a user's perspective using a subminiature camera), and so on, may require communications (e.g., fifth generation (5G) communications, millimeter wave (mmWave) communications, etc.) that support the sending and receiving of large amounts of data.

Therefore, in recent years, millimeter wave (mmWave) communication including 5G communication has been studied, and commercialization/standardization of a chip-type antenna module for smoothly realizing communication has been studied.

Radio Frequency (RF) signals in high frequency bands (e.g., 24GHz, 28GHz, 36GHz, 39GHz, 60GHz, etc.) are easily absorbed during transmission and may cause signal loss, and thus communication quality may be drastically degraded. Therefore, an antenna for communication in a high frequency band requires a method different from that of the conventional antenna technology, and may require development of special techniques, such as providing an additional power amplifier for ensuring integration of antenna gain, antenna and RFIC and ensuring Effective Isotropic Radiated Power (EIRP).

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In one general aspect, a chip antenna module includes: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole; a second patch antenna pattern spaced apart from an upper surface of the first patch antenna pattern and having an area smaller than that of the first patch antenna pattern; a first feed via extending through the first dielectric layer from the lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern; a second feed via extending from the lower surface of the first dielectric layer through the first dielectric layer and the through hole and electrically connected to the second patch antenna pattern; and a shielded via extending from the lower surface of the first dielectric layer through the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to at least partially surround the second feed via.

In one general aspect, a chip antenna module includes: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer; a second patch antenna pattern spaced apart from an upper surface of the first patch antenna pattern and having an area smaller than that of the first patch antenna pattern; a first feed via extending through the first dielectric layer from the lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern; a second feed via provided as a through hole extending from the lower surface of the first dielectric layer through the first dielectric layer and the first patch antenna pattern, and electrically connected to the second patch antenna pattern; and a shielded via extending from the first dielectric layer, through the first dielectric layer, electrically connected to the first patch antenna pattern, and at least partially surrounding the second feed via.

The second feed via may include two or more second feed vias. The shielded vias may be arranged to at least partially surround the two or more second feed vias, respectively.

The first feed via may be offset from a center of the first patch antenna pattern. The second feeding via is disposed closer to the center of the first patch antenna pattern than the first feeding via.

The chip antenna module may further include: and a second dielectric layer disposed between the first patch antenna pattern and the second patch antenna pattern, wherein a dielectric constant of the second dielectric layer is lower than a dielectric constant of the first dielectric layer.

The thickness of the second dielectric layer may be smaller than the thickness of the first dielectric layer.

The second dielectric layer may include a polymer. The first dielectric layer may comprise a ceramic.

The chip antenna module may further include: and the third dielectric layer is arranged above the second dielectric layer, wherein the dielectric constant of the third dielectric layer is higher than that of the second dielectric layer.

The thickness of the third dielectric layer may be greater than the thickness of the second dielectric layer and less than the thickness of the first dielectric layer.

The chip antenna module may further include: a coupling patch pattern disposed on an upper surface of the third dielectric layer.

The chip antenna module may further include: and a third dielectric layer disposed over the first dielectric layer, wherein a lower surface of the third dielectric layer forms an arrangement space of the second patch antenna pattern.

The chip antenna module may further include: a second dielectric layer disposed between the first dielectric layer and the third dielectric layer; and an air cavity surrounded by the second dielectric layer.

The first patch antenna pattern may include two or more first patch antenna patterns. The first dielectric layer may be a single first dielectric layer overlapping each of the two or more first patch antenna patterns.

In another general aspect, an electronic device includes: a chip antenna module; a connection member including an upper surface to which the solder layer of each of the chip antenna modules is electrically connected; and an IC electrically connected to a lower surface of the connection member. At least one of the chip antenna modules includes: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole; a second patch antenna pattern spaced apart from an upper surface of the first patch antenna pattern and having an area smaller than that of the first patch antenna pattern; a first feed via extending through the first dielectric layer from the lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern; a second feed via extending from the lower surface of the first dielectric layer through the first dielectric layer and the through hole and electrically connected to the second patch antenna pattern; and a shielded via extending from the lower surface of the first dielectric layer through the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to at least partially surround the second feed via.

The connection member may further include: a feed line electrically connecting the first feed via to the IC; a routing ground plane at least partially surrounding the feed line; and a first ground plane disposed between the wiring ground plane and the chip antenna module.

The connection member may further include: a second solder layer disposed above the first ground plane and electrically connected to the solder layer; and peripheral vias connecting the second solder layer to the first ground plane.

The connection member may further include: a first ground plane disposed below the chip antenna module; and an endfire antenna, at least a portion of the endfire antenna not overlying the first ground plane and positioned below the first ground plane.

In another general aspect, a chip antenna module includes: a first dielectric layer; a solder layer disposed on a lower surface of the first dielectric layer; a connection member including a ground plane connected to the solder layer; a first patch antenna pattern disposed on an upper surface of the first dielectric layer and configured to transmit and receive signals in a first frequency band; a second patch antenna pattern disposed above the first patch antenna pattern and configured to transmit and receive a signal in a second frequency band, the second frequency band being different from the first frequency band; a first feeding via extending through the first dielectric layer, wherein one end of the first feeding via is connected to a lower surface of the first patch antenna pattern, and the other end of the first feeding via is connected to the connection member; a second feeding via hole extending through the first dielectric layer and the through hole in the first patch antenna pattern, wherein one end of the second feeding via hole is connected to a lower surface of the second patch antenna pattern, and the other end of the second feeding via hole is connected to the connection member; and shielded via holes at least partially surrounding the second feeding via holes in the first dielectric layer, wherein one end of each of the shielded via holes is connected to a lower surface of the first patch antenna pattern, and the other end of the shielded via hole is connected to the connection member.

The chip antenna module may further include a third dielectric layer disposed on an upper surface of the second patch antenna pattern.

The chip antenna module may further include a second dielectric layer disposed between the first dielectric layer and the third dielectric layer and having a dielectric constant lower than that of the first dielectric layer and the third dielectric layer.

The first feeding via hole may be offset from a center of the first patch antenna pattern by a distance greater than a distance by which the second feeding via hole is offset from the center of the first patch antenna pattern.

Other features and aspects will be apparent from the following detailed description, the accompanying drawings, and the claims.

Drawings

Fig. 1A and 1B are side views illustrating a chip type antenna module according to an embodiment.

Fig. 2A and 2B are perspective views illustrating the chip antenna module of fig. 1A according to an embodiment.

Fig. 3 is a perspective view illustrating a shielded via provided in the chip antenna module of fig. 1A according to an embodiment.

Fig. 4A to 4C are plan views illustrating solder layers of the chip antenna module according to the embodiment.

Fig. 5A is a perspective view illustrating an arrangement of a chip-type antenna module according to an embodiment.

Fig. 5B is a perspective view illustrating an integrated chip antenna module in which the chip antenna module according to the embodiment is integrated.

Fig. 6A is a plan view illustrating an end fire antenna included in a connection member disposed under a chip antenna module according to an embodiment.

Fig. 6B is a plan view illustrating an end fire antenna provided in a connection member disposed below a chip antenna module according to an embodiment.

Fig. 7A to 7C are diagrams illustrating a method of manufacturing a chip-type antenna module according to an embodiment.

Fig. 7D is a diagram illustrating a process of forming an arrangement space of a patch antenna pattern of a dielectric layer of a chip antenna module according to an embodiment.

Fig. 8A is a plan view illustrating a first ground plane of a connection member included in an electronic device according to an embodiment.

Fig. 8B is a plan view illustrating a feed line located below the first ground plane of fig. 8A according to an embodiment.

Fig. 8C is a plan view illustrating a routing via and a second ground plane located under the feeder of fig. 8B, according to an embodiment.

Fig. 8D is a plan view illustrating an IC arrangement and an end-fire antenna located below the second ground plane of fig. 8C, in accordance with an embodiment.

Fig. 9A and 9B are side views showing the structure of the portion shown in fig. 8A to 8D and an element located below the portion.

Fig. 10A and 10B are plan views illustrating an electronic device including a sheet type antenna module according to an embodiment.

Like reference numerals refer to like elements throughout the drawings and the detailed description. The figures may not be drawn to scale and the relative sizes, proportions and depictions of the elements in the figures may be exaggerated for clarity, illustration and convenience.

Detailed Description

The following detailed description is provided to assist the reader in obtaining a thorough understanding of the methods, devices, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and/or systems described herein will be apparent to those skilled in the art upon review of the disclosure of this application. For example, the order of operations described herein is merely an example and is not limited to the order set forth herein, but rather, variations may be made in addition to operations that must be performed in a particular order, which will be apparent upon understanding the disclosure of the present application. Moreover, descriptions of features known in the art may be omitted for greater clarity and conciseness.

The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways to implement the methods, devices, and/or systems described herein that will be apparent upon understanding the disclosure of the present application.

Here, it is noted that the use of the term "may" with respect to an example or embodiment, e.g., with respect to what an example or embodiment may include or implement, means that there is at least one example or embodiment that includes or implements such a feature, and all examples or embodiments are not limited thereto.

Throughout the specification, when an element such as a layer, region or substrate is described as being "on," connected to "or" coupled to "another element, it may be directly on," connected to or directly coupled to the other element or one or more other elements may be present therebetween. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there may be no intervening elements present.

As used herein, the term "and/or" includes any one of the associated listed items or any combination of any two or more of the items.

Although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section referred to in the examples described herein could be termed a second element, component, region, layer or section without departing from the teachings of the examples.

Spatially relative terms, such as "above," "upper," "lower," and "below," may be used herein for ease of description to describe one element's relationship to another element as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "upper" relative to another element would then be oriented "below" or "lower" relative to the other element. Thus, the term "above" includes both an above orientation and a below orientation, depending on the spatial orientation of the device. The device may also be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative terms used herein will be interpreted accordingly.

The terminology used herein is for the purpose of describing various examples only and is not intended to be limiting of the disclosure. The singular is intended to include the plural unless the context clearly dictates otherwise. The terms "comprises," "comprising," and "having" specify the presence of stated features, quantities, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and/or combinations thereof.

Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be effected. Accordingly, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shapes that occur during manufacturing.

The features of the examples described herein may be combined in various ways that will be apparent after understanding the disclosure of the present application. Further, while the examples described herein have various configurations, other configurations are possible as will be apparent upon understanding the disclosure of the present application.

According to an aspect described below, a chip antenna module and an electronic device including the chip antenna module can provide a transmitting-receiving device operable in a plurality of frequency bands different from each other while improving antenna performance and/or easily achieving component miniaturization.

Fig. 1A is a side view illustrating a chip-type antenna module 100a according to an embodiment. Fig. 2A and 2B are perspective views illustrating a chip-type antenna module 100a according to an embodiment. Fig. 3 is a perspective view illustrating the shielded via 130a provided in the chip-type antenna module 100a according to the embodiment.

Referring to fig. 1A, 2B, and 3, the chip antenna module 100a may include a first patch antenna pattern 111A and a second patch antenna pattern 112A. Accordingly, the chip antenna module 100a may be a transmitting and receiving device operable in a plurality of frequency bands different from each other. The chip antenna module 100a may further include a coupling patch pattern 115a, and the coupling patch pattern 115a is configured to widen a frequency bandwidth corresponding to the second patch antenna pattern 112 a. The coupling patch pattern 115a may be omitted according to a bandwidth design condition. For example, the coupling patch pattern 115a may have a slit. For example, at least one of the coupling patch pattern 115a, the first patch antenna pattern 111a, and the second patch antenna pattern 112a may be rotated by 45 degrees.

Further, the chip-type antenna module 100a may include first and

second feeding vias

121a and 121b and 122a and 122b, and may be disposed on the first ground plane 201a of the connection member 200.

The first patch antenna pattern 111a is electrically connected to one end of each of the

first feed vias

121a and 121 b. Accordingly, the first patch antenna pattern 111a receives and transmits a first Radio Frequency (RF) signal in a first frequency band (e.g., 28GHz) from the

first feed vias

121a and 121b, or receives and provides the first RF signal to the

first feed vias

121a and 121 b.

The second patch antenna pattern 112a is electrically connected to one end of each of the

second feed vias

122a and 122 b. Accordingly, the second patch antenna pattern 112a receives and transmits a second Radio Frequency (RF) signal in a second frequency band (e.g., 39GHz) from the

second feed vias

122a and 122b, or receives the second RF signal and provides the second RF signal to the

second feed vias

122a and 122 b.

The first and second

patch antenna patterns

111a and 112a resonate corresponding to the first and second frequency bands, respectively, so that energy corresponding to the first and second RF signals is concentratedly received and radiated outward.

The first ground plane 201a may reflect the first and second RF signals radiated toward the first ground plane 201a among the first and second RF signals radiated by the first and second

patch antenna patterns

111a and 112 a. Accordingly, the radiation patterns of the first and second

patch antenna patterns

111a and 112a may be concentrated in a specific direction (e.g., a Z-direction). Accordingly, the gains of the first and second

patch antenna patterns

111a and 112a may be improved.

The resonance of the first and second

patch antenna patterns

111a and 112a may occur based on a resonance frequency according to a combination of inductance and capacitance corresponding to the first and second

patch antenna patterns

111a and 112a and a surrounding structure.

The size (e.g., area) of the upper surface and/or the lower surface of each of the first and second

patch antenna patterns

111a and 112a may affect the resonant frequency. That is, the size of the upper surface and/or the lower surface of each of the first patch antenna pattern 111a and the second patch antenna pattern 112a may depend on the first wavelength corresponding to the first frequency and the second wavelength corresponding to the second frequency, respectively. If the first frequency is lower than the second frequency, the size (e.g., area) of the first patch antenna pattern 111a may be larger than the size (e.g., area) of the second patch antenna pattern 112 a.

At least a portion of the first patch antenna pattern 111a and at least a portion of the second patch antenna pattern 112a may be overlapped with each other in a vertical direction (e.g., Z direction). Accordingly, since the size (e.g., length) of the chip-type antenna module 100a in the horizontal direction (e.g., X-direction and/or Y-direction) can be significantly reduced, the entire chip-type antenna module 100a can be easily miniaturized.

The

first feeding vias

121a and 121b and the

second feeding vias

122a and 122b are disposed as at least one through hole passing through the first ground plane 201 a. Accordingly, one end of each of the first and

second feed vias

121a and 121b and 122a and 122b is located above the first ground plane 201a, and the other end of each of the first and

second feed vias

121a and 121b and 122a and 122b is located below the first ground plane 201 a. Since the other end of each of the first and

second feed vias

121a and 121b and 122a and 122b is electrically connected to an Integrated Circuit (IC) mounted on the component mounting surface, the first and second RF signals are supplied to or received from the IC. Electromagnetic isolation between the first patch antenna pattern 111a and the IC and between the second patch antenna pattern 112a and the IC may be improved by the first ground plane 201 a.

The

first feed vias

121a and 121b include 1 st-1 and 1 st-2 feed vias through which 1 st-1 and 1 st-2 RF signals polarized to each other pass, respectively, and the

second feed vias

122a and 122b include 2 st-1 and 2 nd-2 feed vias through which 2 nd-1 and 2 nd-2 RF signals polarized to each other pass, respectively.

That is, each of the first and second

patch antenna patterns

111a and 112a may transmit and receive a plurality of RF signals, and the plurality of RF signals may be a plurality of carrier signals carrying different data segments therein. Accordingly, the data transmission and reception rate of each of the first and second

patch antenna patterns

111a and 112a may be increased by two times according to the transmission and reception of the plurality of RF signals.

For example, the 1 st-1 st and 1 st-2 nd RF signals have different phases (e.g., 90 degrees or 180 degrees out of phase) to reduce interference with each other, and the 2 nd-1 st and 2 nd-2 nd RF signals have different phases (e.g., 90 degrees or 180 degrees out of phase) to reduce interference with each other.

For example, the 1 st-1 st and 1 st-2 nd RF signals form electric and magnetic fields perpendicular to the direction of propagation (e.g., Z direction) and in X and Y directions, respectively, that are perpendicular to each other. In addition, the 2 nd-1 st RF signal and the 2 nd-2 nd RF signal form a magnetic field and an electric field in the X direction and the Y direction, respectively. Thus, polarization between RF signals can be achieved. In the first and second

patch antenna patterns

111a and 112a, surface currents corresponding to the 1 st-1 st and 2 nd-1 st RF signals and surface currents corresponding to the 1 st-2 nd and 2 nd-2 nd RF signals may flow perpendicular to each other.

Accordingly, the 1 st-1 st feed via is connected to the first patch antenna pattern 111a adjacent to an edge in one direction (e.g., X direction) in the first patch antenna pattern 111a, and the 2 nd-1 st feed via is connected to the second patch antenna pattern 112a adjacent to an edge in one direction (e.g., X direction) in the second patch antenna pattern 112 a. The 1 st-2 nd feed via is connected to the first patch antenna pattern 111a adjacent to an edge in the other direction (e.g., Y direction) in the first patch antenna pattern 111a, and the 2 nd-2 nd feed via is connected to the second patch antenna pattern 112a adjacent to an edge in the other direction (e.g., Y direction) in the second patch antenna pattern 112 a. However, the particular connection point may vary based on design.

Since the electrical length from the first and second

patch antenna patterns

111a and 112a to the IC is reduced, the energy loss of the first and second RF signals in the chip antenna module 100a may be further reduced. Since the lengths in the vertical direction (e.g., Z direction) between the first and second

patch antenna patterns

111a and 112a and the ICs are relatively short, the first and

second feeding vias

121a and 121b and 122a and 122b may easily reduce the electrical connection distance between the first and second

patch antenna patterns

111a and 112a and the ICs.

When at least a portion of the first patch antenna pattern 111a and at least a portion of the second patch antenna pattern 112a are overlapped with each other, the

second feeding vias

122a and 122b may be disposed to pass through the first patch antenna pattern 111a to be electrically connected to the second patch antenna pattern 112 a.

Accordingly, transmission energy loss of the first and second RF signals in the chip antenna module 100a may be reduced, and connection points of the

first feed vias

121a and 121b located in the first patch antenna pattern 111a and connection points of the

second feed vias

122a and 122b located in the second patch antenna pattern 112a may be more freely designed.

In terms of the first and second RF signals, the connection point of the first and

second feed vias

121a and 121b and 122a and 122b may affect the transmission line impedance. As the transmission line impedance is matched closer to a particular impedance (e.g., 50 ohms), reflection phenomena in providing the first and second RF signals may be reduced. Accordingly, when the degree of freedom in design of the connection points of the first and

second feed vias

121a and 121b and 122a and 122b is high, the gains of the first and second

patch antenna patterns

111a and 112a may be more easily improved.

However, since the

second feeding vias

122a and 122b are disposed to pass through the first patch antenna pattern 111a, radiation of the first RF signal concentrated on the first patch antenna pattern 111a may be affected. Therefore, the electromagnetic isolation between the first RF signal and the second RF signal may be degraded. The deterioration of the electromagnetic isolation may cause the deterioration of each gain in the first and second

patch antenna patterns

111a and 112 a.

Accordingly, the chip antenna module 100a includes the first and second

patch antenna patterns

111a and 112a and may further include a shielding via 130a surrounding the

second feeding vias

122a and 122 b.

The shielded via 130a may be provided to electrically connect the first patch antenna pattern 111a to the first ground plane 201 a. Accordingly, a first RF signal radiated toward the

second feed vias

122a and 122b among the first RF signals radiated from the first patch antenna pattern 111a may be reflected by the shielding via 130 a. Accordingly, electromagnetic isolation between the first and second RF signals may be improved, and a gain of each of the first and second

patch antenna patterns

111a and 112a may be improved.

The number and width of the shielded vias 130a are not particularly limited. The first RF signal may not substantially pass through the spaces between the plurality of shielded vias 130a if the distance of the spaces between the plurality of shielded vias 130a is less than a certain length (e.g., a length according to the first wavelength of the first RF signal). Therefore, the electromagnetic isolation between the first RF signal and the second RF signal can be further improved.

When the

second feed vias

122a and 122b are provided, the shielding via 130a may be arranged to surround the

second feed vias

122a and 122b, respectively.

Accordingly, since the electromagnetic isolation between the

second feed vias

122a and 122b and thus the electromagnetic isolation in the second patch antenna pattern 112a between the 2-1RF signal and the 2-2RF signal can be further improved, the overall gain of the second patch antenna pattern 112a can be further improved.

The

first feed vias

121a and 121b are offset from the center of the first patch antenna pattern 111a in the first direction, while the

second feed vias

122a and 122b are closer to the center of the first patch antenna pattern 111a than the

first feed vias

121a and 121 b. That is, the

first feed vias

121a and 121b may be offset from the center of the first patch antenna pattern 111a by a larger distance than the

second feed vias

122a and 122b are offset from the center of the first patch antenna pattern 111 a.

Since the shielding via 130a is electrically connected to the first patch antenna pattern 111a, a surface current of the first patch antenna pattern 111a may flow from a connection point of the

first feed vias

121a and 121b to a connection point of the shielding via 130 a. Accordingly, since the surface current of the first patch antenna pattern 111a may be more concentrated on the edge of the first patch antenna pattern 111a, the RF signal of the first patch antenna pattern 111a may better avoid the second patch antenna pattern 112a to be transmitted remotely in the Z direction. That is, a phenomenon that the second patch antenna pattern 112a interferes with radiation of the first patch antenna pattern 111a may be further reduced, and a gain of the first patch antenna pattern 111a may be further improved.

Further, referring to fig. 1A, the chip antenna module 100a may include at least one of the first dielectric layer 151A and the third dielectric layer 151b in addition to the second dielectric layer 152a, and may be mounted on the connection member 200. For example, the connection member 200 may have a stacked structure including at least a portion of the first ground plane 201a, the routing ground plane 202a, the second ground plane 203a, and the IC ground plane 204a, and may be implemented as a Printed Circuit Board (PCB).

The chip antenna module 100a and the connection member 200 may be separately manufactured, and may be physically coupled to each other after each of the chip antenna module 100a and the connection member 200 is manufactured.

Accordingly, the first, third and second

dielectric layers

151a, 151b and 152a may be more easily configured to have characteristics (e.g., dielectric constant Dk, dielectric tangent (Df), durability, etc.) different from those of the insulating layer of the connection member 200. Accordingly, the chip antenna module 100a may easily have improved antenna characteristics (e.g., gain, bandwidth, directivity, etc.) with respect to the size, and the connection member 200 may have improved routing performance (e.g., torsion strength with respect to the number of stacked layers, low dielectric constant, etc.) of the feed line and the feed via.

The first and third

dielectric layers

151a and 151b may be formed using a material having a higher dielectric constant than that of the second dielectric layer 152 a. For example, the first and third

dielectric layers

151a and 151b may be formed using a material such as a ceramic-based material, such as low temperature co-fired ceramic (LTCC), or a glass-based material, and may be configured to have a higher dielectric constant or greater durability by further including any one of magnesium (Mg), silicon (Si), aluminum (Al), calcium (Ca), and titanium (Ti), or any combination of any two or more thereof. For example, the first and third

dielectric layers

151a and 151b may include Mg₂SiO₄、MgAlO₄And CaTiO₃。

The lower surface of the first dielectric layer 151a may form an arrangement space of the solder layer 140 a. The solder layer 140a is mounted on the upper surface of the connection member 200 to be physically coupled to the connection member 200.

For example, the chip antenna module 100a may be disposed such that the second solder layer 180a disposed on the upper surface of the connection member 200 overlaps the solder layer 140 a. The second solder layer 180a is connected to the peripheral via 185a of the connection member 200 and thus has a strong bonding force to the connection member 200. For example, the peripheral vias 185a may connect the second solder layer 180a to the first ground plane 201 a.

The solder layer 140a and the second solder layer 180a may be bonded to each other by solder paste formed using a material having a low melting point, such as tin (Sn). The solder paste may be interposed between the solder layer 140a and the second solder layer 180a at a temperature higher than the melting point of the solder paste. As the temperature decreases, the solder paste may form the electrical connection structure 160 a. That is, the electrical connection structure 160a may electrically connect the solder layer 140a to the second solder layer 180 a.

For example, to improve the bonding efficiency between the solder layer 140a and the second solder layer 180a, the surface of the solder layer 140a and the surface of the second solder layer 180a may form a stacked structure of a nickel plated layer and a tin plated layer, but is not limited thereto. That is, at least a portion of the solder layer 140a and at least a portion of the second solder layer 180a may be formed using a plating process, and the first dielectric layer 151a may be configured to have characteristics (e.g., high temperature reliability) suitable for the plating process of the solder layer 140 a.

In addition, the lower surface of the first dielectric layer 151a may be provided with lead-out spaces for the

first feed vias

121a and 121b, the

second feed vias

122a and 122b, and the shield via 130 a.

Accordingly, the electrical connection structure 160a having a relatively low melting point or a relatively large width in the horizontal direction may be connected to the lower end of each of the

first feed vias

121a and 121b, the

second feed vias

122a and 122b, and the shielding via 130 a. For example, the electrical connection structure 160a may be provided as at least one of a solder ball, a pin, a pad, and may have a shape similar to that of the solder layer 140a according to design.

An upper surface of the first dielectric layer 151a may form an arrangement space of the first patch antenna pattern 111 a.

The lower surface of the third dielectric layer 151b may form an arrangement space of the second patch antenna pattern 112 a.

The upper surface of the third dielectric layer 151b may form an arrangement space of the coupling patch pattern 115a and may be sealed by an encapsulant according to design.

The second dielectric layer 152a may be disposed on an upper surface of the first dielectric layer 151a or a lower surface of the third dielectric layer 151b, and may have a dielectric constant lower than that of the first dielectric layer 151a or that of the third dielectric layer 151 b.

The second dielectric layer 152a may be formed using a material having a dielectric constant lower than that of the insulating layer of the connection member 200, such as a polymer, but is not limited thereto. For example, the second dielectric layer 152a may be formed using ceramic, may be formed using a material having high flexibility, such as Liquid Crystal Polymer (LCP) or polyimide, may be formed using an epoxy resin having high strength or high adhesive force, may be formed using a material having high durability, such as Teflon, or may be formed using a material having high compatibility with the connection member 200, such as prepreg.

When an RF signal transmitted and received from the chip antenna module 100a passes through the first, third, and second

dielectric layers

151a, 151b, and 152a, the RF signal may have a wavelength based on the dielectric constant of the first dielectric layer 151a, the dielectric constant of the third dielectric layer 151b, and the dielectric constant of the second dielectric layer 152 a. That is, the effective wavelength of the RF signal in the chip antenna module 100a may become short according to the high dielectric constant of the first dielectric layer 151a and the high dielectric constant of the third dielectric layer 151 b. The overall size of the chip antenna module 100a has a high correlation with the length of the effective wavelength of the RF signal. Accordingly, the chip antenna module 100a includes the first dielectric layer 151a and/or the third dielectric layer 151b having a high dielectric constant, thereby having a reduced size without substantially deteriorating antenna performance.

The overall size of the chip antenna module 100a may correspond to the number of arrangements of the chip antenna module 100a per unit size of the first ground plane 201 a. That is, as the size of the chip antenna module 100a is reduced, the overall gain and/or directivity of the chip antenna module 100a may be improved.

On the other hand, since the second dielectric layer 152a has a relatively low dielectric constant, the wavelength of the RF signal at the second dielectric layer 152a may be relatively long.

Each of a first interface between the second dielectric layer 152a and the first dielectric layer 151a and a second interface between the second dielectric layer 152a and the third dielectric layer 151b may be used as a boundary condition of the RF signal.

Due to the difference in dielectric constant between the first dielectric layer 151a and/or the third dielectric layer 151b and the second dielectric layer 152a, the propagation direction of the RF signal through the boundary condition is made to be refracted. As the difference in dielectric constant becomes larger, the refraction amplitude of the RF signal may become larger.

Since the second dielectric layer 152a having a low dielectric constant is disposed between the first and third

dielectric layers

151a and 151b having a high dielectric constant, the transmission and reception directions of each of the first and second RF signals may be more concentrated in the Z direction.

Since the first RF signal radiated from the upper surface of the first patch antenna pattern 111a is guided from a medium having a low dielectric constant to a medium having a high dielectric constant, a vector component of the first RF signal in a horizontal direction may be shortened. Accordingly, the radiation direction of the first patch antenna pattern 111a may be more concentrated in the Z direction. Accordingly, the gain of the first patch antenna pattern 111a may be improved.

In addition, the first RF signal has a relatively long vector component in the horizontal direction at the second dielectric layer 152a, and thus may better avoid the second patch antenna pattern 112a to be radiated in the Z direction. Accordingly, a phenomenon in which the second patch antenna pattern 112a interferes with radiation of the first patch antenna pattern 111a may be further reduced, and a gain of the first patch antenna pattern 111a may be further improved.

The second RF signal radiated from the lower surface of the second patch antenna pattern 112a may propagate in the Z direction by reflection of the first ground plane 201a and/or the first patch antenna pattern 111 a. In this case, the second RF signal is guided from the medium having a low dielectric constant to the medium having a high dielectric constant, and thus can be more concentrated in the Z direction. Accordingly, the gain of the second patch antenna pattern 112a may be improved.

As a result, the chip antenna module 100a may improve the gain of the first RF signal and the gain of the second RF signal.

The thickness of the second dielectric layer 152a may be smaller than that of the first dielectric layer 151 a. Accordingly, due to the relatively low dielectric constant of the second dielectric layer 152a, remote transmission and reception of the first and second RF signals may be concentrated in the Z direction.

The thickness of the third dielectric layer 151b may be greater than that of the second dielectric layer 152a and may be smaller than that of the first dielectric layer 151 a. Accordingly, a phenomenon in which the second patch antenna pattern 112a causes electromagnetic interference with the first patch antenna pattern 111a via the coupling patch pattern 115a may be further suppressed.

Fig. 1B is a side view illustrating a chip-type antenna module 100a-1 according to an embodiment.

Referring to fig. 1B, in contrast to the chip-type antenna module 100a of fig. 1A, the chip-type antenna module 100a-1 may include a second dielectric layer 152B and an air cavity 152 c.

For example, the second dielectric layer 152b may be configured to surround the air cavity 152c, and may physically support a space between the first dielectric layer 151a and the third dielectric layer 151 b.

Accordingly, the dielectric constant of the air cavity 152c between the first and second

patch antenna patterns

111a and 112a may be lower than that of the second dielectric layer 152b, and the first and second RF signals may be more effectively refracted at the interface between the first dielectric layer 151a and the air cavity 152c due to the large difference in dielectric constant between the first dielectric layer 151a and the air cavity 152 c. Accordingly, the gain of the chip antenna module 100a-1 can be further improved.

Referring to fig. 4A, the solder layer 140a of the chip antenna module 100a may have a rectangular plate shape.

Referring to fig. 4B, the solder layer 140e of the chip antenna module 100e may have a straight bar shape.

Referring to fig. 4C, the solder layer 140f of the chip antenna module 100f according to the embodiment may have a shape of a guide ring surrounding the outer circumference of the chip antenna module 100 f.

As the size of the solder layer 140a/140e/140f increases, the bonding force of the solder layer 140a/140e/140f to the connection member may become strong. Accordingly, the shapes of the

solder layers

140a, 140e, and 140f may be determined based on the characteristics of the

chip antenna modules

100a, 100e, and 100f (e.g., the total number of arrangements, the total number of patch antenna patterns, and the total number of via holes). For example, the

solder layers

140a, 140e, and 140f may have a cylindrical shape.

Fig. 5A is a perspective view illustrating the arrangement of the chip-

type antenna modules

100a, 100b, 100c, and 100d according to the embodiment.

Referring to fig. 5A, the

chip antenna modules

100a, 100b, 100c, and 100d may be arranged in a [1 × n ] structure, where n is a natural number.

The space between adjacent ones of the chip-

type antenna modules

100a, 100b, 100c, and 100d may be formed using air or an encapsulant having a dielectric constant lower than that of each of the dielectrics in the chip-

type antenna modules

100a, 100b, 100c, and 100 d.

A side surface of each of the

chip antenna modules

100a, 100b, 100c, and 100d may serve as a boundary condition with respect to RF signals. Accordingly, when the

chip antenna modules

100a, 100b, 100c, and 100d are arranged spaced apart from each other, electromagnetic isolation with respect to each of the

chip antenna modules

100a, 100b, 100c, and 100d may be improved.

Fig. 5B is a perspective view showing an integrated chip antenna module 100abcd in which the chip antenna module is integrated.

Referring to fig. 5B, the integrated chip antenna module 100abcd according to an embodiment may have a structure in which the chip antenna module shown in fig. 1A through 5A is integrated.

That is, the first dielectric layer may be configured as a single first dielectric layer overlapping each of the first patch antenna patterns according to design. The first patch antenna patterns may be arranged in parallel with each other in the integrated chip antenna module 100abcd to overlap the

coupling patch patterns

115a, 115b, 115c, and 115d in the Z direction.

Accordingly, the overall size of the integrated chip antenna module 100abcd may be reduced.

The electromagnetic interference provided by the first feed vias (e.g., the

first feed vias

121a and 121b) with each other may be reduced by the shielded via (e.g., the shielded via 130a) as described above. Accordingly, the integrated chip antenna module 100abcd may have a further reduced size while preventing deterioration of antenna performance caused by size reduction.

Fig. 6A is a plan view illustrating end fire antennas ef1, ef2, ef3, and ef4 included in the connection member 200-1 disposed under the chip

type antenna modules

100a, 100b, 100c, and 100d according to an embodiment.

Referring to fig. 6A, the connection member 200-1 may include end fire antennas ef1, ef2, ef3, and ef4 arranged in parallel to the chip

type antenna modules

100a, 100b, 100c, and 100d, and may form a radiation pattern of an RF signal in a horizontal direction (e.g., X-direction and/or Y-direction).

Each of the end-fire antennas ef1, ef2, ef3, and ef4 includes an end-fire antenna pattern 210a and a power feed line 220a, and may further include a guide pattern 215 a.

The

chip antenna module

100a, 100b, 100c, 100d includes a shielding via arranged to surround the first feeding via, and thus electromagnetic isolation with respect to the endfire antennas ef1, ef2, ef3, and ef4 is improved. Accordingly, the gains of the

chip antenna modules

100a, 100b, 100c, and 100d may be further improved.

Fig. 6B is a plan view illustrating end fire antennas ef5, ef6, ef7, and ef8 provided in the connection member 200-2 disposed under the chip

type antenna modules

100a, 100B, 100c, and 100d according to an embodiment.

Referring to fig. 6B, the connection member 200-2 may include end fire antennas ef5, ef6, ef7, and ef8 arranged in parallel to the chip

type antenna modules

100a, 100B, 100c, and 100d, and thus may form a radiation pattern of an RF signal in a horizontal direction (e.g., X-direction and/or Y-direction).

Each 430 of endfire antennas ef5, ef6, ef7, and ef8 may include a radiator 431 and a dielectric 432.

Referring to fig. 7A, a first dielectric layer 151a and a third dielectric layer 151b may be provided, a through hole TH may be formed in the first dielectric layer 151a, and a conductive paste may be applied to or filled in the through hole TH to form a first feed via 121a, a second feed via 122a, and a shield via 130 a.

Referring to fig. 7B, a first patch antenna pattern 111a is formed by printing a pattern in a conductive paste state on an upper surface of the first dielectric layer 151a and drying the pattern. The second patch antenna pattern 112a is formed by printing a pattern in a conductive paste state on the lower surface of the third dielectric layer 151b and drying the pattern. The coupling patch pattern 115a is formed by printing a pattern in a conductive paste state on the upper surface of the third dielectric layer 151b and drying the pattern. The solder layer 140a is formed on the lower surface of the first dielectric layer 151a by printing a layer in a conductive paste state and drying the layer. Then, a second dielectric layer 152a may be formed on an upper surface of the first dielectric layer 151a, and a third dielectric layer 151b may be pressed on the second dielectric layer 152 a.

Referring to fig. 7C, a plurality of first patch antenna patterns 111a and solder layers 140a may be formed on a single first dielectric layer 151a, and the first dielectric layer 151a may be Cut along cutting lines Cut1 and Cut 2. Accordingly, a plurality of chip antenna modules can be simultaneously manufactured.

Referring to fig. 7D, the upper surface and/or the lower surface of the third dielectric layer 151b may have a groove. For the sake of accuracy, the grooves may be formed using laser machining, but are not limited to being formed using laser machining.

The second patch antenna pattern 112a and/or the coupling patch pattern 115a may be printed and dried in the groove of the third dielectric layer 151 b. A groove may be formed in the first dielectric layer 151a according to design.

Accordingly, since process variations among the first patch antenna pattern 111a, the second patch antenna pattern 112a, and/or the coupling patch pattern 115a may become small and a spacing distance between the first patch antenna pattern 111a, the second patch antenna pattern 112a, and/or the coupling patch pattern 115a may be more precisely optimized, reliability of antenna performance (e.g., gain and/or bandwidth) may be further increased.

Fig. 8A is a plan view illustrating a first ground plane 201a of a connection member included in an electronic device according to an embodiment. Fig. 8B is a plan view illustrating the power feeding line 221a located below the first ground plane 201a of fig. 8A. Fig. 8C is a plan view showing the wiring via and the second ground plane 203a located under the feeder line of fig. 8B. Fig. 8D is a plan view illustrating an IC arrangement and an end-fire antenna located below the second ground plane 203a of fig. 8C.

Referring to fig. 8A to 8D, the feed via 120a corresponds to the first and second feed vias described above in common, and the chip-type antenna module may be arranged in a horizontal direction (e.g., X-direction and/or Y-direction).

Referring to fig. 8A, the first ground plane 201a may have a through hole through which the feed via 120a passes, and may electromagnetically shield between the patch antenna patterns (e.g., the first and second

patch antenna patterns

111a and 112a) and the feed line. The peripheral vias 185a may extend toward the upper side (e.g., Z-direction) and may be connected to the second solder layer 180a described above.

Referring to fig. 8B, the wiring ground plane 202a may surround at least a portion of each of the end-fire antenna feed line 220a and the feed line 221 a. The end-fire antenna feed line 220a may be electrically connected to the second routing via 232a, and the feed line 221a may be electrically connected to the first routing via 231 a. The wiring ground plane 202a may electrically shield between the end-fire antenna feed line 220a and the feed line 221 a. One end of the endfire antenna feed line 220a may be connected to the second feed via 211 a.

Referring to fig. 8C, the second ground plane 203a may have a through hole through which each of the first and

second routing vias

231a and 232a passes, and may have a coupling ground pattern 235 a. The second ground plane 203a may electrically shield the feed line from the IC310a (fig. 8D).

Referring to fig. 8D, the IC ground plane 204a may have a through hole through which each of the first and

second routing vias

231a and 232a passes. The IC310a may be disposed below the IC ground plane 204a and may be electrically connected to the first and

second routing vias

231a and 232 a. The end-fire antenna pattern 210a and the guide pattern 215a may be disposed at substantially the same vertical height as that of the IC ground plane 204a (e.g., in the Z-direction).

The IC ground plane 204a may be formed as a ground for the IC310a and/or passive components (used in the circuitry of the IC310a and/or passive components). Depending on the design, the IC ground plane 204a may provide a transmission path for power and signals used in the IC310a and/or passive components. Accordingly, the IC ground plane 204a may be electrically connected to the IC310a and/or passive components.

The routing ground plane 202a, the second ground plane 203a, and the IC ground plane 204a may have a concave shape to form a cavity. Therefore, the end-fire antenna pattern 210a may be disposed closer to the IC ground plane 204a than in an embodiment in which no cavity is formed.

The vertical relationship and shape of the routing ground plane 202a, the second ground plane 203a, and the IC ground plane 204a may vary according to design.

Fig. 9A and 9B are side views illustrating a structure of a portion illustrated in fig. 8A to 8D and an element located below the portion according to an embodiment.

Referring to fig. 9A, the chip antenna module according to the embodiment may include at least a portion of the connection member 200, the IC310, the adhesive member 320, the electrical connection structure 330, the encapsulant 340, the passive component 350, and the core member 410.

The connection member 200 may have a structure similar to that described above with reference to fig. 1A to 7C.

The IC310 is the same as described above, and may be disposed below the connection member 200. The IC310 may be electrically connected to a wiring of the connection member 200 to transmit or receive an RF signal, and may be electrically connected to a ground plane of the connection member 200 to be grounded. For example, the IC310 may generate a signal converted by performing at least a part of frequency conversion, amplification, filtering, phase control, and power generation.

The adhesive member 320 may bond the IC310 and the connection member 200 to each other.

The electrical connection structure 330 may electrically connect the IC310 and the connection member 200 to each other. For example, the electrical connection structure 330 may have a structure such as a solder ball, a pin, a pad, and the like. The electrical connection structure 330 has a melting point lower than that of the wiring of the ground plane of the connection member 200, and thus the IC310 and the connection member 200 can be electrically connected to each other by using a process of a low melting point.

Encapsulant 340 may encapsulate at least a portion of IC310, thereby improving the heat dissipation performance and impact protection performance of IC 310. For example, the encapsulant 340 may be provided as a photosensitive encapsulant (PIE), ABF (Ajinomoto build-up film), Epoxy Molding Compound (EMC), or the like.

The passive components 350 may be disposed on the lower surface of the connection member 200 and may be electrically connected to the wiring and/or the ground plane of the connection member 200 through the electrical connection structure 330. For example, passive components 350 may include at least a portion of a capacitor (e.g., a multilayer ceramic capacitor (MLCC)), an inductor, and a chip resistor.

The core means 410 may be disposed under the connection means 200 and may be electrically connected to the connection means 200 to receive an Intermediate Frequency (IF) signal or a baseband signal from an external source to transmit the IF signal or the baseband signal to the IC310, or to receive the IF signal or the baseband signal from the IC310 to transmit the IF signal or the baseband signal to the external source. Here, the frequency of the RF signal (e.g., 24GHz, 28GHz, 36GHz, 39GHz, and 60GHz) may be greater than the frequency of the IF signal (e.g., 2GHz, 5GHz, 10GHz, etc.).

For example, the core means 410 transmits or receives an IF signal or a baseband signal to or from the IC310 through a wiring included in the IC ground plane of the connection means 200. Since the first ground plane of the connection member 200 is disposed between the IC ground plane and the wiring, the IF signal or the baseband signal and the RF signal may be electrically isolated from each other in the chip antenna module.

Referring to fig. 9B, the chip antenna module according to the embodiment may include at least a portion of the shield member 360, the connector 420, and the chip endfire antenna 430.

The shielding member 360 is disposed under the connection member 200, and may be disposed to define the IC310 together with the connection member 200. For example, the shielding member 360 may be disposed to cover (e.g., conformally shield) the IC310 and the passive components 350, or may be disposed to cover (e.g., compartment shield) each of the IC310 and the passive components 350. For example, the shielding member 360 has a hexahedral shape with one surface opened, and may have a hexahedral receiving space by being combined with the connection member 200. The shielding member 360 is formed using a material having high conductivity, such as copper, to have a short skin depth (skin depth), and may be electrically connected to the ground plane of the connection member 200. Accordingly, the shielding member 360 may reduce electromagnetic noise received by the IC310 and the passive components 350.

The connector 420 may have a connection structure of a cable (e.g., a coaxial cable) or a flexible PCB, may be electrically connected to the IC ground plane of the connection member 200, and may perform a similar function to that of the core member 410 described above. That is, the connector 420 may receive the IF signal, the baseband signal, and/or the power from the cable, or may provide the IF signal and/or the baseband signal to the cable.

The chip endfire antenna 430 may transmit or receive RF signals to support the chip antenna module. For example, the chip endfire antenna 430 may include: a dielectric block having a dielectric constant greater than that of the insulating layer; and electrodes disposed on both sides of the dielectric block. One of the electrodes may be electrically connected to the wiring of the connection member 200, and the other of the electrodes may be electrically connected to the ground plane of the connection member 200.

Referring to fig. 10A, a chip antenna module including a chip antenna pattern 100g may be disposed adjacent to a boundary of a side surface of an electronic device 700g on a set board 600g of the electronic device 700 g.

The electronic device 700g may be a smart phone, a Personal Digital Assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, etc., but is not limited to the foregoing examples.

A communication module 610g and a baseband circuit 620g may also be provided on the gang board 600 g. The chip antenna module may be electrically connected to the communication module 610g and/or the baseband circuit 620g through a coaxial cable 630 g.

The communication module 610g may include at least a portion of the following chips for performing digital signal processing: a memory chip such as a volatile memory (e.g., a Dynamic Random Access Memory (DRAM)), a nonvolatile memory (e.g., a Read Only Memory (ROM)), a flash memory, or the like; an application processor chip such as a central processing unit (e.g., Central Processing Unit (CPU)), a graphics processor (e.g., image processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and logic chips such as analog-to-digital converters (ADCs), Application Specific Integrated Circuits (ASICs), and the like.

The baseband circuit 620g may generate a baseband signal by performing analog-to-digital conversion, amplification for analog signals, filtering, and frequency conversion. The baseband signal from the input and output of the baseband circuit 620g may be transmitted to the antenna module through a cable.

For example, baseband signals may be transmitted to the IC through electrical connection structures, core vias, and wiring. The IC may convert the baseband signal to an RF signal in the millimeter wave (mmWave) band.

Referring to fig. 10B, a chip antenna module and an antenna module, each including a chip antenna pattern 100i, may be disposed adjacent to a corresponding side of a polygonal electronic device 700i on a group board 600i of the electronic device 700i, and a communication module 610i and a baseband circuit 620i may also be disposed on the group board 600 i. The chip antenna module and the antenna module may be electrically connected to the communication module 610i and/or the baseband circuit 620i through a coaxial cable 630 i.

Referring to fig. 10A and 10B, in the chip antenna module, regions where no pattern, via hole, plane, bar, line, and electrical connection structure are disposed may be filled with

dielectric layers

1140g and 1140i, respectively.

For example, the dielectric layer 1140g/1140i may be provided as FR4, Liquid Crystal Polymer (LCP), low temperature co-fired ceramic (LTCC), thermosetting resin such as epoxy resin, thermoplastic resin such as polyimide resin, resin in which thermosetting resin or thermoplastic resin is mixed with inorganic filler or impregnated in a core material such as glass fiber (or glass cloth or glass fabric) together with inorganic filler (e.g., prepreg, ABF, FR-4, BT, etc.), photosensitive dielectric (PID) resin, Copper Clad Laminate (CCL), glass-based insulating material or ceramic-based insulating material, or the like.

The patterns, vias, planes, bars, lines, and electrical connection structures disclosed herein may include a metal material (e.g., such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc.) and may be formed using a plating method such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering, subtractive, additive, semi-additive process (SAP), modified semi-additive process (MSAP), etc., but are not limited to the foregoing materials and formation methods.

The RF signals disclosed herein may include signals based on protocols such asNumber: wireless fidelity (Wi-Fi) (institute of electrical and electronics engineers (IEEE)802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), evolution data optimized (Ev-DO), high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), Enhanced Data GSM Environment (EDGE), global system for mobile communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), bluetooth (r), wireless telecommunications systems, and wireless communication systems

The 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the above protocols, but are not limited to these example protocols.

As described above, according to the embodiments, the chip antenna module and the electronic device including the chip antenna module provide a transmission and reception device operable in frequency bands different from each other while improving antenna performance (e.g., gain, bandwidth, directivity, transmission and reception rates, etc.) or easily achieving miniaturization.

The communication module 610g in fig. 10A and the communication module 610i in fig. 10B, which perform the operations described in the present application, are implemented by hardware components configured to perform the operations described in the present application performed by the hardware components. Examples of suitable hardware components that may be used to perform the operations described herein include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described herein. In other examples, one or more of the hardware components that perform the operations described herein may be implemented by computing hardware, such as by one or more processors or computers. A processor or computer may be implemented by one or more processing elements (such as an array of logic gates, a controller, and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software for execution by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an Operating System (OS) and one or more software applications running on the OS, to perform the operations described herein. Hardware components may also access, manipulate, process, create, and store data in response to execution of instructions or software. For simplicity, the singular terms "processor" or "computer" may be used in the description of the examples described in this application, but in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or processors and controllers, may implement a single hardware component or two or more hardware components. The hardware components may have any one or more of a variety of different processing configurations, examples of which include single processors, independent processors, parallel processors, Single Instruction Single Data (SISD) multiprocessing, Single Instruction Multiple Data (SIMD) multiprocessing, Multiple Instruction Single Data (MISD) multiprocessing, and Multiple Instruction Multiple Data (MIMD) multiprocessing.

Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions, or any combination thereof, that individually or collectively instruct or configure one or more processors or computers to operate as a machine or special purpose computer to perform the operations performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by one or more processors or computers (such as machine code produced by a compiler). In another example, the instructions or software comprise higher level code that is executed by one or more processors or computers using an interpreter. The instructions or software can be written using any programming language based on the block diagrams and flow diagrams illustrated in the figures and the corresponding descriptions in the specification, which disclose algorithms for performing the operations performed by the hardware components and methods as described above.

Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and perform the methods and any associated data, data files, and data structures as described above may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer readable storage media include read-only memory (ROM), random-access memory (RAM), flash memory, CD-ROM, CD-R, CD + R, CD-RW, CD + RW, DVD-ROM, DVD-R, DVD + R, DVD-RW, DVD + RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, magnetic tape, floppy disk, magneto-optical data storage, hard disk, solid-state disk, and any other device, the above-described devices are configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner, and provide instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over a network of networked computer systems such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by one or more processors or computers.

While the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of features or aspects in each example will be understood to be applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order and/or if components in the described systems, architectures, devices, or circuits are combined in a different manner and/or replaced or added by other components or their equivalents. Therefore, the scope of the present disclosure is defined not by the detailed description but by the claims and their equivalents, and all modifications within the scope of the claims and their equivalents are to be construed as being included in the present disclosure.

Claims

1. A chip antenna module comprising:

a first dielectric layer;

a solder layer disposed on a lower surface of the first dielectric layer;

a first patch antenna pattern disposed on an upper surface of the first dielectric layer and having a through hole;

a second patch antenna pattern spaced apart from an upper surface of the first patch antenna pattern and having an area smaller than that of the first patch antenna pattern;

a first feed via extending through the first dielectric layer from the lower surface of the first dielectric layer and electrically connected to the first patch antenna pattern;

a second feed via extending from the lower surface of the first dielectric layer through the first dielectric layer and the through hole and electrically connected to the second patch antenna pattern; and

a shielded via extending from the lower surface of the first dielectric layer through the first dielectric layer, electrically connected to the first patch antenna pattern, and arranged to at least partially surround the second feed via.

2. The chip antenna module according to claim 1, wherein the second feeding via hole includes two or more second feeding via holes, and

wherein the shielded vias are arranged to at least partially surround the two or more second feed vias, respectively.

3. The chip antenna module as claimed in claim 1, wherein the first feeding via hole is offset from a center of the first chip antenna pattern, and

wherein the second feeding via is disposed closer to the center of the first patch antenna pattern than the first feeding via.

4. The chip antenna module according to claim 1, further comprising:

a second dielectric layer disposed between the first patch antenna pattern and the second patch antenna pattern,

wherein the dielectric constant of the second dielectric layer is lower than the dielectric constant of the first dielectric layer.

5. The chip antenna module as claimed in claim 4, wherein a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer.

6. The chip antenna module according to claim 4, wherein the second dielectric layer comprises a polymer, and

wherein the first dielectric layer comprises a ceramic.

7. The chip antenna module according to claim 4, further comprising:

a third dielectric layer disposed over the second dielectric layer,

wherein the dielectric constant of the third dielectric layer is higher than the dielectric constant of the second dielectric layer.

8. The chip antenna module as claimed in claim 7, wherein a thickness of the third dielectric layer is greater than a thickness of the second dielectric layer and less than a thickness of the first dielectric layer.

9. The chip antenna module according to claim 8, further comprising:

a coupling patch pattern disposed on an upper surface of the third dielectric layer.

10. The chip antenna module according to claim 1, further comprising:

a third dielectric layer disposed over the first dielectric layer,

wherein a lower surface of the third dielectric layer forms an arrangement space of the second patch antenna pattern.

11. The chip antenna module according to claim 10, further comprising:

a second dielectric layer disposed between the first dielectric layer and the third dielectric layer; and

an air cavity surrounded by the second dielectric layer.

12. The chip antenna module according to claim 1, wherein the first patch antenna pattern includes two or more first patch antenna patterns, and

wherein the first dielectric layer is a single first dielectric layer overlapping each of the two or more first patch antenna patterns.

13. An electronic device, comprising:

a chip antenna module;

a connection member including an upper surface to which the solder layer of each of the chip antenna modules is electrically connected; and

an integrated circuit electrically connected to a lower surface of the connection member,

wherein at least one of the chip antenna modules comprises:

a first dielectric layer;

a solder layer disposed on a lower surface of the first dielectric layer;

14. The electronic device of claim 13, wherein the connecting member further comprises:

a feed line electrically connecting the first feed via to the integrated circuit;

a routing ground plane at least partially surrounding the feed line; and

a first ground plane disposed between the wiring ground plane and the chip antenna module.

15. The electronic device of claim 14, wherein the connecting member further comprises:

a second solder layer disposed above the first ground plane and electrically connected to the solder layer; and

a peripheral via connecting the second solder layer to the first ground plane.

16. The electronic device of claim 13, wherein the connecting member further comprises:

a first ground plane disposed below the chip antenna module; and

an endfire antenna, at least a portion of the endfire antenna not overlapping and positioned below the first ground plane.

17. A chip antenna module comprising:

a first dielectric layer;

a solder layer disposed on a lower surface of the first dielectric layer;

a connection member including a ground plane connected to the solder layer;

a first patch antenna pattern disposed on an upper surface of the first dielectric layer and configured to transmit and receive signals in a first frequency band;

a second patch antenna pattern disposed above the first patch antenna pattern and configured to transmit and receive a signal in a second frequency band, the second frequency band being different from the first frequency band;

a first feeding via extending through the first dielectric layer, wherein one end of the first feeding via is connected to a lower surface of the first patch antenna pattern, and the other end of the first feeding via is connected to the connection member;

a second feeding via hole extending through the first dielectric layer and the through hole in the first patch antenna pattern, wherein one end of the second feeding via hole is connected to a lower surface of the second patch antenna pattern, and the other end of the second feeding via hole is connected to the connection member; and

and a shielded via hole at least partially surrounding the second feeding via hole in the first dielectric layer, wherein one end of each of the shielded via holes is connected to a lower surface of the first patch antenna pattern, and the other end of the shielded via hole is connected to the connection member.

18. The chip antenna module as claimed in claim 17, further comprising a third dielectric layer disposed on an upper surface of the second chip antenna pattern.

19. The chip antenna module according to claim 18, further comprising a second dielectric layer disposed between the first and third dielectric layers and having a dielectric constant lower than that of the first and third dielectric layers.

20. The chip antenna module as claimed in claim 17, wherein the first feeding via is offset from a center of the first patch antenna pattern by a distance greater than a distance by which the second feeding is offset from the center of the first patch antenna pattern.