CN111725322A - Graphene field effect transistor and preparation method and application method thereof - Google Patents

Graphene field effect transistor and preparation method and application method thereof Download PDF

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CN111725322A
CN111725322A CN201910813317.XA CN201910813317A CN111725322A CN 111725322 A CN111725322 A CN 111725322A CN 201910813317 A CN201910813317 A CN 201910813317A CN 111725322 A CN111725322 A CN 111725322A
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graphene
type
effect transistor
field effect
conductive region
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王彩露
叶力
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

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Abstract

The invention discloses a graphene field effect transistor and a preparation method and an application method thereof, and relates to the technical field of semiconductor devices. According to the invention, through n-type doping and p-type doping of the graphene conductive channel layer, the band gap of the graphene can be effectively opened, so that the graphene has the property of a semiconductor, and a field effect transistor can be formed.

Description

Graphene field effect transistor and preparation method and application method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a graphene field effect transistor, and a preparation method and an application method of the graphene field effect transistor.
Background
At present, most of the integrated circuits are designed based on silicon semiconductor devices, and with the development of technology, the device size in the field of integrated circuits is continuously reduced, and silicon materials are gradually approaching the limit of processing thereof, and higher requirements are put forward on the performance of integrated circuits, such as speed, etc., and new material systems with higher carrier mobility and new technical means need to be developed to further extend moore's law and surpass the silicon material systems, so as to promote the development of integrated circuit technology.
Graphene (Graphene) is a carbon atom sp2The two-dimensional plane structure of hexagonal honeycomb lattice is formed by orbital hybridization, the unique electrical characteristics of graphene are derived from the special electronic energy band structure of graphene, and intrinsic graphene has very high carrier mobility, and the value of the intrinsic graphene is up to 2000cm2v-1s-1The carrier mobility of the silicon material is about 10 times of that of the current silicon material. Since the successful development of graphene in 2004, the research of graphene devices has made great progress. Because of its advantages of high carrier mobility, thermal conductivity, saturation velocity, and controllable forbidden band width, etc., and its film form is compatible with the current silicon planar process and can be integrated on a large scale, it may become one of the new Semiconductor materials of generation exceeding and replacing silicon-based Complementary Metal Oxide Semiconductor (CMOS).
One of the most valuable fields of application of graphene is field effect transistors. The transistor manufactured by utilizing the graphene has the advantages of small volume, low power consumption and low requirement on working environment, and is easy to design into various structures. However, since graphene is a zero band gap material, its fermi energy is linearly distributed, and its energy band diagram is shown in fig. 1, it is not suitable for direct application to a transistor. To apply graphene to a field effect transistor, the bandgap of the graphene needs to be turned on. A common method is to prepare a graphene nanoribbon, but the electrical property of the graphene nanoribbon is easily affected by edge chirality and an adsorbed substance, so that the property is unstable; in addition, the process for preparing the graphene nanoribbon has high requirements, which greatly limits the application of the graphene nanoribbon.
Graphene Field Effect Transistors (GFETs) in the prior art mainly have a structure of a bottom gate Graphene Field Effect Transistor, a top gate Graphene Field Effect Transistor, a double gate Graphene Field Effect Transistor, a suspended Graphene Field Effect Transistor, and the like. In the existing research, single-layer or few-layer graphene is used as an active layer, when voltage is applied to a gate electrode, the position distribution of carriers in the graphene is only changed, so that a band gap with a certain size is generated, and only the carrier concentration and the mobility are changed to a certain extent, so that the on-off ratio is very small, even if the gate voltage reaches tens of volts, the on-off ratio does not exceed 3, the output characteristic is linear, the on-off control of a logic circuit cannot be effectively performed through the gate voltage, and the performance of a device is greatly influenced.
In view of the above, it is necessary to provide a graphene field effect transistor, a method for manufacturing the same, and a method for applying the same to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a graphene field effect transistor, a preparation method and an application method thereof, which are used for overcoming the technical problem that the graphene field effect transistor in the prior art cannot effectively control the on or off of a logic circuit through the voltage of a gate electrode.
The invention is realized by the following technical scheme:
the invention provides a graphene field effect transistor which comprises a substrate, wherein a first conductive region, a second conductive region and a third conductive region are arranged on the substrate, and the second conductive region is positioned between the first conductive region and the third conductive region; the first and third conductive regions are each formed of first and second conductivity type doped graphene, and the second conductive region is formed of second conductivity type doped graphene.
Further, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.
Further, the p-type doping or the n-type doping of the graphene adopts a lattice doping or adsorption doping method.
Further, the substrate is a Si substrate or Si/SiO2A substrate, wherein the Si substrate is formed of p-type doped or n-type doped Si.
Further, the graphene is of a single-layer or multi-layer structure; the first conductive region is formed with a source electrode, the second conductive region is formed with a gate electrode, and the third conductive region is formed with a drain electrode.
Correspondingly, the invention provides a preparation method of a graphene field effect transistor, which is used for preparing the graphene field effect transistor and comprises the following steps:
providing a substrate, and forming a graphene channel layer on the substrate;
performing first conduction type doping on a first conduction region and a third conduction region at two ends of the graphene channel layer, and performing second conduction type doping on a second conduction region in the middle of the channel layer;
preparing a source electrode on the first conductive region and a drain electrode on the third conductive region;
and forming a gate electrode on the second conductive region to form the graphene field effect transistor.
Further, a mechanical stripping method, a graphene oxide chemical reduction method, an epitaxial growth method or a chemical vapor deposition method is adopted for forming the graphene channel layer on the substrate; the graphene is of a single-layer or multi-layer structure.
Further, the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.
Further, p-type doping or n-type doping is respectively carried out on the graphene channel layer in a mask mode; the p-type doping or the n-type doping of the graphene is formed by a lattice doping or adsorption doping method.
Correspondingly, the invention provides an application method, which applies the graphene field effect transistor to the field of integrated circuits.
The implementation of the invention has the following beneficial effects:
according to the graphene field effect transistor and the preparation method thereof, the band gap of the graphene can be effectively opened through n-type doping and p-type doping of the graphene conductive channel layer, so that the graphene has the property of a semiconductor, the field effect transistor can be formed, the process flow is simple, compared with the prior art, the graphene field effect transistor can control the formation and disappearance of the channel through the voltage of a gate electrode, a high on-off ratio can be realized, the gate control capability is improved, a three-terminal device with a switching function can be prepared, the on-off of a logic circuit is realized, the static power consumption of the logic circuit is reduced, and the graphene field effect transistor has a good application prospect in the field of integrated circuits.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions and advantages of the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of graphene energy bands in the background art;
fig. 2 is a schematic structural diagram of a graphene field-effect transistor according to embodiment 1 of the present invention;
fig. 3 is a top view of a graphene field effect transistor according to embodiment 1 of the present invention;
fig. 4 is another schematic structural diagram of a graphene field-effect transistor according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a N atom and B atom doped structure of a graphene layer according to example 1 of the present invention;
fig. 6 is another schematic structural diagram of a graphene field-effect transistor according to embodiment 1 of the present invention;
fig. 7 is another schematic structural diagram of a graphene field-effect transistor according to embodiment 1 of the present invention;
fig. 8 is a flowchart of a method for manufacturing a graphene fet according to embodiment 2 of the present invention;
FIG. 9 is a schematic structural view of a magnetic tunnel junction of embodiment 3 of the present invention;
FIG. 10 is a block diagram of a magnetic random access memory according to embodiment 3 of the present invention.
Wherein the reference numerals correspond to: 1-substrate, 2-first conductive region, 3-third conductive region, 4-second conductive region, 5-source electrode, 6-drain electrode, 7-dielectric layer and 8-gate electrode; s-source electrode, G-gate electrode, D-drain electrode, WL-word line, SL-source line and BL-bit line.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following examples. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms first, second, third and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.
Example 1
The embodiment provides a graphene field effect transistor, which comprises a substrate 1, wherein a first conductive region 2, a second conductive region 4 and a third conductive region 3 are arranged on the substrate 1, and the second conductive region 4 is located between the first conductive region 2 and the third conductive region 3; the first conductive region 2 and the third conductive region 3 are each formed of first conductive type-doped graphene, and the second conductive region 4 is formed of second conductive type-doped graphene.
In an alternative embodiment, the substrate 1 is Si/SiO2The first conductivity type of the substrate is n-type, the second conductivity type of the substrate is p-type, a structural schematic diagram of the formed graphene field effect transistor is shown in fig. 2, and a top view of the graphene field effect transistor is shown in fig. 3.
In an alternativeIn the embodiment (1), the substrate is Si/SiO2The structure of the graphene field effect transistor formed by the substrate with the first conductivity type being p-type and the second conductivity type being n-type is schematically shown in fig. 4.
In a specific embodiment, the first conductive region 2 is formed as a source region, the third conductive region 3 is formed as a drain region, and the second conductive region 4 is formed as a conductive channel. The source region and the drain region are formed by n-type doped graphene, and the conducting channel is formed by p-type doped graphene; alternatively, the source and drain regions are formed from p-type doped graphene and the conduction channel is formed from n-type doped graphene.
In this embodiment, the first conductive region 2 is formed with a source electrode 5, the third conductive region 3 is formed with a drain electrode 6, the second conductive region 4 is formed with a gate electrode 8, and a dielectric layer 7 is formed under the gate electrode 8.
It can be understood that the bottom gate graphene field effect transistor and the side gate graphene field effect transistor having similar structures to the graphene field effect transistor described above all belong to the protection scope of the technical solution of the present invention.
The graphene field effect transistor in the prior art cannot effectively control the on or off of a logic circuit through the voltage of a gate electrode, and the graphene field effect transistor is essentially different from the graphene field effect transistor in the prior art. According to the graphene field effect transistor, the n-type doping and the p-type doping of the graphene can effectively open the band gap of the graphene, so that the graphene has the property of a semiconductor, the n-type or p-type doped graphene is formed on the conductive channel layer, and the field effect transistor can be formed. In the aspect of gate voltage control channel, the high switching ratio and nonlinear output are realized. The graphene field effect transistor can control the formation and disappearance of a channel through the voltage of a gate electrode, can realize higher switching ratio, and improves the gate control capability, so that a three-terminal device with a switching function can be prepared, the on-off of a logic circuit is realized, and the static power consumption of the logic circuit is reduced.
In an alternative embodiment, the p-type doping or n-type doping of the graphene is performed by lattice doping or adsorption doping.
In a preferred embodiment, boron (B) atoms replace carbon in the graphene lattice to form p-type doped graphene, nitrogen (N) atoms replace carbon in the graphene lattice to form N-type doped graphene, and a schematic diagram of the N-atom and B-atom doping structure of graphene is shown in fig. 5.
In another alternative embodiment, the p-type doped graphene may also be formed by modifying tetrafluorotetracyanodimethylbenzoquinone on the surface of graphene; of course, in other embodiments, the graphene may be p-doped or n-doped by other methods as long as the same function can be achieved.
In this embodiment, the graphene has a single-layer or multi-layer structure.
In an alternative embodiment, the substrate 1 is a Si substrate, wherein the Si substrate is formed by p-type doped or n-type doped Si, and the structural schematic diagram of the graphene field effect transistor formed on the Si substrate is shown in fig. 6 and 7.
The working principle of the graphene field effect transistor is as follows: the graphene Field effect transistor of the embodiment has a structure similar to a conventional Metal-Oxide-Semiconductor Field effect transistor (MOSFET) structure, and also has a similar working principle. The core structure of the graphene field effect transistor is formed by overlapping three layers of materials, namely a conductor, an insulator and a doped semiconductor forming a tube substrate, and the core structure has the function of inducing carriers with the type opposite to the original doping type on the surface of the semiconductor to form a conductive channel. Taking the graphene field effect transistor in fig. 2 as an example for explanation, as a complete device, n-type doped graphene at two ends forms a source electrode 5 and a drain electrode 6 through ohmic contact with a metal conductor respectively. Due to the inherent symmetry in the structure, there is no physical difference between the first conductive region 2, which is the source region, and the third conductive region 3, which is the drain region. In this MOS transistor-like structure, the gate electrode 8 is a control electrode that controls the current flow in the channel between the drain 6 and the source 5. In the absence of any applied bias voltage, there are now two back-to-back diodes from the drain electrode 6 to the source electrode 5. The current that can flow between them is the reverse leakage current of the diode. No conductive channel is formed under the gate electrode 8. If the source electrode 5, drain electrode 6 and substrate 1 are grounded, a sufficiently high positive voltage is applied to the gate electrode 8 that, from an electrostatics point of view, will repel hole charges mobile in the p-type layer under the gate electrode 8 and attract electrons. When electrons are gathered to a certain concentration on the surface, the p-type layer under the gate electrode 8 becomes an N-type layer, namely an N-type inversion layer is presented, and the N-type inversion layer is communicated with the N-type diffusion layers at the two ends of the source and the drain to form a conductive channel taking the electrons as carriers. If there is a potential difference between the source electrode 5 and the drain electrode 6, a current will flow. The higher the positive voltage applied to the gate electrode 8, the higher the electron concentration in the channel region and the better the conduction.
Example 2
The embodiment provides a method for manufacturing a graphene field effect transistor, which is used for manufacturing the graphene field effect transistor in the above embodiment, and with reference to fig. 8, the method includes the following steps:
s1, providing a substrate 1, and forming a graphene channel layer on the substrate 1;
s2, carrying out first conduction type doping on a first conduction region 2 and a third conduction region 3 at two ends of the graphene channel layer, and carrying out second conduction type doping on a second conduction region 4 in the middle of the channel layer;
s3, preparing a source electrode 5 on the first conductive region 2, and a drain electrode 6 on the third conductive region 3;
and S4, forming a gate electrode 8 on the second conductive region 4 to form the graphene field effect transistor.
In an alternative embodiment, the substrate 1 is a Si substrate or Si/SiO2The substrate, wherein, the Si substrate is formed by P type doped or N type doped Si, and the P type doped or N type doped Si is prepared by adopting an atom diffusion or ion implantation method; Si/SiO2The substrate is prepared by preparing SiO on the Si layer2And (4) layer formation.
In an alternative embodiment, in step S2, the graphene channel layer is formed on the substrate 1 by using a mechanical lift-off method, a graphene oxide chemical reduction method, an epitaxial growth method, or a chemical vapor deposition method.
In an alternative embodiment, in step S2, the graphene is a single-layer or multi-layer structure.
In an alternative embodiment, in step S2, the first conductivity type is n-type and the second conductivity type is p-type; alternatively, the first conductivity type is p-type and the second conductivity type is n-type.
In an optional embodiment, in step S2, p-type doping or n-type doping is performed on the graphene channel layer by means of a mask respectively; the p-type doping or the n-type doping of the graphene is formed by a lattice doping or an adsorption doping method.
In a preferred embodiment, the p-type doped graphene is formed by carbon in the lattice of graphene with boron (B) atom substitution, and the N-type doped graphene is formed by carbon in the lattice of graphene with nitrogen (N) atom substitution. The graphene is doped with nitrogen and boron atoms by adopting modes of vapor deposition, arc discharge, plasma treatment, thermal annealing and the like, and the doping process conditions are controlled to adjust the atomic ratio of the doped nitrogen and boron atoms, so that the regulation and control of the size of the graphene band gap are realized. The method is simple and reliable, and has good compatibility with the whole process of the integrated circuit.
In another alternative embodiment, the p-type doped graphene can also be obtained by low-temperature deposition of tetrafluorotetracyanoquinodimethane molecules onto graphene in a high vacuum chamber; of course, in other embodiments, the graphene may be p-doped or n-doped by other methods as long as the same function can be achieved.
In a specific embodiment, the preparing the source electrode 5 on the first conductive region 2 and the drain electrode 6 on the third conductive region 3 in step S3 includes: a photoresist is applied to the doped graphene channel layer in step S2, a source electrode pattern and a drain electrode pattern are formed by exposure and development, and a metal layer is evaporated in the source electrode pattern and drain electrode pattern regions to form a source electrode 5 and a drain electrode 6.
In an alternative embodiment, the metal layer may be any one of Ti, Pb, Pd, Au; alternatively, a combination of metal materials of Pb/Au, Ni/Au, Sn/Au and Ti/Au is adopted, for example, the thickness of the bottom metal Pd is selected to be 20nm, and the thickness of the top metal Au is 80 nm.
In a specific embodiment, the forming of the gate electrode 8 on the second conductive region 4 in step S4 includes: depositing a high-dielectric-constant dielectric layer 7 on the second conductive region 4 of the channel layer, wherein the material of the dielectric layer 7 is SiO2、Si3N4、Al2O3、HfO2、TiO2、Y2O3Any one or more of; forming a metal layer of the gate electrode with reference to the metal layer used for the source or drain electrode, such as any one of Ti, Pb, Pd, and Au, or a combination of Pb/Au, Ni/Au, Sn/Au, and Ti/Au metal materials, with a thickness of about 1nm to 10nm, for example, depositing 10nm thick Al by Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD)2O3And finally forming the field effect transistor.
Example 3
The embodiment provides an application method, which applies the graphene field effect transistor in the above embodiment to the field of integrated circuits.
Taking Magnetic Random Access Memory (MRAM) as an example, the basic Memory bit of MRAM is a Magnetic Tunnel Junction (MTJ) formed by two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, wherein the Magnetic moment direction of one of the ferromagnetic layers is fixed, called the reference layer; the other layer has a variable direction of magnetic moment and is called the free layer, so the magnetization direction of the free layer can be parallel or anti-parallel to the magnetization direction of the reference layer, and referring to FIG. 9, the directions of the magnetic moments of the free and reference layers can be either parallel to the in-plane or perpendicular to the out-of-plane direction. Due to quantum tunneling, current can pass through the tunnel barrier layer in the device, and the MTJ device can be considered as a variable resistor whose resistance value depends on the magnetization direction of the variable magnetization layer. When the magnetic moment directions of the free layer and the reference layer are consistent, the resistance of the MTJ device presents a low resistance state, which can represent a logic state of "0"; when the magnetic moment directions of the free layer and the reference layer are opposite, the resistance of the MTJ device assumes a high resistance state, which may represent a logic state "1". The process of reading the magnetic random access memory is to measure the resistance of the storage bit component MTJ of the corresponding address. The process of writing into the magnetic random access memory is to pass a suitable current through the storage bit element MTJ of the corresponding address to flip (manipulate) the magnetic moment of the memory layer. The two different current directions from bottom to top and from top to bottom can respectively realize the overturning of the magnetic moments from parallel to antiparallel and from antiparallel to parallel.
The simplest basic memory unit of a magnetic random access memory includes an MTJ memory device and a switching device. The switching device is a three-terminal device having a switching function, the switching device is connected to a word line WL of the chip responsible for turning on or off this cell, and the MTJ and the switching device are connected in series and connected to a bit line BL and a source line SL. In the prior art, an MTJ and a CMOS transistor are generally connected in series as a basic unit of a memory, wherein the CMOS transistor is used as a three-terminal switching device. Referring to fig. 10, the graphene field effect transistor of the present invention may replace a CMOS transistor, and be used as a three-terminal switching device to control the on/off of the current on the MTJ device, and to realize the turning of the magnetic moment of the free layer, thereby realizing two logic states "0" and "1". The graphene field effect transistor in the embodiment can be prepared into a three-terminal device with a switching function, so that the on-off of the logic circuit is realized, and the static power consumption of the logic circuit is reduced, therefore, the graphene field effect transistor has a good application prospect in the field of integrated circuits.
The above embodiment of the invention has the following beneficial effects:
according to the graphene field effect transistor and the preparation method thereof, the band gap of the graphene can be effectively opened through n-type doping and p-type doping of the graphene conductive channel layer, so that the graphene has the property of a semiconductor, the field effect transistor can be formed, the process flow is simple, compared with the prior art, the graphene field effect transistor can control the formation and disappearance of the channel through the voltage of a gate electrode, a high on-off ratio can be realized, the gate control capability is improved, a three-terminal device with a switching function can be prepared, the on-off of a logic circuit is realized, the static power consumption of the logic circuit is reduced, and the graphene field effect transistor has a good application prospect in the field of integrated circuits.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (10)

1. The graphene field effect transistor is characterized by comprising a substrate (1), wherein a first conductive region (2), a second conductive region (4) and a third conductive region (3) are arranged on the substrate (1), and the second conductive region (4) is positioned between the first conductive region (2) and the third conductive region (3);
the first conductive region (2) and the third conductive region (3) are both formed from graphene doped with a first conductivity type, and the second conductive region (4) is formed from graphene doped with a second conductivity type.
2. The graphene field effect transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.
3. The graphene field effect transistor according to claim 2, wherein the p-type doping or the n-type doping of the graphene is a lattice doping or an adsorption doping method.
4. Graphene field-effect transistor according to claim 2, characterized in that the substrate (1) is a Si substrate or Si/SiO substrate2A substrate, wherein the Si substrate is formed of p-type doped or n-type doped Si.
5. The graphene field effect transistor according to claim 1, wherein the graphene is a single-layer or multi-layer structure; the first conductive region (2) is formed with a source electrode (5), the second conductive region (4) is formed with a gate electrode (8), and the third conductive region (3) is formed with a drain electrode (6).
6. A preparation method of a graphene field effect transistor, which is used for preparing the graphene field effect transistor as claimed in any one of claims 1 to 5, and is characterized by comprising the following steps:
providing a substrate (1), and forming a graphene channel layer on the substrate (1);
carrying out first conduction type doping on a first conduction region (2) and a third conduction region (3) at two ends of the graphene channel layer, and carrying out second conduction type doping on a second conduction region (4) in the middle of the channel layer;
-providing a source electrode (5) on said first conductive area (2) and a drain electrode (6) on said third conductive area (3);
and forming a gate electrode (8) on the second conductive region (4) to form the graphene field effect transistor.
7. The method for manufacturing a graphene field effect transistor according to claim 6, wherein a mechanical lift-off method, a chemical reduction method of graphene oxide, an epitaxial growth method or a chemical vapor deposition method is used for forming a graphene channel layer on the substrate (1); the graphene is of a single-layer or multi-layer structure.
8. The method for manufacturing a graphene field effect transistor according to claim 6, wherein the first conductivity type is n-type, and the second conductivity type is p-type; or, the first conductivity type is p-type, and the second conductivity type is n-type.
9. The method for preparing the graphene field effect transistor according to claim 8, wherein the graphene channel layer is doped p-type or n-type by means of a mask; the p-type doping or the n-type doping of the graphene is formed by a lattice doping or adsorption doping method.
10. An application method of the graphene field effect transistor according to any one of claims 1 to 5 in the field of integrated circuits.
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