CN111724848B - Operation circuit and operation method of resistive random access memory unit and integrated circuit - Google Patents
Operation circuit and operation method of resistive random access memory unit and integrated circuit Download PDFInfo
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- CN111724848B CN111724848B CN202010523027.4A CN202010523027A CN111724848B CN 111724848 B CN111724848 B CN 111724848B CN 202010523027 A CN202010523027 A CN 202010523027A CN 111724848 B CN111724848 B CN 111724848B
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0026—Bit-line or column circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
Abstract
The invention discloses an operating circuit, an operating method and an integrated circuit of a resistive random access memory unit, wherein the operating circuit at least comprises a resistive random access memory unit consisting of a transistor, a first resistive random access memory and a second resistive random access memory; one end of the first resistive random access memory and one end of the second resistive random access memory are connected to a source electrode of the transistor together, the other end of the first resistive random access memory is connected with a first source line, the other end of the second resistive random access memory is connected with a second source line, and the direction of the first source line is perpendicular to the direction of the second source line; the gate of the transistor is connected with a word line, and the word line is parallel to a first source line; the drain of the transistor is wired to be a bit line, which is parallel to the second source line.
Description
Technical Field
The present invention relates to semiconductor technologies, and in particular, to an operating circuit, an operating method, and an integrated circuit of a resistive random access memory cell.
Background
In the prior art, a Resistive Random Access Memory (RRAM cell) generally has a 1T1R structure, that is, a transistor (transistor) is used to control a Resistive Memory (i.e., a Resistive Memory).
The conventional 1T1R structure has a transistor that is shrunk with the shrinking of the process, so that the resistive random access memory cell cannot be further shrunk.
Disclosure of Invention
In order to effectively overcome the problems of the conventional 1T1R structure, embodiments of the present invention creatively provide an operation circuit, an operation method, and an integrated circuit of a resistive random access memory cell.
According to a first aspect of the present invention, there is provided an operation circuit of a resistance change memory unit, the operation circuit including at least a resistance change memory unit composed of one transistor, a first resistance change memory, and a second resistance change memory; one end of the first resistive random access memory and one end of the second resistive random access memory are connected to a source electrode of the transistor together, the other end of the first resistive random access memory is connected with a first source line, the other end of the second resistive random access memory is connected with a second source line, and the direction of the first source line is perpendicular to the direction of the second source line; the gate of the transistor is connected with a word line, and the word line is parallel to a first source line; the drain of the transistor is wired to be a bit line, which is parallel to the second source line.
According to an embodiment of the present invention, when the first resistance change memory is formed, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the first source line is a forming pulse voltage, and the second source line is in a floating state; when the second resistive random access memory is formed, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the second source line is a forming pulse voltage, and the first source line is in a floating state.
According to an embodiment of the present invention, when the first resistance change memory is set, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the first source line is a set pulse voltage, and the second source line is in a floating state; when the second resistance change type memory is set, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the second source line is a set pulse voltage, and the first source line is in a floating state.
According to an embodiment of the present invention, when the first resistance change memory is reset, the potential of the bit line is a reset pulse voltage, the potential of the word line is a word bit pulse voltage, the potential of the first source line is zero, and the second source line is in a floating state; when the second resistance random access memory is reset, the potential of the bit line is reset pulse voltage, the potential of the word line is word bit pulse voltage, the potential of the second source line is zero, and the first source line is in a floating state.
According to an embodiment of the present invention, when reading the resistance value of the first resistance change memory, the potential of the bit line is a read pulse voltage, the potential of the word line is a fixed voltage, the potential of the first source line is zero, and the potential of the second source line is a read pulse voltage; when the resistance value of the second resistance change type memory is read, the potential of the bit line is a read pulse voltage, the potential of the word line is a fixed voltage, the potential of the second source line is zero, and the potential of the first source line is a read pulse voltage.
According to an embodiment of the present invention, the operation circuit includes a plurality of resistance change memory cells; and or and logic operation is carried out on bit lines among the plurality of resistance change type memory units.
According to the second aspect of the present invention, there is also provided an operating method of a resistance change memory unit, the resistance change memory unit being composed of one transistor, a first resistance change memory, and a second resistance change memory; the operation method comprises the following steps: one end of the first resistance change type memory and one end of the second resistance change type memory are connected to a source electrode of the transistor together, the other end of the first resistance change type memory is connected with a first source line, the other end of the second resistance change type memory is connected with a second source line, and the direction of the first source line is vertical to the direction of the second source line; connecting gates of the transistors to word lines, the word lines being parallel to the first source line; and connecting the drain electrode of the transistor to a bit line, wherein the bit line is parallel to the second source line, and the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the transistor by utilizing the first source line and the second source line which are perpendicular to each other and an operation bias setting mode.
According to an embodiment of the present invention, the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor using the first source line and the second source line which are perpendicular to each other and an operation bias setting method, including: when the first resistive random access memory is subjected to a forming operation, setting the potential of the bit line to be zero, setting the potential of the word line to be a word bit pulse voltage, setting the potential of the first source line to be a forming pulse voltage, and setting the second source line to be a floating state; when the second resistance change type memory is subjected to a forming operation, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the second source line is set to a forming pulse voltage, and the first source line is set to a floating state.
According to an embodiment of the present invention, the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor using the first source line and the second source line which are perpendicular to each other and an operation bias setting method, including: when the first resistance change type memory is set, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the first source line is set to a set pulse voltage, and the second source line is set to a floating state; when the second resistance change memory is set, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the second source line is set to a set pulse voltage, and the first source line is set to a floating state.
According to an embodiment of the present invention, the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor using the first source line and the second source line which are perpendicular to each other and an operation bias setting method, including: when the first resistance change type memory is reset, setting the potential of the bit line as a reset pulse voltage, setting the potential of the word line as a word bit pulse voltage, setting the potential of the first source line as zero, and setting the second source line as a floating state; when the second resistance change type memory is reset, the potential of the bit line is set to be a reset pulse voltage, the potential of the word line is set to be a word bit pulse voltage, the potential of the second source line is set to be zero, and the first source line is set to be in a floating state.
According to an embodiment of the present invention, the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor using the first source line and the second source line which are perpendicular to each other and an operation bias setting method, including: when reading the resistance value of the first resistance change memory, setting the potential of the bit line as a read pulse voltage, the potential of the word line as a fixed voltage, the potential of the first source line as zero, and the potential of the second source line as a read pulse voltage; when reading the resistance value of the second resistance change memory, the potential of the bit line is set to a read pulse voltage, the potential of the word line is set to a fixed voltage, the potential of the second source line is set to zero, and the potential of the first source line is set to a read pulse voltage.
According to an embodiment of the invention, the method of operation further comprises: and carrying out AND or logic operation on bit lines of the plurality of resistive random access memory units aiming at an operation circuit comprising the plurality of resistive random access memory units.
According to the third aspect of the present invention, there is provided an integrated circuit, which at least includes several operating circuits of any one of the resistive random access memory cells.
The operation circuit, the operation method and the integrated circuit of the resistive random access memory unit in the embodiment of the invention comprise at least one resistive random access memory unit consisting of a transistor, a first resistive random access memory and a second resistive random access memory; one end of the first resistive random access memory and one end of the second resistive random access memory are connected to a source electrode of the transistor together, the other end of the first resistive random access memory is connected with a first source line, the other end of the second resistive random access memory is connected with a second source line, and the direction of the first source line is perpendicular to the direction of the second source line; the gate of the transistor is connected with a word line, and the word line is parallel to a first source line; the drain of the transistor is wired to be a bit line, which is parallel to the second source line. Therefore, the two resistive memories including the first resistive memory and the second resistive memory are simultaneously controlled by the transistor by utilizing the first source line and the second source line which are perpendicular to each other and an operation bias setting mode, so that the resistive memory unit can be further miniaturized along with the process miniaturization, and the product process is effectively improved.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 is a schematic diagram illustrating a composition structure of a resistive random access memory cell having a 1T1R structure in the related art;
FIG. 2 is a schematic diagram illustrating a composition structure of an operation circuit of a resistive random access memory cell according to an embodiment of the invention;
fig. 3 is a schematic diagram illustrating a bias setting manner of an operation circuit of a resistance change memory cell according to an embodiment of the invention during a forming and setting operation;
fig. 4 is a schematic diagram illustrating a bias setting manner of an operation circuit of a resistance change memory cell according to an embodiment of the invention during a reset operation;
fig. 5 is a schematic diagram illustrating a bias setting manner of an operating circuit of a resistance change memory cell according to an embodiment of the invention when reading a resistance value;
fig. 6 is a schematic diagram of an operation circuit of a resistance change memory unit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the integrated circuit of an embodiment of the present invention;
fig. 8 shows an implementation flow diagram of an operation method of the resistance change memory unit according to the embodiment of the invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Fig. 1 shows a schematic structural diagram of a resistive random access memory cell having a 1T1R structure in the related art.
Referring to fig. 1, the resistance change type memory cell of the related art 1T1R structure is composed of one transistor and one memory, in which a Source Line (SL) may be parallel to a Bit Line (BL) or a Word Line (WL). Specifically, at a SET (SET) operation, the resistive memory is switched from a high resistance state to a low resistance state; in a RESET (RESET) operation, switching the resistive memory device from a low resistance state to a high resistance state; in resistance value READ (READ), V is appliedREADOn the bit line, a read circuit determines "1" or "0". It is clear that only one resistor can be controlled by one transistor in the 1T1R structure.
The conventional 1T1R structure will shrink the transistor as the process shrinks. Although the driving capability of the transistor is enhanced, the driving capability of the transistor cannot catch up with the reduced amplitude due to the scaling, so that the resistive random access memory cell cannot be scaled further.
In order to effectively solve the problems of the existing 1T1R structure, the invention creatively provides a resistive random access memory unit with a 1T2R structure, namely, one transistor is used for simultaneously controlling two resistive random access memories, so that the resistive random access memory unit can be further miniaturized along with the process miniaturization.
FIG. 2 is a schematic diagram illustrating a composition structure of an operation circuit of a resistive random access memory cell according to an embodiment of the invention; fig. 3 is a schematic diagram illustrating a bias setting manner of an operation circuit of a resistance change memory cell according to an embodiment of the invention during a forming and setting operation; fig. 4 is a schematic diagram illustrating a bias setting manner of an operation circuit of a resistance change memory cell according to an embodiment of the invention during a reset operation; fig. 5 is a schematic diagram illustrating a bias setting manner of an operating circuit of a resistance change memory cell according to an embodiment of the invention when reading a resistance value; fig. 6 is a schematic diagram of an operation circuit of a combination of a plurality of resistive random access memory units according to an embodiment of the present invention.
Referring to fig. 2, an operating circuit of a resistance change memory unit according to an embodiment of the present invention at least includes a first resistance change memory R and a transistor THAnd a resistance change memory unit composed of a second resistance change memory Rv; wherein the first resistive random access memory RHIs connected to the source of the transistor T in common with one end of the second resistance change memory Rv, the first resistance change memory RHThe other end of the second resistance change type memory Rv is connected with a second source line SL _ V, and the direction of the first source line SL _ H and the direction of the second source line SL _ V are perpendicular to each other; the grid of the transistor T is connected with a word line WL which is parallel to the first source line SL _ H; the drain of the transistor T is connected to a bit line BL which is parallel to the second source line SL _ V.
The invention realizes that the first resistive random access memory R is simultaneously controlled by one transistor T by utilizing a first source line SL _ H and a second source line SL _ V which are perpendicular to each other and an operation bias setting modeHAnd the purpose of two resistive memories of the second resistive random access memory Rv.
Specifically, referring to fig. 3 to 5, the simultaneous control of the first resistance change memory R by one transistor T is realized by using the first source line SL _ H and the second source line SL _ V perpendicular to each other and the operation bias setting mannerHAnd a second resistance change memoryRv two resistor memory implementation.
Referring to fig. 3, in the first resistance change memory RHIn the Forming (Forming), the potential of the bit line BL is zero, the potential of the word line WL is the word pulse voltage VWL, and the potential of the first source line SL _ H is the Forming pulse voltage VFThe second source line SL _ V is in a floating state for RHForming (Forming); in the formation (Forming) of the second resistance change memory Rv, the potential of the bit line BL is zero, the potential of the word line WL is the word pulse voltage VWL, and the potential of the second source line SL _ V is the Forming pulse voltage VFThe first source line SL _ H is in a floating state to perform shaping (Forming) of Rv.
Similarly, referring to fig. 3, in the first resistance change type memory RHIn the SET (SET), the potential of the bit line BL is zero, the potential of the word line WL is the word pulse voltage VWL, and the potential of the first source line SL _ H is the SET pulse voltage VSETThe second source line SL _ V is in a floating state for RHSetting (SET); when the second resistance change memory Rv is SET (SET), the potential of the bit line BL is zero, the potential of the word line WL is the word pulse voltage VWL, and the potential of the second source line SL _ V is the SET pulse voltage VSETThe first source line SL _ H is in a floating state to SET Rv (SET).
Referring to fig. 4, in the first resistance change memory RHAt RESET (RESET), the potential of the bit line BL is a RESET pulse voltage VRESETThe potential of the word line WL is a word bit pulse voltage VWL, the potential of the first source line SL _ H is zero, and the second source line SL _ V is in a floating state to perform RHRESET (RESET); when the second resistance change memory Rv is RESET (RESET), the potential of the bit line BL is a RESET pulse voltage VRESETThe potential of the word line WL is a word bit pulse voltage VWL, the potential of the second source line SL _ V is zero, and the first source line SL _ H is in a floating state to RESET Rv (RESET).
Referring to fig. 5, in Reading (READ) the first resistance change memory RHThe potential of the bit line BL is the read pulse voltage V at the resistance value of (1)READThe potential of the word line WL is a fixed voltage VDD, the potential of the first source line SL _ H is zero, and the potential of the second source line SL _ V is a read pulse voltage VREADTo read out RHThe resistance value of (1); when Reading (READ) the resistance value of the second resistance change memory, the potential of the bit line BL is a READ pulse voltage VREADThe potential of the word line WL is a fixed voltage VDD, the potential of the second source line SL _ V is zero, and the potential of the first source line SL _ H is a read pulse voltage VREADTo read the resistance value of Rv.
According to an embodiment of the present invention, as shown in fig. 6, when a plurality of resistive random access memory cells shown in fig. 2 are included, bit lines between the plurality of resistive random access memory cells perform AND (AND) AND OR (OR) logic operations. In this way, the logical operation of AND (AND) AND OR (OR) can be performed on two Bit Lines (BL) in the same resistive random access memory unit in coordination with the control of a Source Line (SL).
Therefore, the two resistive memories including the first resistive memory and the second resistive memory are simultaneously controlled by the transistor by utilizing the first source line and the second source line which are perpendicular to each other and an operation bias setting mode, so that the resistive memory unit can be further miniaturized along with the process miniaturization, and the product process is effectively improved.
Similarly, based on the operation circuit of the resistive memory unit as described above, an embodiment of the present invention further provides an integrated circuit, as shown in fig. 7, the integrated circuit 70 at least includes a plurality of operation circuits 701 of the resistive memory unit as shown in fig. 2, and the operation circuits 701 at least include a resistive memory unit composed of a transistor, a first resistive memory, and a second resistive memory; one end of the first resistive random access memory and one end of the second resistive random access memory are connected to a source electrode of the transistor together, the other end of the first resistive random access memory is connected with a first source line, the other end of the second resistive random access memory is connected with a second source line, and the direction of the first source line is perpendicular to the direction of the second source line; the gate of the transistor is connected with a word line, and the word line is parallel to a first source line; the drain of the transistor is wired to be a bit line, which is parallel to the second source line.
Further, based on the operating circuit of the resistive random access memory unit, an embodiment of the present invention further provides an operating method of a resistive random access memory unit, where the resistive random access memory unit is composed of a transistor, a first resistive random access memory, and a second resistive random access memory; as shown in fig. 8, the operation method includes: operation 801, connecting one end of the first resistive random access memory and one end of the second resistive random access memory to a source of the transistor, connecting the other end of the first resistive random access memory to a first source line, connecting the other end of the second resistive random access memory to a second source line, and enabling the direction of the first source line and the direction of the second source line to be perpendicular to each other; an operation 802 of connecting gates of the transistors to word lines, the word lines being parallel to the first source line; operation 803, connecting the drain of the transistor to a bit line, the bit line being parallel to the second source line; and an operation 804 of simultaneously controlling the first resistive random access memory and the second resistive random access memory by the transistor by using the first source line and the second source line which are perpendicular to each other and an operation bias setting mode.
According to an embodiment of the invention, the operating method further comprises: and carrying out AND or logic operation on bit lines of the plurality of resistive random access memory units aiming at an operation circuit comprising the plurality of resistive random access memory units.
Here, it should be noted that: the above description of the embodiment of the operation method of the resistance change memory unit is similar to the description of the circuit embodiment shown in fig. 2 and fig. 6, and has similar beneficial effects to the circuit embodiment shown in fig. 2 and fig. 6, and therefore, the description is omitted. For technical details that are not disclosed in the embodiment of the operation method of the resistance change memory unit of the invention, please refer to the description of the circuit embodiments shown in fig. 2 and fig. 6 of the present invention for understanding, and therefore, for brevity, will not be described again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another device, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: various media that can store program codes, such as a removable Memory device, a Read Only Memory (ROM), a magnetic disk, or an optical disk.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. An operation circuit of a resistance change type memory unit is characterized by at least comprising a resistance change type memory unit which is composed of a transistor, a first resistance change type memory and a second resistance change type memory; wherein the content of the first and second substances,
one end of the first resistive random access memory and one end of the second resistive random access memory are connected to a source electrode of the transistor together, the other end of the first resistive random access memory is connected with a first source line, the other end of the second resistive random access memory is connected with a second source line, and the direction of the first source line is vertical to the direction of the second source line; the gate of the transistor is connected with a word line, and the word line is parallel to a first source line; the drain of the transistor is connected with a bit line, and the bit line is parallel to a second source line;
when the resistance value of the first resistance change type memory is read, the potential of the bit line is a read pulse voltage, the potential of the word line is a fixed voltage, the potential of the first source line is zero, and the potential of the second source line is a read pulse voltage;
when the resistance value of the second resistance change type memory is read, the potential of the bit line is a read pulse voltage, the potential of the word line is a fixed voltage, the potential of the second source line is zero, and the potential of the first source line is a read pulse voltage.
2. The operating circuit of claim 1,
when the first resistive random access memory is formed, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the first source line is a forming pulse voltage, and the second source line is in a floating state;
when the second resistive random access memory is formed, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the second source line is a forming pulse voltage, and the first source line is in a floating state.
3. The operating circuit of claim 1,
when the first resistance random access memory is set, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the first source line is a set pulse voltage, and the second source line is in a floating state;
when the second resistance change type memory is set, the potential of the bit line is zero, the potential of the word line is a word bit pulse voltage, the potential of the second source line is a set pulse voltage, and the first source line is in a floating state.
4. The operating circuit of claim 1,
when the first resistance random access memory is reset, the potential of the bit line is reset pulse voltage, the potential of the word line is word bit pulse voltage, the potential of the first source line is zero, and the second source line is in a floating state;
when the second resistance random access memory is reset, the potential of the bit line is reset pulse voltage, the potential of the word line is word bit pulse voltage, the potential of the second source line is zero, and the first source line is in a floating state.
5. The operating circuit according to any one of claims 1 to 4, wherein the operating circuit comprises a plurality of resistive switching memory cells; and or and logic operation is carried out on bit lines among the plurality of resistance change type memory units.
6. The operation method of the resistive random access memory unit is characterized in that the resistive random access memory unit consists of a transistor, a first resistive random access memory and a second resistive random access memory; the operation method comprises the following steps:
one end of the first resistance change type memory and one end of the second resistance change type memory are connected to a source electrode of the transistor together, the other end of the first resistance change type memory is connected with a first source line, the other end of the second resistance change type memory is connected with a second source line, and the direction of the first source line is vertical to the direction of the second source line; connecting gates of the transistors to word lines, the word lines being parallel to the first source line; connecting the drain electrode of the transistor to a bit line, wherein the bit line is parallel to the second source line, and the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the transistor in a mode of utilizing the first source line and the second source line which are perpendicular to each other and setting an operation bias voltage;
the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the transistor by utilizing the first source line and the second source line which are perpendicular to each other and an operation bias setting mode, and the method comprises the following steps: when reading the resistance value of the first resistance change memory, setting the potential of the bit line as a read pulse voltage, the potential of the word line as a fixed voltage, the potential of the first source line as zero, and the potential of the second source line as a read pulse voltage; when reading the resistance value of the second resistance change memory, the potential of the bit line is set to a read pulse voltage, the potential of the word line is set to a fixed voltage, the potential of the second source line is set to zero, and the potential of the first source line is set to a read pulse voltage.
7. The operating method according to claim 6, wherein the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor by using the first source line and the second source line which are perpendicular to each other and an operating bias setting manner, and the operating method includes:
when the first resistive random access memory is subjected to a forming operation, setting the potential of the bit line to be zero, setting the potential of the word line to be a word bit pulse voltage, setting the potential of the first source line to be a forming pulse voltage, and setting the second source line to be a floating state;
when the second resistance change type memory is subjected to a forming operation, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the second source line is set to a forming pulse voltage, and the first source line is set to a floating state.
8. The operating method according to claim 7, wherein the first resistive random access memory and the second resistive random access memory are simultaneously controlled by the one transistor by using the first source line and the second source line which are perpendicular to each other and an operating bias setting manner, and the operating method includes:
when the first resistance change type memory is set, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the first source line is set to a set pulse voltage, and the second source line is set to a floating state;
when the second resistance change memory is set, the potential of the bit line is set to zero, the potential of the word line is set to a word bit pulse voltage, the potential of the second source line is set to a set pulse voltage, and the first source line is set to a floating state.
9. An integrated circuit, characterized in that the integrated circuit comprises at least a number of operating circuits of the resistive switching memory cell according to any one of claims 1 to 6.
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| WO2009084514A1 (en) * | 2007-12-27 | 2009-07-09 | Nec Corporation | Storage element, semiconductor storage device and information reading method |
| CN102005242A (en) * | 2009-08-28 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Resistance random storage and drive method thereof |
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