CN111723542A - Self-adaptive synchronization method and circuit of four-dimensional balance-point-free hyperchaotic system - Google Patents
Self-adaptive synchronization method and circuit of four-dimensional balance-point-free hyperchaotic system Download PDFInfo
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Abstract
The invention belongs to the technical field of chaotic systems, and discloses a four-dimensional non-balance point hyperchaotic system self-adaptive synchronization method and circuit, which comprise a power supply module for supplying power; the central control module controls each module to work normally through the main control chip; the circuit design module designs a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit; the chaotic sequence generating module generates a chaotic multiphase sequence; the operation module performs operation through an operator; the chaotic system constructing module constructs a four-dimensional equilibrium-point-free hyper-chaotic system; the synchronization module performs signal synchronization on the four-dimensional balance-point-free hyper-chaotic system; the simulation module simulates the chaotic system through a simulation program; and the circuit testing module performs testing. According to the invention, the chaotic sequence generating module can realize that irrelevant chaotic sequences can be generated by randomly changing the initial value, so that an irrelevant sequence with infinite data can be generated; meanwhile, the implementation effect of the four-dimensional balance-point-free hyper-chaotic system is greatly improved through the chaotic system construction module.
Description
Technical Field
The invention belongs to the technical field of chaotic systems, and particularly relates to a four-dimensional balance point-free hyperchaotic system self-adaptive synchronization method and circuit.
Background
The chaotic system refers to a deterministic system in which seemingly random irregular motion exists, and the behavior of the chaotic system is represented by uncertainty, unrepeatability and unpredictability, namely a chaotic phenomenon. The chaos is the inherent characteristic of the nonlinear power system and is a ubiquitous phenomenon of the nonlinear system. Chaos can be divided into four types according to the nature of the dynamical system: temporal chaos, spatial chaos, spatiotemporal chaos, functional chaos. However, the existing four-dimensional non-balance point hyperchaotic system self-adaptive synchronization method and circuit based on the five simplest chaotic systems cannot generate an infinite data non-correlation sequence; meanwhile, the four-dimensional balance point-free hyperchaotic system has poor realization effect.
In summary, the problems of the prior art are as follows: the existing four-dimensional balance point-free hyperchaotic system self-adaptive synchronization method and circuit based on the five simplest chaotic systems cannot generate an infinite data non-correlation sequence; meanwhile, the four-dimensional balance point-free hyperchaotic system has poor realization effect.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a four-dimensional balance-point-free hyperchaotic system self-adaptive synchronization method and circuit.
The invention is realized in such a way, a four-dimensional balance-point-free hyperchaotic system self-adaptive synchronization method and a circuit based on a five-term simplest chaotic system, wherein the four-dimensional balance-point-free hyperchaotic system self-adaptive synchronization method comprises the following steps:
the method comprises the following steps that firstly, a power supply module supplies power to a four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit based on a five-term simplest chaotic system;
and step two, the central control module designs a four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by using a design program through a circuit design module.
Step three, configuring working parameters of a chaotic sequence generator through a chaotic sequence generating module to start the chaotic sequence generator, and performing chaotic iterative operation through a chaotic mapping function to generate a chaotic sequence;
the chaotic iterative operation is carried out through the chaotic mapping function, and the chaotic sequence generation comprises the following steps:
(1.1) the chaotic mapping function f (·) is symmetrical about the medial axis over the predetermined interval I, and the chaotic sequence satisfies: f (c + x) ═ f (c-x);
(1.2) the chaos sequences iteratively generated by the chaos mapping function are symmetrically distributed in a wide area axis in the preset interval I, and the chaos sequences iteratively generated satisfy the following conditions: obtaining a chaotic sequence { xn | N ∈ N }, wherein c is a midpoint of the predetermined interval I, f (x) is the chaotic mapping function, and ρ (x) is a probability distribution function of the chaotic sequence;
step four, obtaining a chaotic multiphase sequence by using a complex quantizer according to a quantization function;
constructing a four-dimensional balance point-free hyper-chaotic system by utilizing an electric device component through a chaotic system constructing module;
the chaotic system construction method comprises the following steps:
(3.1) the Rikitake three-dimensional chaotic system i is as follows:
(3.2) on the basis of the three-dimensional chaotic system i, adding a differential equation dw/dt-ky, and feeding back w to a second equation of the system i to obtain a chaotic system ii;
(3.3) constructing an analog circuit system according to the balance point-free hyper-chaotic system ii;
sixthly, performing signal synchronization on the four-dimensional balance-point-free hyper-chaotic system through a synchronization module; an analog circuit system is constructed according to the chaotic system by an analog module through an analog program, two analog high and low levels are obtained by a voltage comparator, different conditions are used as control inputs of an analog switch, different outputs are realized according to different conditions, and the chaotic system is simulated;
step seven, testing the four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by using the circuit testing module through the testing equipment;
and step eight, displaying the chaotic multiphase sequence, the simulation result and the test result by using a display through a display module.
Further, in step three, the chaotic mapping function takes at least a logical mapping and a tent mapping and is defined over a predetermined interval.
Further, the chaotic mapping function is a logical mapping or a tent mapping,
wherein the logical mapping is: x is the number ofn+1＝rxn(1-xn)，xn∈[0，1]，
The tent map is: x is the number ofn+1＝fT(xn)＝1-|1-bxn|xn∈[0，1]，
3.5699<r≤4，1<b is less than or equal to 2, n is a natural number, xnRepresenting the chaotic sequence.
Further, in the fifth step, the constructing the analog circuit system according to the non-equilibrium point hyper-chaotic system ii includes:
the operational amplifiers U1, U2, resistors and capacitors form an inverting adder and an inverting integrator, multiplication is achieved through multipliers U3, U4 and U5, constant input is achieved through a 1V direct-current power supply, LF347N is adopted for the operational amplifier U1 and the operational amplifier U2, and AD633JN is adopted for the multipliers U3, U4 and U5.
The operational amplifier U1 is connected with an operational amplifier U2, multipliers U3 and U4, the operational amplifier U2 is connected with a multiplier U5, a 1V direct-current power supply and an operational amplifier U1, the multiplier U3 is connected with the operational amplifier U1, the multiplier U4 is connected with the operational amplifier U1, the multiplier U5 is connected with the operational amplifier U2, and the 1V direct-current power supply is connected with the operational amplifier U2;
further, the 1 st pin of the operational amplifier U1 is connected to the 2 nd pin through a resistor R7, the 6 th pin of the U1 is connected through a resistor R8, the 3 rd, 5 th, 10 th and 12 th pins are grounded, the 4 th pin is connected with VCC, the 11 th pin is connected with VEE, the 6 th pin is connected with the 7 th pin of the U1 through a capacitor C2, the 7 th pin is connected with an output y, the No. 6 pin is connected with the No. 6 pin through a resistor R10, the No. 6 pin of the U2 is connected with the resistor R13, the No. 7 pin is connected with the No. 1 pin of the multiplier U3, the No. 7 pin is connected with the No. 3 pin of the multiplier U5, the No. 8 pin outputs x, the 9 th pin is connected with the 8 th pin through a capacitor C1, the 8 th pin is connected with the 1 st pin of the multiplier U4, the 8 th pin is connected with the 1 st pin of the multiplier U5, the first pin is connected with the 6 th pin of the U1 through a resistor R9, the second pin is connected with the 9 th pin of the U1 through a resistor R4, the 13 th pin is connected with the 14 th pin through a resistor R2, and the 14 th pin is connected with the 9 th pin through a resistor R3;
the 1 st, 2 nd, 13 th and 14 th pins of the operational amplifier U2 are suspended, the 3 rd, 5 th, 10 th and 12 th pins are grounded, the 4 th pin is connected with VCC, the 11 th pin is connected with VEE, the 6 th pin is connected with the 7 th pin through a capacitor C4, the 7 th pin outputs w and is connected with the 2 nd pin of U1 through a resistor R5, the 8 th pin is connected with output z, the 3 rd pin of a multiplier U3 is connected with the 3 rd pin of a multiplier U4, the 9 th pin is connected with the 8 th pin of U2 through a capacitor C3 and is grounded after being connected with a 1V power supply through a resistor R12.
Further, the constructing the analog circuit system according to the balance-point-free hyper-chaotic system ii further comprises:
the 1 st pin of the multiplier U3 is connected with the 7 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 13 th pin of U1 through a resistor R1, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U4 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 2 nd pin of U1 through a resistor R6, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U5 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 7 th pin of U1, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 9 th pin of U2 through a resistor R11, and the 8 th pin is connected with VCC.
Another object of the present invention is to provide a four-dimensional unbalanced point-free hyperchaotic system adaptive synchronization circuit for implementing the four-dimensional unbalanced point-free hyperchaotic system adaptive synchronization method, the four-dimensional unbalanced point-free hyperchaotic system adaptive synchronization circuit comprising:
the chaotic system comprises a power supply module, a central control module, a circuit design module, a chaotic sequence generation module, an operation module, a chaotic system construction module, a synchronization module, a simulation module, a circuit test module and a display module;
the power supply module is connected with the central control module and used for supplying power to a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit based on the five simplest chaotic systems;
the central control module is connected with the power supply module, the circuit design module, the chaotic sequence generation module, the operation module, the chaotic system construction module, the synchronization module, the simulation module, the circuit test module and the display module and is used for controlling each module to normally work through the main control chip;
the circuit design module is connected with the central control module and used for designing a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems through a design program;
the chaotic sequence generating module is connected with the central control module and is used for generating a chaotic multiphase sequence through the chaotic sequence generator;
the arithmetic module is connected with the central control module and is used for carrying out arithmetic operation through the arithmetic unit;
the chaotic system constructing module is connected with the central control module and is used for constructing a four-dimensional balance point-free hyperchaotic system through electric appliance parts;
the synchronization module is connected with the central control module and is used for carrying out signal synchronization on the four-dimensional balance-point-free hyperchaotic system;
the simulation module is connected with the central control module and used for simulating the chaotic system through a simulation program;
the circuit testing module is connected with the central control module and used for testing the four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems through testing equipment;
and the display module is connected with the central control module and used for displaying the chaotic multiphase sequence, the simulation result and the test result through the display.
Another object of the present invention is to provide a computer program product stored on a computer readable medium, which includes a computer readable program for providing a user input interface to implement the four-dimensional balance-point-free hyper-chaotic system adaptive synchronization method when the computer program product is executed on an electronic device.
Another object of the present invention is to provide a computer-readable storage medium storing instructions which, when executed on a computer, cause the computer to perform the four-dimensional balance-point-free hyper-chaotic system adaptive synchronization method.
The invention has the advantages and positive effects that: according to the invention, the chaotic sequence generating module can realize that irrelevant chaotic sequences can be generated by randomly changing the initial value, so that an irrelevant sequence with infinite data can be generated; meanwhile, the implementation effect of the four-dimensional balance-point-free hyper-chaotic system is greatly improved through the chaotic system construction module.
Drawings
Fig. 1 is a flow chart of a four-dimensional equilibrium point-free hyper-chaotic system adaptive synchronization method based on a five-term simplest chaotic system according to an embodiment of the present invention.
Fig. 2 is a structural block diagram of a four-dimensional equilibrium-point-free hyper-chaotic system adaptive synchronization circuit based on a five-term simplest chaotic system according to an embodiment of the present invention.
Fig. 3 is a flowchart of a method for generating a chaotic sequence generating module according to an embodiment of the present invention.
Fig. 4 is a flowchart of a method for generating a chaotic sequence by performing chaotic iterative operation through a chaotic mapping function according to an embodiment of the present invention.
Fig. 5 is a circuit connection diagram of a chaotic system constructed by a chaotic system constructing module according to an embodiment of the present invention.
In fig. 2: 1. a power supply module; 2. a central control module; 3. a circuit design module; 4. a chaotic sequence generating module; 5. an operation module; 6. a chaotic system constructing module; 7. a synchronization module; 8. a simulation module; 9. a circuit test module; 10. and a display module.
Detailed Description
In order to further understand the contents, features and effects of the present invention, the following embodiments are illustrated and described in detail with reference to the accompanying drawings.
The structure of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the four-dimensional non-balance-point hyper-chaotic system adaptive synchronization method based on the five simplest chaotic systems provided by the invention comprises the following steps:
s101, supplying power to a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit based on a five-term simplest chaotic system through a power supply module;
s102, designing a four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by a central control module through a circuit design module by utilizing a design program;
s103, generating a chaotic multiphase sequence by using a chaotic sequence generator through a chaotic sequence generating module, and performing operation by using an arithmetic unit through an operation module;
s104, constructing a four-dimensional balance point-free hyper-chaotic system by utilizing an electric device component through a chaotic system constructing module; performing signal synchronization on the four-dimensional balance-point-free hyperchaotic system through a synchronization module; simulating the chaotic system by using a simulation program through a simulation module;
s105, testing the four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by using a circuit testing module through testing equipment;
and S106, displaying the chaotic multiphase sequence, the simulation result and the test result by using a display through a display module.
As shown in fig. 2, the four-dimensional non-equilibrium point hyper-chaotic system adaptive synchronization circuit based on the five simplest chaotic systems provided in the embodiments of the present invention includes: the chaotic circuit comprises a power supply module 1, a central control module 2, a circuit design module 3, a chaotic sequence generation module 4, an operation module 5, a chaotic system construction module 6, a synchronization module 7, an analog module 8, a circuit test module 9 and a display module 10.
The power supply module 1 is connected with the central control module 2 and used for supplying power to a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit based on the five simplest chaotic systems;
the central control module 2 is connected with the power supply module 1, the circuit design module 3, the chaotic sequence generation module 4, the operation module 5, the chaotic system construction module 6, the synchronization module 7, the simulation module 8, the circuit test module 9 and the display module 10 and is used for controlling each module to normally work through a main control chip;
the circuit design module 3 is connected with the central control module 2 and is used for designing a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by a design program;
the chaotic sequence generating module 4 is connected with the central control module 2 and is used for generating a chaotic multiphase sequence through the chaotic sequence generator;
the operation module 5 is connected with the central control module 2 and is used for performing operation through an operator;
the chaotic system constructing module 6 is connected with the central control module 2 and is used for constructing a four-dimensional balance point-free hyperchaotic system through electrical parts;
the synchronization module 7 is connected with the central control module 2 and used for carrying out signal synchronization on the four-dimensional balance-point-free hyper-chaotic system;
the simulation module 8 is connected with the central control module 2 and used for simulating the chaotic system through a simulation program;
the circuit testing module 9 is connected with the central control module 2 and used for testing the four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems through testing equipment;
and the display module 10 is connected with the central control module 2 and is used for displaying the chaotic multiphase sequence, the simulation result and the test result through a display.
The technical solution of the present invention is further illustrated by the following specific examples.
Example 1
The five simplest chaotic systems-based four-dimensional non-balance point hyper-chaotic system adaptive synchronization method provided by the embodiment of the invention is shown in fig. 1, and as a preferred embodiment, as shown in fig. 3, the chaotic sequence generation method provided by the embodiment of the invention is as follows:
s201, configuring working parameters of a chaotic sequence generator to start the chaotic sequence generator, and performing chaotic iterative operation through a chaotic mapping function to generate a chaotic sequence;
s202, obtaining a chaotic multiphase sequence according to a quantization function by using a complex quantizer, wherein the chaotic mapping function at least takes logic mapping and tent mapping and is defined on a preset interval.
As shown in fig. 4, the method for generating a chaotic sequence by performing chaotic iterative operation through a chaotic mapping function according to the present invention is as follows:
s301, the chaotic mapping function f (.) is symmetrical about a central axis in the preset interval I, and the chaotic sequence meets the following conditions: f (c + x) ═ f (c-x);
s302, the chaos sequence generated by the chaos mapping function in an iteration mode is symmetrically distributed in a wide area axis in the preset interval I, and the chaos sequence generated in the iteration mode meets the following requirements: and rho (c + x) ═ rho (c-x), and obtaining a chaotic sequence { xn | N ∈ N }, wherein c is the midpoint of the predetermined interval I, f (x) is the chaotic mapping function, and rho (x) is the probability distribution function of the chaotic sequence.
The chaotic mapping function provided by the invention is a logical mapping or a tent mapping,
wherein the logical mapping is: x is the number ofn+1＝rxn(1-xn)，xn∈[0，1]，
The tent map is: x is the number ofn+1＝fT(xn)＝1-|1-bxn|xn∈[0，1]]，
3.5699<r≤4，1<b is less than or equal to 2, n is a natural number, xnRepresenting the chaotic sequence.
Example 2
The four-dimensional non-balance point hyper-chaotic system adaptive synchronization method based on the five simplest chaotic systems provided by the embodiment of the invention is shown in fig. 1, and as a preferred embodiment, as shown in fig. 5, the chaotic system construction method provided by the invention is as follows:
(1) the Rikitake three-dimensional chaotic system i is as follows:
(2) on the basis of the three-dimensional chaotic system i, adding a differential equation dw/dt which is-ky, and feeding back w to a second equation of the system i to obtain a chaotic system ii;
(3) an analog circuit system is constructed according to a balance-point-free hyper-chaotic system ii, an inverting adder and an inverting integrator are formed by operational amplifiers U1 and U2, resistors and capacitors, multiplication is achieved by multipliers U3, U4 and U5, constant input is achieved by a 1V direct-current power supply, LF347N is adopted by the operational amplifier U1 and the operational amplifier U2, and AD633JN is adopted by the multipliers U3, U4 and U5;
the operational amplifier U1 is connected with an operational amplifier U2, multipliers U3 and U4, the operational amplifier U2 is connected with a multiplier U5, a 1V direct-current power supply and an operational amplifier U1, the multiplier U3 is connected with the operational amplifier U1, the multiplier U4 is connected with the operational amplifier U1, the multiplier U5 is connected with the operational amplifier U2, and the 1V direct-current power supply is connected with the operational amplifier U2;
the 1 st pin of the operational amplifier U1 is connected with the 2 nd pin through a resistor R7, connected with the 6 th pin of the U1 through a resistor R8, the 3 rd, 5 th, 10 th and 12 th pins are grounded, the 4 th pin is connected with VCC, the 11 th pin is connected with VEE, the 6 th pin is connected with the 7 th pin of the U1 through a capacitor C2, the 7 th pin is connected with an output y, the No. 6 pin is connected with the No. 6 pin through a resistor R10, the No. 6 pin of the U2 is connected with the resistor R13, the No. 7 pin is connected with the No. 1 pin of the multiplier U3, the No. 7 pin is connected with the No. 3 pin of the multiplier U5, the No. 8 pin outputs x, the 9 th pin is connected with the 8 th pin through a capacitor C1, the 8 th pin is connected with the 1 st pin of the multiplier U4, the 8 th pin is connected with the 1 st pin of the multiplier U5, the first pin is connected with the 6 th pin of the U1 through a resistor R9, the second pin is connected with the 9 th pin of the U1 through a resistor R4, the 13 th pin is connected with the 14 th pin through a resistor R2, and the 14 th pin is connected with the 9 th pin through a resistor R3;
the 1 st, 2 nd, 13 th and 14 th pins of the operational amplifier U2 are suspended, the 3 rd, 5 th, 10 th and 12 th pins are grounded, the 4 th pin is connected with VCC, the 11 th pin is connected with VEE, the 6 th pin is connected with the 7 th pin through a capacitor C4, the 7 th pin outputs w and is connected with the 2 nd pin of U1 through a resistor R5, the 8 th pin is connected with output z and is connected with the 3 rd pin of a multiplier U3 and the 3 rd pin of a multiplier U4, the 9 th pin is connected with the 8 th pin of U2 through a capacitor C3 and is grounded after being connected with a 1V power supply through a resistor R12;
the 1 st pin of the multiplier U3 is connected with the 7 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 13 th pin of U1 through a resistor R1, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U4 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 2 nd pin of U1 through a resistor R6, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U5 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 7 th pin of U1, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 9 th pin of U2 through a resistor R11, and the 8 th pin is connected with VCC.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When used in whole or in part, can be implemented in a computer program product that includes one or more computer instructions. When loaded or executed on a computer, cause the flow or functions according to embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL), or wireless (e.g., infrared, wireless, microwave, etc.)). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications, equivalent changes and modifications made to the above embodiment according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.
Claims (10)
1. A four-dimensional non-balance point hyperchaotic system self-adaptive synchronization method is characterized by comprising the following steps:
the method comprises the following steps that firstly, a power supply module supplies power to a four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit based on a five-term simplest chaotic system;
and step two, the central control module designs a four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by using a design program through a circuit design module.
Step three, configuring working parameters of a chaotic sequence generator through a chaotic sequence generating module to start the chaotic sequence generator, and performing chaotic iterative operation through a chaotic mapping function to generate a chaotic sequence;
the chaotic iterative operation is carried out through the chaotic mapping function, and the chaotic sequence generation comprises the following steps:
(1.1) the chaotic mapping function f (·) is symmetrical about the medial axis over the predetermined interval I, and the chaotic sequence satisfies: f (c + x) ═ f (c-x);
(1.2) the chaos sequences iteratively generated by the chaos mapping function are symmetrically distributed in a wide area axis in the preset interval I, and the chaos sequences iteratively generated satisfy the following conditions: obtaining a chaotic sequence { xn | N ∈ N }, wherein c is a midpoint of the predetermined interval I, f (x) is the chaotic mapping function, and ρ (x) is a probability distribution function of the chaotic sequence;
step four, obtaining a chaotic multiphase sequence by using a complex quantizer according to a quantization function;
constructing a four-dimensional balance point-free hyper-chaotic system by utilizing an electric device component through a chaotic system constructing module;
the chaotic system construction method comprises the following steps:
(3.1) the Rikitake three-dimensional chaotic system i is as follows:
(3.2) on the basis of the three-dimensional chaotic system i, adding a differential equation dw/dt-ky, and feeding back w to a second equation of the system i to obtain a chaotic system ii;
(3.3) constructing an analog circuit system according to the balance point-free hyper-chaotic system ii;
sixthly, performing signal synchronization on the four-dimensional balance-point-free hyper-chaotic system through a synchronization module; an analog circuit system is constructed according to the chaotic system by an analog module through an analog program, two analog high and low levels are obtained by a voltage comparator, different conditions are used as control inputs of an analog switch, different outputs are realized according to different conditions, and the chaotic system is simulated;
step seven, testing the four-dimensional balance point-free hyper-chaotic system self-adaptive synchronous circuit of the five simplest chaotic systems by using the circuit testing module through the testing equipment;
and step eight, displaying the chaotic multiphase sequence, the simulation result and the test result by using a display through a display module.
2. The adaptive synchronization method for the four-dimensional unbalanced-point hyper-chaotic system in accordance with claim 1, wherein in step three, the chaotic mapping function takes at least a logical mapping and a tent mapping and is defined over a predetermined interval.
3. The four-dimensional non-balance point hyper-chaotic system adaptive synchronization method according to claim 1, wherein the chaotic mapping function is a logical mapping or a tent mapping,
wherein the logical mapping is: x is the number ofn+1＝rxn(1-xn)，xn∈[0，1]，
The tent map is: x is the number ofn+1＝fT(xn)＝1-|1-bxn|xn∈[0，1]，
3.5699<r≤4，1<b is less than or equal to 2, n is a natural number, xnRepresenting the chaotic sequence.
4. The adaptive synchronization method of the four-dimensional unbalanced-point hyperchaotic system as claimed in claim 1, wherein in the fifth step, the constructing the analog circuit system according to the unbalanced-point hyperchaotic system ii comprises:
the operational amplifiers U1, U2, resistors and capacitors form an inverting adder and an inverting integrator, multiplication is achieved through multipliers U3, U4 and U5, constant input is achieved through a 1V direct-current power supply, LF347N is adopted for the operational amplifier U1 and the operational amplifier U2, and AD633JN is adopted for the multipliers U3, U4 and U5.
5. The adaptive synchronization method for the four-dimensional unbalanced-point hyperchaotic system as claimed in claim 4, wherein the operational amplifier U1 is connected with the operational amplifier U2, the multipliers U3 and U4, the operational amplifier U2 is connected with the multipliers U5, the 1V DC power supply and the operational amplifier U1, the multiplier U3 is connected with the operational amplifier U1, the multiplier U4 is connected with the operational amplifier U1, the multiplier U5 is connected with the operational amplifier U2, and the 1V DC power supply is connected with the operational amplifier U2.
6. The adaptive synchronization method of the four-dimensional unbalanced-point-free hyperchaotic system of claim 4, wherein the 1 st pin of the operational amplifier U1 is connected to the 2 nd pin through a resistor R7, connected to the 6 th pin of U1 through a resistor R8, connected to ground through the 3 rd, 5 th, 10 th and 12 th pins, connected to VCC through the 4 th pin, connected to VEE through the 11 th pin, connected to the 7 th pin of U1 through a capacitor C2 through the 6 th pin of the resistor R10, connected to the 6 th pin of U2 through a resistor R13, connected to the 1 st pin of a multiplier U3 through the 7 th pin, connected to the 3 rd pin of a multiplier U5 through a capacitor C1 through the 8 th pin, connected to the 1 st pin of U4 through the 8 th pin, connected to the 1 st pin of a multiplier U5 through the resistor R9, connected to the 6 th pin of U1 through a resistor R1, the 13 th pin is connected with the 14 th pin through a resistor R2, and the 14 th pin is connected with the 9 th pin through a resistor R3;
the 1 st, 2 nd, 13 th and 14 th pins of the operational amplifier U2 are suspended, the 3 rd, 5 th, 10 th and 12 th pins are grounded, the 4 th pin is connected with VCC, the 11 th pin is connected with VEE, the 6 th pin is connected with the 7 th pin through a capacitor C4, the 7 th pin outputs w and is connected with the 2 nd pin of U1 through a resistor R5, the 8 th pin is connected with output z, the 3 rd pin of a multiplier U3 is connected with the 3 rd pin of a multiplier U4, the 9 th pin is connected with the 8 th pin of U2 through a capacitor C3 and is grounded after being connected with a 1V power supply through a resistor R12.
7. The adaptive synchronization method of the four-dimensional unbalanced point-free hyper-chaotic system as claimed in claim 4, wherein the constructing the analog circuit system according to the unbalanced point-free hyper-chaotic system ii further comprises:
the 1 st pin of the multiplier U3 is connected with the 7 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 13 th pin of U1 through a resistor R1, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U4 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 8 th pin of U2, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 2 nd pin of U1 through a resistor R6, and the 8 th pin is connected with VCC;
the 1 st pin of the multiplier U5 is connected with the 8 th pin of U1, the 3 rd pin is connected with the 7 th pin of U1, the 2 nd, the 4 th and the 6 th pins are all grounded, the 5 th pin is connected with VEE, the 7 th pin is connected with the 9 th pin of U2 through a resistor R11, and the 8 th pin is connected with VCC.
8. A four-dimensional non-balance point hyper-chaotic system adaptive synchronization circuit for implementing the four-dimensional non-balance point hyper-chaotic system adaptive synchronization method according to claims 1 to 7, wherein the four-dimensional non-balance point hyper-chaotic system adaptive synchronization circuit comprises:
the chaotic system comprises a power supply module, a central control module, a circuit design module, a chaotic sequence generation module, an operation module, a chaotic system construction module, a synchronization module, a simulation module, a circuit test module and a display module;
the power supply module is connected with the central control module and used for supplying power to a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit based on the five simplest chaotic systems;
the central control module is connected with the power supply module, the circuit design module, the chaotic sequence generation module, the operation module, the chaotic system construction module, the synchronization module, the simulation module, the circuit test module and the display module and is used for controlling each module to normally work through the main control chip;
the circuit design module is connected with the central control module and used for designing a four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems through a design program;
the chaotic sequence generating module is connected with the central control module and is used for generating a chaotic multiphase sequence through the chaotic sequence generator;
the arithmetic module is connected with the central control module and is used for carrying out arithmetic operation through the arithmetic unit;
the chaotic system constructing module is connected with the central control module and is used for constructing a four-dimensional balance point-free hyperchaotic system through electric appliance parts;
the synchronization module is connected with the central control module and is used for carrying out signal synchronization on the four-dimensional balance-point-free hyperchaotic system;
the simulation module is connected with the central control module and used for simulating the chaotic system through a simulation program;
the circuit testing module is connected with the central control module and used for testing the four-dimensional balance point-free hyperchaotic system self-adaptive synchronous circuit of the five simplest chaotic systems through testing equipment;
and the display module is connected with the central control module and used for displaying the chaotic multiphase sequence, the simulation result and the test result through the display.
9. A computer program product stored on a computer readable medium, comprising a computer readable program for providing a user input interface to implement the four-dimensional non-equilibrium point hyper-chaotic system adaptive synchronization method according to any one of claims 1-7 when executed on an electronic device.
10. A computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the four-dimensional non-equilibrium point hyper-chaotic system adaptive synchronization method according to any one of claims 1 to 7.
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