CN111722834B - Robot-oriented EKF-SLAM algorithm acceleration method - Google Patents
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Abstract
An acceleration method for an EKF-SLAM algorithm of a robot belongs to the field of EKF-SLAM algorithm acceleration for building and positioning foundation of an environment map of the robot. The problem that the operation speed of the conventional EKF-SLAM algorithm is low is solved. The acceleration method is realized based on FPGA, and the matrix (Z.K) in the EKF-SLAM algorithm is subjected to FPGAT)T·KTAnd performing parallel operation, thereby realizing acceleration of the EKF-SLAM algorithm. The method is mainly used for accelerating the EKF-SLAM algorithm.
Description
Technical Field
The invention belongs to the Field of EKF-SLAM algorithm acceleration based on robot environment map construction and positioning, and particularly relates to a method for realizing EKF-SLAM algorithm hardware acceleration by means of a Field Programmable Gate Array (FPGA).
Background
The basis of the robot-oriented environment map construction and positioning is realized by adopting an EKF-SLAM algorithm, and the EKF-SLAM algorithm can be divided into two parts:
and (3) prediction circulation:
and (3) updating circulation:
in the formula (I), the compound is shown in the specification,
a prior representing a state vector; f represents a state equation;
a posteriori representing the state vector; u. ofkA control vector representing an input;
a prior representing a covariance matrix; f represents the partial derivative of the state equation to the state vector;
a posteriori representing a covariance matrix; rkA covariance matrix representing state vector noise; z represents an innovation covariance matrix; h represents the partial derivative of the observation equation to the state vector; qkA covariance matrix representing observation vector noise; k represents a Kalman gain matrix; z is a radical ofkRepresenting an observation vector; h represents an observation equation;
the research shows that: in the last formula of the update cycle (Z.K)T)T·KTAccounting for 64% of the time used by all the equations in the EKF-SLAM algorithm, the entire calculation process of the EKF-SLAM algorithm is performed in the CPU, the dimension of the matrix Z is 2 x 2, the dimension of the matrix K is 2 x n, and the calculation (Z.K.T)T·KTIn the process of (2), a serial calculation mode is adopted, one element in a result matrix can be obtained in each calculation, the calculation speed is low, and the (Z.K) is also causedT)T·KTThe calculation process of (2) is slow, which results in the slow calculation speed of the EKF-SLAM algorithm, so how to accelerate the EKF-SLAM algorithm, the above problems need to be solved urgently.
Disclosure of Invention
The invention aims to solve the problem that the conventional EKF-SLAM algorithm is low in operation speed, and provides an acceleration method for a robot EKF-SLAM algorithm.
An acceleration method for robot EKF-SLAM algorithm is realized based on FPGA, and matrix (Z.K) in EKF-SLAM algorithm is subjected to FPGAT)T·KTPerforming parallel operation so as to realize acceleration of the EKF-SLAM algorithm;
the dimension of matrix Z is 2 × 2, the dimension of matrix K is nx2, and n is an integer.
Preferably, the acceleration method comprises the following specific processes:
step one, transposing K of matrix K in DDR memory of robotTDividing the DDR memory into M2 multiplied by 2 block matrixes No. 1, and respectively defining the DDR memory as a first block matrix No. 1 to an Mth block matrix No. 1 according to the dividing sequence, wherein the DDR memory further stores a matrix Z, M is an integer, and n is 2M;
step two, the FPGA sequentially calls the first to Mth No. 1 block matrixes and the matrix Z from the DDR memory and stores the matrixes; according to the calling sequence of M No. 1 block matrixes, enabling the matrix Z to be respectively equal to KTMultiplying M number 1 blocks in matrix to obtain matrix Z.KT；
The matrix Z and any one No. 1 block matrix are multiplied by each other in the following implementation mode: 4 elements in the matrix Z are multiplied with 4 elements in any No. 1 block matrix in a parallel operation mode;
step three, the matrix Z.K is alignedTTransposing to obtain a matrix (Z.K)T)TAnd the matrix (Z.K)T)TDividing the matrix into M2 × 2 block matrixes, and respectively defining the matrix as a first block matrix to an Mth block matrix No. 2 according to the dividing sequence;
step four, making the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe first to mth block number 1 matrices in (b) are multiplied, thereby obtaining a matrix (Z · K)T)T·KTCompleting the acceleration of the EKF-SLAM algorithm;
the realization mode of multiplying any one No. 2 block matrix in the M No. 2 block matrices by the corresponding No. 1 block matrix is as follows: any 4 elements in the block matrix No. 2 are multiplied with 4 elements in the corresponding block matrix No. 1 in a parallel operation mode.
Preferably, the FPGA and the DDR memory of the robot communicate with each other through an interface module of an AXI protocol.
Preferably, the FPGA comprises 8 dual-port RAM modules, 4 registers and two processing modules;
wherein, the 4 registers are respectively used for storing 4 elements in the matrix Z;
4 double-port RAM modules are used as a group and are respectively defined as a first double-port RAM module, a second double-port RAM module and a third double-port RAM module; the first double-port RAM module is used for storing elements of a first row and a first column in M No. 1 block matrixes; the second double-port RAM module is used for storing elements of a first row and a second column in M No. 1 block matrixes; the third double-port RAM module is used for storing elements of a second row and a first column in M No. 1 block matrixes; the fourth double-port RAM module is used for storing elements of a second row and a second column in M No. 1 block matrixes;
the rest 4 dual-port RAM modules are used as another group and are respectively defined as a fifth dual-port RAM module to an eighth dual-port RAM module; the fifth double-port RAM module is used for storing elements of a first row and a first column in M No. 2 block matrixes; the sixth double-port RAM module is used for storing elements of a first row and a second column in M No. 2 block matrixes; the seventh double-port RAM module is used for storing elements of a second row and a first column in M No. 2 block matrixes; the eighth double-port RAM module is used for storing elements of a second row and a second column in the M No. 2 block matrixes;
the first of the two processing modules is used for realizing that the matrix Z is respectively equal to the matrix KTMultiplying M block matrixes No. 1;
a second processing module for implementing the Z.K matrixTTransposing to obtain a matrix (Z.K)T)TAnd will be a momentArray (Z.K)T)TDividing the matrix into M2 multiplied by 2 block matrixes; and also for implementing the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe multiplication operation of the first to mth block matrices No. 1.
Preferably, the address lines of the first to fourth dual-port RAM modules are changed, so that the first to fourth dual-port RAM modules can sequentially output corresponding elements in the first to M block matrixes No. 1.
Preferably, the address lines of the fifth to eighth dual-port RAM modules are changed, so that the fifth to eighth dual-port RAM modules can sequentially output corresponding elements in the first to M number 2 block matrixes.
Preferably, the matrix (Z.K)T)T·KTIs composed of an M × M block matrix having dimensions of 2 × 2.
The invention has the following beneficial effects: by means of FPGA, the matrix (Z.K) in EKF-SLAM algorithmT)T·KTThe calculation process of the method is realized in the FPGA, and the calculation is carried out in a parallel calculation mode, so that the calculation speed is improved, the requirement of the EKF-SLAM algorithm on the real-time performance is met, the method breaks away from the mode that the EKF-SLAM algorithm in the prior art is completely dependent on the realization of a CPU, and the defects of occupying hardware storage resources of the robot and increasing the calculation amount of the CPU are avoided.
The process of accelerating the EKF-SLAM algorithm comprises two rounds of acceleration calculation: the first round of acceleration is for the matrix Z.KTIn other words, the acceleration is realized by using KTDividing into M2 × 2 block matrixes No. 1, and making matrix Z and K respectively according to the calling sequence of M block matrixes No. 1TThe M number 1 block matrixes are multiplied, parallel operation can be performed in each multiplication operation, in the first round of acceleration process, the matrix with larger dimension is divided into the block matrixes with smaller dimension, and the smaller block matrixes are used for performing parallel operation, so that the first round of operation speed is increased.
The second round of acceleration is for (Z.K)T)T·KTIn other words, the acceleration is realized by a matrix (Z.cndot.) after the first round of accelerationKT)TThe number 2 block matrixes with smaller dimensions are divided into M number 2 block matrixes, the M number 2 block matrixes are respectively multiplied with the number 1 block matrix in parallel, and each multiplication operation can be carried out in parallel, so that the second round of acceleration is realized.
Drawings
FIG. 1 is a schematic diagram of the FPGA of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, the embodiment is described, and the acceleration method for the robot EKF-SLAM algorithm is realized based on the FPGA, and the matrix (Z · K) in the EKF-SLAM algorithm is applied to the FPGAT)T·KTPerforming parallel operation so as to realize acceleration of the EKF-SLAM algorithm;
the dimension of matrix Z is 2 × 2, the dimension of matrix K is nx2, and n is an integer.
In the present embodiment, the matrix (Z.K) in the EKF-SLAM algorithm is implemented by means of FPGAT)T·KTThe calculation process of the method is realized in the FPGA, and the calculation is carried out in a parallel calculation mode, so that the calculation speed is improved, the requirement of the EKF-SLAM algorithm on the real-time performance is met, the method breaks away from the mode that the EKF-SLAM algorithm in the prior art is completely dependent on the realization of a CPU, and the defects of occupying hardware storage resources of the robot and increasing the calculation amount of the CPU are avoided.
Further, the acceleration method comprises the following specific processes:
step one, transferring a matrix K in a DDR memory of a robotPut KTDividing the DDR memory into M2 multiplied by 2 block matrixes No. 1, and respectively defining the DDR memory as a first block matrix No. 1 to an Mth block matrix No. 1 according to the dividing sequence, wherein the DDR memory further stores a matrix Z, M is an integer, and n is 2M;
step two, the FPGA sequentially calls the first to Mth No. 1 block matrixes and the matrix Z from the DDR memory and stores the matrixes; according to the calling sequence of M No. 1 block matrixes, enabling the matrix Z to be respectively equal to KTMultiplying M number 1 blocks in matrix to obtain matrix Z.KT；
The matrix Z and any one No. 1 block matrix are multiplied by each other in the following implementation mode: 4 elements in the matrix Z are multiplied with 4 elements in any No. 1 block matrix in a parallel operation mode;
step three, the matrix Z.K is alignedTTransposing to obtain a matrix (Z.K)T)TAnd the matrix (Z.K)T)TDividing the matrix into M2 × 2 block matrixes, and respectively defining the matrix as a first block matrix to an Mth block matrix No. 2 according to the dividing sequence;
step four, making the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe first to mth block number 1 matrices in (b) are multiplied, thereby obtaining a matrix (Z · K)T)T·KTCompleting the acceleration of the EKF-SLAM algorithm;
the realization mode of multiplying any one No. 2 block matrix in the M No. 2 block matrices by the corresponding No. 1 block matrix is as follows: any 4 elements in the block matrix No. 2 are multiplied with 4 elements in the corresponding block matrix No. 1 in a parallel operation mode.
In the preferred embodiment, the robot EKF-SLAM algorithm-oriented acceleration method mainly performs two-round acceleration, wherein the first round of acceleration is relative to the matrix Z.KTIn other words, the acceleration is realized by using KTDividing into M2 × 2 block matrixes No. 1, and making matrix Z and K respectively according to the calling sequence of M block matrixes No. 1TMultiplying M number 1 block matrixes, performing parallel operation in each multiplication operation, and dividing the matrix with larger dimension into the matrix with smaller dimension in the first round of acceleration processThe block matrix of (2) performs parallel operation by using a smaller block matrix, thereby improving the operation speed of the first round.
The second round of acceleration is for (Z.K)T)T·KTThe acceleration is realized by the matrix (Z.K) after the first round of accelerationT)TThe number 2 block matrixes with smaller dimensions are divided into M number 2 block matrixes, the M number 2 block matrixes are respectively multiplied with the number 1 block matrix in parallel, and each multiplication operation can be carried out in parallel, so that the second round of acceleration is realized.
Furthermore, the FPGA and the DDR memory of the robot are communicated through an interface module of an AXI protocol.
Further, referring specifically to fig. 1, the FPGA includes 8 dual-port RAM modules, 4 registers, and two processing modules;
wherein, the 4 registers are respectively used for storing 4 elements in the matrix Z;
4 double-port RAM modules are used as a group and are respectively defined as a first double-port RAM module, a second double-port RAM module and a third double-port RAM module; the first double-port RAM module is used for storing elements of a first row and a first column in M No. 1 block matrixes; the second double-port RAM module is used for storing elements of a first row and a second column in M No. 1 block matrixes; the third double-port RAM module is used for storing elements of a second row and a first column in M No. 1 block matrixes; the fourth double-port RAM module is used for storing elements of a second row and a second column in M No. 1 block matrixes;
the rest 4 dual-port RAM modules are used as another group and are respectively defined as a fifth dual-port RAM module to an eighth dual-port RAM module; the fifth double-port RAM module is used for storing elements of a first row and a first column in M No. 2 block matrixes; the sixth double-port RAM module is used for storing elements of a first row and a second column in M No. 2 block matrixes; the seventh double-port RAM module is used for storing elements of a second row and a first column in M No. 2 block matrixes; the eighth double-port RAM module is used for storing elements of a second row and a second column in the M No. 2 block matrixes;
the first of the two processing modules is used for realizing that the matrix Z is respectively equal to the matrix KTMultiplying M block matrixes No. 1;
a second processing module for implementingMatrix Z.KTTransposing to obtain a matrix (Z.K)T)TAnd the matrix (Z.K)T)TDividing the matrix into M2 multiplied by 2 block matrixes; and also for implementing the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe multiplication operation of the first to mth block matrices No. 1.
Furthermore, the operation result of the second processing module can be sent to the DDR memory through the interface module.
Furthermore, by changing the address lines of the first to fourth dual-port RAM modules, the first to fourth dual-port RAM modules can sequentially output corresponding elements in the first to M block matrixes No. 1.
In the preferred embodiment, the direction of outputting data to the first to fourth dual-port RAM modules can be realized by controlling the address lines of the first to fourth dual-port RAM modules.
Furthermore, by changing the address lines of the fifth to eighth dual-port RAM modules, the fifth to eighth dual-port RAM modules can sequentially output corresponding elements in the first to M number 2 block matrixes.
In the preferred embodiment, the direction of outputting data to the fifth to eighth dual-port RAM modules can be realized by controlling the address lines of the fifth to eighth dual-port RAM modules.
Further, the matrix (Z.K)T)T·KTIs composed of an M × M block matrix having dimensions of 2 × 2.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (6)
1. The robot-oriented EKF-SLAM algorithm acceleration method is realized based on FPGA, and is characterized in that the matrix (Z.K) in the EKF-SLAM algorithm is subjected to FPGAT)T·KTPerforming parallel operation so as to realize acceleration of the EKF-SLAM algorithm;
wherein, the dimension of the matrix Z is 2 multiplied by 2, the dimension of the matrix K is nx2, and n is an integer;
the acceleration method comprises the following specific processes:
step one, transposing K of matrix K in DDR memory of robotTDividing the DDR memory into M2 multiplied by 2 block matrixes No. 1, and respectively defining the DDR memory as a first block matrix No. 1 to an Mth block matrix No. 1 according to the dividing sequence, wherein the DDR memory further stores a matrix Z, M is an integer, and n is 2M;
step two, the FPGA sequentially calls the first to Mth No. 1 block matrixes and the matrix Z from the DDR memory and stores the matrixes; according to the calling sequence of M No. 1 block matrixes, enabling the matrix Z to be respectively equal to KTMultiplying M number 1 blocks in matrix to obtain matrix Z.KT；
The matrix Z and any one No. 1 block matrix are multiplied by each other in the following implementation mode: 4 elements in the matrix Z are multiplied with 4 elements in any No. 1 block matrix in a parallel operation mode;
step three, the matrix Z.K is alignedTTransposing to obtain a matrix (Z.K)T)TAnd the matrix (Z.K)T)TDividing the matrix into M2 × 2 block matrixes, and respectively defining the matrix as a first block matrix to an Mth block matrix No. 2 according to the dividing sequence;
step four, making the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe first to mth block number 1 matrices in (b) are multiplied, thereby obtaining a matrix (Z · K)T)T·KTCompleting the acceleration of the EKF-SLAM algorithm;
the realization mode of multiplying any one No. 2 block matrix in the M No. 2 block matrices by the corresponding No. 1 block matrix is as follows: any 4 elements in the block matrix No. 2 are multiplied with 4 elements in the corresponding block matrix No. 1 in a parallel operation mode.
2. The acceleration method for the robot EKF-SLAM algorithm as claimed in claim 1, wherein the FPGA communicates with the robot DDR memory through an AXI protocol interface module.
3. The robot-oriented EKF-SLAM algorithm acceleration method of claim 1, wherein FPGA comprises 8 dual-port RAM modules, 4 registers and two processing modules;
wherein, the 4 registers are respectively used for storing 4 elements in the matrix Z;
4 double-port RAM modules are used as a group and are respectively defined as a first double-port RAM module, a second double-port RAM module and a third double-port RAM module; the first double-port RAM module is used for storing elements of a first row and a first column in M No. 1 block matrixes; the second double-port RAM module is used for storing elements of a first row and a second column in M No. 1 block matrixes; the third double-port RAM module is used for storing elements of a second row and a first column in M No. 1 block matrixes; the fourth double-port RAM module is used for storing elements of a second row and a second column in M No. 1 block matrixes;
the rest 4 dual-port RAM modules are used as another group and are respectively defined as a fifth dual-port RAM module to an eighth dual-port RAM module; the fifth double-port RAM module is used for storing elements of a first row and a first column in M No. 2 block matrixes; the sixth double-port RAM module is used for storing elements of a first row and a second column in M No. 2 block matrixes; the seventh double-port RAM module is used for storing elements of a second row and a first column in M No. 2 block matrixes; the eighth double-port RAM module is used for storing elements of a second row and a second column in the M No. 2 block matrixes;
the first of the two processing modules is used for realizing that the matrix Z is respectively equal to the matrix KTMultiplying M block matrixes No. 1;
a second processing module for implementing the Z.K matrixTTransposing to obtain a matrix (Z.K)T)TAnd the matrix (Z.K)T)TDivided into M2 x 2Block matrix number 2; and also for implementing the matrix (Z.K)T)TThe first to Mth No. 2 block matrixes are respectively connected with KTThe multiplication operation of the first to mth block matrices No. 1.
4. The acceleration method for EKF-SLAM algorithm of robot as claimed in claim 3, wherein the address lines of the first to the fourth dual-port RAM modules are changed, so that the first to the fourth dual-port RAM modules can output the corresponding elements of the first to M number 1 block matrixes in sequence.
5. The acceleration method for EKF-SLAM algorithm of robot as claimed in claim 3, wherein the address lines of the fifth to eighth dual-port RAM modules are changed to make the fifth to eighth dual-port RAM modules output the corresponding elements of the first to M number 2 block matrixes in turn.
6. The acceleration method for robot EKF-SLAM algorithm as in claim 3, wherein the matrix (Z.K)T)T·KTIs composed of an M × M block matrix having dimensions of 2 × 2.
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