CN111710676B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN111710676B CN111710676B CN202010773347.5A CN202010773347A CN111710676B CN 111710676 B CN111710676 B CN 111710676B CN 202010773347 A CN202010773347 A CN 202010773347A CN 111710676 B CN111710676 B CN 111710676B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 244
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims description 22
- 238000010438 heat treatment Methods 0.000 abstract description 24
- 230000000694 effects Effects 0.000 abstract description 12
- 238000002955 isolation Methods 0.000 description 19
- 239000000463 material Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000007769 metal material Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application provides a semiconductor device and a manufacturing method thereof.A substrate is provided with at least one fin structure, and the fin structures are arranged along a first direction; at least two metal gates crossing the fin structure, wherein each metal gate covers part of the top surface and part of the side wall surface of the fin structure, the metal gates are arranged along a second direction, and the second direction and the first direction are vertically crossed; at least one virtual grid is arranged between at least two adjacent metal grids, and the potentials at two sides of each virtual grid are equal. Thus, the potentials at the two sides of each virtual gate electrode are equal, so that the potentials at the source region and the drain region at the two sides of the virtual gate electrode are equal, the source region and the drain region at the two sides of the virtual gate electrode have no voltage crossing, the influence of short channel effect is reduced, the generation of extra current and self-heating are reduced, and the self-heating of the transistor is reduced.
Description
Technical Field
The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
The Fin-shaped structure of the Fin Field-Effect Transistor (FinFET) increases the area of the metal gate around the channel, and enhances the control of the metal gate on the channel, so that the short channel effect in the planar device can be effectively relieved, and the gate length of the transistor is greatly shortened.
As process nodes advance, the increasing metal gate density may cause the FinFET to generate more localized hot spots that cannot dissipate heat completely through the substrate, and localized power consumption hot spots may also translate into higher localized self-heating. The self-heating effect of the transistor becomes more pronounced as the process node advances during normal operation of the circuit, resulting in reduced reliability of the subsequent process (BEOL).
The existing method for reducing self-heating of FinFETs can reduce the density of transistors by increasing the virtual grid, but when the virtual grid is floating, the two ends of the source and the drain still have cross voltage, and when the length of the metal grid is shorter, extra electric leakage is easy to generate due to the short channel effect, and a heat source is generated to heat the transistors, so that the self-heating of the transistors is increased.
Disclosure of Invention
In view of the above, an object of the present application is to provide a semiconductor device and a method for manufacturing the same, which can reduce self-heating of a transistor.
In order to achieve the above purpose, the application has the following technical scheme:
a semiconductor device, comprising:
a substrate, wherein at least one fin structure is formed on the substrate, and the fin structures are arranged along a first direction;
at least two metal gates spanning the fin structure, each metal gate covering a portion of a top surface and a portion of a sidewall surface of the fin structure, the metal gates being arranged along a second direction, the second direction perpendicularly intersecting the first direction;
at least one virtual grid is arranged between at least two adjacent metal grids, and the electric potential at two sides of each virtual grid is equal.
Optionally, the method further comprises equalizing the potential on both sides of each of the virtual gates by:
and the two sides of each virtual grid electrode are connected with the same bias voltage.
Optionally, the method further comprises:
a first metal wire, a second metal wire, a third metal wire and a fourth metal wire are sequentially connected to at least one metal gate;
and obtaining the resistance of the at least one metal gate by using the voltage between the first metal line and the fourth metal line and the current between the second metal line and the third metal line, wherein the resistance is used for obtaining the temperature of the at least one metal gate.
Optionally, the method further comprises:
the first metal wire and the second metal wire are connected to the first position of at least one metal gate;
the third metal line and the fourth metal line are connected to the second position of the at least one metal gate.
Optionally, at least one virtual gate is included between the at least two adjacent metal gates, and the electric potential at two sides of each virtual gate is equal, which specifically includes:
and a plurality of virtual gates are arranged between at least two adjacent metal gates, and the potentials of a source region and a drain region in the plurality of virtual gates are equal to each other and equal to the potential between each virtual gate in the plurality of virtual gates.
A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein at least one fin structure is formed on the substrate, and the fin structures are arranged along a first direction;
forming at least two metal gates across the fin structure, each metal gate covering a portion of a top surface and a portion of a sidewall surface of the fin structure, the metal gates being arranged along a second direction, the second direction perpendicularly intersecting the first direction;
at least one virtual grid electrode is arranged between at least two adjacent metal grid electrodes, and the electric potential at two sides of each virtual grid electrode is equal.
Optionally, at least one virtual gate is disposed between at least two adjacent metal gates, and the electric potential at two sides of each virtual gate is equal, which specifically includes:
at least one virtual grid electrode is arranged between at least two adjacent metal grid electrodes, and the two sides of each virtual grid electrode are connected with the same bias voltage so as to make the electric potential at the two sides of each virtual grid electrode equal.
Optionally, the method further comprises:
sequentially connecting a first metal wire, a second metal wire, a third metal wire and a fourth metal wire on at least one metal gate;
and obtaining the resistance of the at least one metal gate by using the voltage between the first metal line and the fourth metal line and the current between the second metal line and the third metal line, wherein the resistance is used for obtaining the temperature of the at least one metal gate.
Optionally, the method further comprises:
connecting a first metal wire and a second metal wire at a first position of at least one metal gate;
and connecting a third metal wire and a fourth metal wire at a second position of the at least one metal gate.
Optionally, at least one virtual gate is disposed between at least two adjacent metal gates, and the electric potential at two sides of each virtual gate is equal, which specifically includes:
a plurality of virtual gates are arranged between at least two adjacent metal gates, and the potentials of a source region and a drain region in the plurality of virtual gates are equal to each other and equal to the potential between each of the plurality of virtual gates.
In the semiconductor device provided by the embodiment of the application, at least one fin structure is formed on a substrate, and the fin structures are arranged along a first direction; at least two metal gates crossing the fin structure, wherein each metal gate covers part of the top surface and part of the side wall surface of the fin structure, the metal gates are arranged along a second direction, and the second direction and the first direction are vertically crossed; at least one virtual grid is arranged between at least two adjacent metal grids, and the potentials at two sides of each virtual grid are equal. Thus, the potentials at the two sides of each virtual gate electrode are equal, so that the potentials at the source region and the drain region at the two sides of the virtual gate electrode are equal, the source region and the drain region at the two sides of the virtual gate electrode have no voltage crossing, the influence of short channel effect is reduced, the generation of extra current and self-heating are reduced, and the self-heating of the transistor is reduced.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are some embodiments of the application and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2 to 6 show schematic structural views of a semiconductor device according to an embodiment of the present application.
Detailed Description
In order that the above objects, features and advantages of the application will be readily understood, a more particular description of the application will be rendered by reference to the appended drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present application is not limited to the specific embodiments disclosed below.
As described in the background art, the current method for reducing FinFET self-heating can reduce the density of the transistor by increasing the dummy gate, but when the dummy gate is floating (floating), the voltage across the source and drain is still high, and when the metal gate is short, additional leakage is easily generated due to the short channel effect, and a heat source is generated to heat the transistor, so as to increase the self-heating of the transistor.
To this end, the present application provides a semiconductor device having at least one fin structure formed on a substrate, the fin structures being arranged along a first direction; at least two metal gates crossing the fin structure, wherein each metal gate covers part of the top surface and part of the side wall surface of the fin structure, the metal gates are arranged along a second direction, and the second direction and the first direction are vertically crossed; at least one virtual grid is arranged between at least two adjacent metal grids, and the potentials at two sides of each virtual grid are equal. Like this, the electric potential of every virtual grid both sides that sets up between the metal grid is equal for the electric potential of the source region and the drain region of virtual grid both sides is equal, makes source region and the drain region of virtual grid both sides not have the cross voltage, can not receive short channel effect's influence simultaneously, and then can not produce extra electric current and self-heating, reduces the self-heating of transistor.
In order to facilitate understanding of the technical scheme and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
An embodiment of the present application provides a semiconductor device, as shown with reference to fig. 2 to 4, including:
a substrate 100, at least one fin structure 110 is formed on the substrate 100, the fin structures 110 being arranged along a first direction;
at least two metal gates 130 crossing the fin structure 110, each metal gate 130 covering a portion of the top surface and a portion of the sidewall surface of the fin structure 110, the metal gates 130 being arranged along a second direction, the second direction perpendicularly intersecting the first direction;
at least one dummy gate 140 is included between at least two adjacent metal gates 130, and the potential at both sides of each dummy gate 140 is equal.
In an embodiment of the present application, the substrate 100 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon on insulator ), a GOI (germanium on insulator, germaniun On Insulator), or the like. In other embodiments, the substrate 100 may further comprise other elemental or compound semiconductor substrates, such as GaAs, inP, siC, etc., stacked structures, such as Si/SiGe, etc., and other epitaxial structures, such as SGOI (silicon germanium on insulator ), etc.
At least one fin structure 110 is formed on the substrate 100, the fin structures 110 being arranged along a first direction. The fin structures 110 are protruding from the substrate 100, and a plurality of fin structures 110 are formed in a first direction, where each fin structure 110 is arranged along the first direction, and the first direction may be a direction parallel to the substrate 100, and the material of the fin structures 110 may be a semiconductor material, for example, may be the same as or different from the material of the substrate 100. An isolation layer 120 may be further formed between the fin structures 110, and referring to fig. 2, the isolation layer 120 is used to isolate each fin structure 110, and the isolation layer 120 may be, for example, a silicon oxide layer.
In an embodiment of the present application, at least two metal gates 130 span the fin structure 110, and each metal gate 130 covers a portion of the top surface and a portion of the sidewall surface of the fin structure 110, and the metal gates 130 are arranged along a second direction, and the second direction and the first direction vertically intersect, as shown in fig. 3 and 4.
A plurality of metal gates 130 are formed over the fin structure 110, the plurality of metal gates 130 being sequentially arranged along a second direction parallel to the substrate 100 and perpendicularly intersecting the first direction, each metal gate 130 being formed on the substrate 100 and covering a portion of the sidewalls and top surface of the fin structure 110, in particular, each metal gate 130 covering the isolation layer 120 and covering sidewalls and top surfaces of the fin structure 110 higher than the isolation layer 120. The lower portion of the fin structure 110 under the metal gate 130 is a well region, such as the fin structure 110 covered by the isolation layer 120, and the upper portion of the fin structure 110 under the metal gate 130 is a channel region, such as the fin structure 110 protruding from the top of the isolation layer 120. Each metal gate 130 has a certain interval therebetween, and the smaller the interval between each metal gate 130, the greater the number of metal gates 130, and the higher the integration of the device. In a specific embodiment, the metal gate 130 may be polysilicon. In a specific embodiment, a gate dielectric layer 125 is formed between the fin structure 110 and the metal gate 130, where the gate dielectric layer 125 separates the fin structure 110 and the metal gate 130, and the gate dielectric layer 125 may be, for example, a high-k dielectric material.
However, when the number of the metal gates 130 is large, that is, when the number of the transistors formed is large, the self-heating effect of the transistors is remarkable, and thus the performance of the device is affected, a dummy gate may be provided between the metal gates 130. In the embodiment of the present application, at least one dummy gate 140 is included between at least two adjacent metal gates 130, and the electric potentials at two sides of each dummy gate 140 are equal. The regions on both sides of the dummy gate 140 may be regions between each of the dummy gates 140 or regions between the dummy gate 140 and the metal gate 130.
In this embodiment, a dummy gate 140 may be disposed between the metal gates 130, and as shown in fig. 3, the source and drain regions between the dummy gate 140 and the metal gate 130 may be made equal in potential by connecting the same bias voltages to both sides of the dummy gate 140. A plurality of dummy gates 140 may be disposed between the metal gates 130, and as shown in fig. 4, the same bias voltage may be connected to both sides of each dummy gate 140 among the plurality of dummy gates 140 such that the potential of the source and drain regions between the dummy gate 140 and the metal gate 130 is equal to the potential of the region between each two dummy gates 140. For example, the same high bias voltage may be connected to both sides of each of the plurality of dummy gates 140, and the source and drain regions between the dummy gates 140 and the metal gate 130 may be high bias voltages, and the high bias voltages may be connected between the dummy gates 140. The same low bias voltage may be connected to both sides of each dummy gate 140 among the plurality of dummy gates 140, and thus the source and drain regions between the dummy gates 140 and the metal gate 130 may be low bias voltages, and the low bias voltages may be connected between the dummy gates 140. In a particular application, dummy gates 145 may be formed at both end edges of fin structure 110, the dummy gates 145 facilitating epitaxial growth of the source and drain regions.
In this embodiment, a first metal line 211, a second metal line 212, a third metal line 213, and a fourth metal line 214 may be sequentially connected to at least one metal gate 130, the first metal line 211 and the fourth metal line 214 may be connected to two ends of the metal gate 130, and referring to fig. 5, two ends refer to two ends of the metal gate 130, the second metal line 212 and the third metal line 213 are connected to the metal gate 130 between the first metal line 211 and the fourth metal line 214, the second metal line 212 is close to the first metal line 211, and the third metal line 213 is close to the fourth metal line 214. Then, the resistance of the metal gate 130 is obtained by using the voltage between the first metal line 211 and the fourth metal line 214 and the current between the second metal line 212 and the third metal line 213, so as to measure the resistance more precisely, and the temperature of the metal gate 130 can be obtained according to the resistance, and the self-heating condition of the metal gate 130 can be obtained.
In this embodiment, a first metal line 211 and a second metal line 212 are connected to a first position of at least one metal gate 130, and a third metal line 213 and a fourth metal line 214 are connected to a second position of the metal gate 130, with a certain distance between the first position and the second position, as shown in fig. 6. Then, the resistance of the metal gate 130 may be obtained according to the current between the second metal line 212 and the third metal line 213 according to the voltage between the first metal line 211 and the fourth metal line 214. Then, the temperature of the metal gate 130 can be obtained according to the resistance, so as to obtain the self-heating condition of the metal gate 130.
In a specific application, the dummy gate 140 may be set to a floating state, when the dummy gate 140 is floating, since the electric potential between the source region and the drain region of the dummy gate 140 is equal, and when there are a plurality of dummy gates 140 between the metal gates 130, the electric potential between the source region and the drain region of the dummy gate 140 is equal, no voltage crossing exists between the source region and the drain region of the dummy gate 140, and the self-heating outside is not generated by the dummy gate 140, thereby reducing the self-heating effect of the device. The potential capable of turning off the transistor may be connected to both sides of the dummy gate 140, for example, when the dummy gate 140 is connected to a low bias voltage and when the dummy gate 140 is connected to a pFET, a high bias voltage may be connected to the dummy gate 140.
The semiconductor device provided by the embodiment of the application is described in detail above, the electric potentials at the two sides of each virtual grid electrode are equal between the metal grid electrodes, so that the electric potentials of the source region and the drain region at the two sides of the virtual grid electrode are equal, the source region and the drain region at the two sides of the virtual grid electrode have no voltage crossing, and meanwhile, the influence of short channel effect is reduced, and further, the generation of extra current and self-heating is reduced, and the self-heating of the transistor is reduced.
The embodiment of the application also provides a manufacturing method of the semiconductor device, which is shown by referring to fig. 1, and comprises the following steps:
in step S01, a substrate 100 is provided, and at least one fin structure 110 is formed on the substrate 100, the fin structures 110 being arranged along a first direction.
In this embodiment, one fin structure 110 or a plurality of fin structures 110 are formed on the substrate 100, when the fin structures 110 are formed, the fin structures 110 are arranged along a first direction, which may be a direction parallel to the substrate 100, and an isolation layer 120 may be formed between the fin structures 110, where the isolation layer 120 isolates the fin structures 110.
The fin structure 110 may be formed by depositing a semiconductor material on the substrate 100 and then depositing a hard mask material over the semiconductor material to form a hard mask layer. A photoresist layer is formed over the hard mask layer, and then the photoresist layer is sequentially subjected to an exposure process and a development process, thereby transferring the pattern of the fin structure into the photoresist layer. And etching the hard mask layer by taking the photoresist layer as a mask so as to transfer the pattern of the fin structure into the hard mask layer, thereby forming a patterned hard mask layer. The semiconductor material layer is then etched with the patterned hard mask layer as a mask to form fin structure 110. The photoresist layer and the hard mask layer may then be removed. After forming fin structure 110, a dielectric material may be deposited on substrate 100, forming an isolation layer 120 covering the surface of substrate 100 and portions of the sidewalls of fin structure 110, and fin structure 110 above isolation layer 120 may be used to form source and drain regions and channels.
The fin structure 110 may also be formed by forming an isolation layer 120 on the substrate 100, then forming a trench on the isolation layer 120, then epitaxially growing a semiconductor material in the trench to fill the trench, and then performing a planarization process to remove the semiconductor material outside the trench so that the semiconductor material in the trench is level with the isolation layer 120. Subsequently, an upper portion of the isolation layer 120 is etched away such that the top of the semiconductor material in the trench is higher than the top of the isolation layer 120, thereby forming the fin structure 110.
In step S02, at least two metal gates 130 are formed across the fin structure 110, each metal gate 130 covering a portion of the top surface and a portion of the sidewall surface of the fin structure 110, the metal gates 130 being arranged along a second direction, the second direction perpendicularly intersecting the first direction.
In this embodiment, a plurality of metal gates 130 may be formed on the fin structure 110, and the metal gates 130 may be formed on the isolation layer 130 and cover the sidewalls and the top surfaces of the fin structure 110 protruding from the isolation layer 130, where the plurality of metal gates 130 are arranged along a second direction, and the second direction perpendicularly intersects the first direction. The metal gate 130 is in close proximity to the sidewalls and top of the fin structure 110, increasing the area of the metal gate 130 surrounding the channel, where the channel is the fin structure 110 protruding from the top of the spacer 120.
The method of forming the plurality of metal gates 130 may be to deposit a metal material on the isolation layer 130 such that the metal material covers the fin structure 110, and then a planarization process may be performed on the metal material. Subsequently, a hard mask layer and a photoresist layer may be sequentially formed on the metal material, the photoresist layer is subjected to exposure and development processes, the pattern of the metal gate 130 is transferred onto the photoresist layer, and then the hard mask layer is etched with the photoresist layer as a mask, thereby transferring the pattern of the metal gate 130 onto the hard mask layer. Finally, the metal material is etched using the hard mask layer as a mask, thereby forming a plurality of metal gates 130 covering a portion of the sidewalls and a portion of the top surface of the fin structure 110. Each of the metal gates 130 has a certain interval therebetween, and the smaller the interval, the greater the density of the metal gates 130 and the greater the density of the transistors.
In step S03, at least one dummy gate 140 is disposed between at least two adjacent metal gates 130, and the electric potential of each of the two sides of the dummy gate 140 is equal.
In this embodiment, one or more dummy gates 140 may be disposed between the metal gates 130 to reduce the density of the transistor, thereby reducing the self-heating effect of the transistor, and two sides of each dummy gate 140 are connected to the same bias voltage, so that the potentials at two sides of each dummy gate 140 are equal. Thus, there is no voltage across the voltage between the source and drain regions between the dummy gate 140 and the metal gate 130, thereby reducing the generation of self-heating.
In this embodiment, a plurality of dummy gates 140 are connected between the metal gates 130, and the bias voltages on both sides of each dummy gate 140 may be high bias voltages or low bias voltages. The potentials of the source and drain regions in the plurality of dummy gates 140 are equal and equal to the potential between each of the plurality of dummy gates 140.
In this embodiment, the first metal line 211, the second metal line 212, the third metal line 213, and the fourth metal line 214 may be sequentially connected to the at least one metal gate 130, for example, the first metal line 211 and the fourth metal line 214 may be connected to two ends of the metal gate 130, the second metal line 212 and the third metal line 213 are connected to the metal gate 130 between the first metal line 211 and the fourth metal line 214, the second metal line 212 is close to the first metal line 211, and the third metal line 213 is close to the fourth metal line 214. Then, the resistance of the metal gate 130 is obtained by using the voltage between the first metal line 211 and the fourth metal line 214 and the current between the second metal line 212 and the third metal line 213, so that the temperature of the metal gate 130 can be obtained according to the resistance, and the self-heating condition of the metal gate 130 can be obtained.
In this embodiment, the first metal line 211 and the second metal line 212 are connected at a first position of at least one metal gate 130, and the third metal line 213 and the fourth metal line 214 are connected at a second position of the metal gate 130, with a certain distance between the first position and the second position. Then, the resistance of the metal gate 130 may be obtained according to the current between the second metal line 212 and the third metal line 213 according to the voltage between the first metal line 211 and the fourth metal line 214. Then, the temperature of the metal gate 130 can be obtained according to the resistance, so as to obtain the self-heating condition of the metal gate 130.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for method embodiments, since they are substantially similar to device embodiments, the description is relatively simple, with reference to the description of device embodiments in part.
The foregoing is merely a preferred embodiment of the present application, and the present application has been disclosed in the above description of the preferred embodiment, but is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.
Claims (10)
1. A semiconductor device, comprising:
a substrate, wherein at least one fin structure is formed on the substrate, and the fin structures are arranged along a first direction;
at least two metal gates spanning the fin structure, each metal gate covering a portion of a top surface and a portion of a sidewall surface of the fin structure, the metal gates being arranged along a second direction, the second direction perpendicularly intersecting the first direction;
at least one virtual grid is arranged between at least two adjacent metal grids, and the electric potential at two sides of each virtual grid is equal.
2. The device of claim 1, further comprising equalizing the potential across each of the dummy gates by:
and the two sides of each virtual grid electrode are connected with the same bias voltage.
3. The device of claim 1, further comprising:
a first metal wire, a second metal wire, a third metal wire and a fourth metal wire are sequentially connected to at least one metal gate;
and obtaining the resistance of the at least one metal gate by using the voltage between the first metal line and the fourth metal line and the current between the second metal line and the third metal line, wherein the resistance is used for obtaining the temperature of the at least one metal gate.
4. The device of claim 1, further comprising:
a first metal wire and a second metal wire are connected to a first position of at least one metal gate;
a third metal wire and a fourth metal wire are connected to the second position of the at least one metal gate;
and obtaining the resistance of the at least one metal gate by using the voltage between the first metal line and the fourth metal line and the current between the second metal line and the third metal line, wherein the resistance is used for obtaining the temperature of the at least one metal gate.
5. The device according to claim 1, characterized in that at least one dummy gate is included between said at least two adjacent metal gates, the potential on both sides of each dummy gate being equal, in particular comprising:
and a plurality of virtual gates are arranged between at least two adjacent metal gates, and the potentials of a source region and a drain region in the plurality of virtual gates are equal to each other and equal to the potential between each virtual gate in the plurality of virtual gates.
6. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein at least one fin structure is formed on the substrate, and the fin structures are arranged along a first direction;
forming at least two metal gates across the fin structure, each metal gate covering a portion of a top surface and a portion of a sidewall surface of the fin structure, the metal gates being arranged along a second direction, the second direction perpendicularly intersecting the first direction;
at least one virtual grid electrode is arranged between at least two adjacent metal grid electrodes, and the electric potential at two sides of each virtual grid electrode is equal.
7. The method according to claim 6, wherein at least one dummy gate is provided between at least two adjacent metal gates, and potentials on both sides of each dummy gate are equal, specifically comprising:
at least one virtual grid electrode is arranged between at least two adjacent metal grid electrodes, and the two sides of each virtual grid electrode are connected with the same bias voltage so as to make the electric potential at the two sides of each virtual grid electrode equal.
8. The method of manufacturing according to claim 6, further comprising:
sequentially connecting a first metal wire, a second metal wire, a third metal wire and a fourth metal wire on at least one metal gate;
and obtaining the resistance of the at least one metal gate by using the voltage between the first metal line and the fourth metal line and the current between the second metal line and the third metal line, wherein the resistance is used for obtaining the temperature of the at least one metal gate.
9. The method of manufacturing according to claim 6, further comprising:
connecting a first metal wire and a second metal wire at a first position of at least one metal gate;
and connecting a third metal wire and a fourth metal wire at a second position of the at least one metal gate.
10. The method according to claim 6, wherein at least one dummy gate is provided between at least two adjacent metal gates, and potentials on both sides of each dummy gate are equal, specifically comprising:
a plurality of virtual gates are arranged between at least two adjacent metal gates, and the potentials of a source region and a drain region in the plurality of virtual gates are equal to each other and equal to the potential between each of the plurality of virtual gates.
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| CN103295899A (en) * | 2012-02-27 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of FinFET device |
| CN106558610A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof, electronic installation |
| CN106910685A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
| CN107634088A (en) * | 2016-07-18 | 2018-01-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
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| CN103295899A (en) * | 2012-02-27 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of FinFET device |
| CN106558610A (en) * | 2015-09-25 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor device and preparation method thereof, electronic installation |
| CN106910685A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
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