CN111708577A - Method and equipment for self-adapting processor model and VR parameter - Google Patents
Method and equipment for self-adapting processor model and VR parameter Download PDFInfo
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Abstract
The invention provides a method and equipment for self-adapting processor model and VR parameters, wherein the method comprises the following steps: dividing the storage equipment into a plurality of areas, and storing VR parameters of a type of processor in each area; the access address corresponding to each area is arranged into an address mapping table, and default VR parameter information and the address mapping table are stored in a processor; responding to the power-on of the mainboard, the processor acquires the type of the processor in the system and matches the type of the processor with default VR parameter information stored in the processor; in response to the processor type not matching the default VR parameters stored in the processor, the processor accesses a region corresponding to the processor type through the address mapping table and updates the respective VR chips with the processor VR parameters stored in the corresponding region. By using the scheme of the invention, when the multiplexing mainboard module adopts various processor types to generate different configurations, the workload of manual off-line burning can be reduced, the debugging flexibility is improved, and the production cost is reduced.
Description
Technical Field
The field relates to the field of computers, and more particularly to a method and apparatus for self-adapting processor model and VR parameters.
Background
With the rapid development of various industries, the demands of customers on computer systems are different according to specific business types of various industries. Customer demand is more and more, design cycle of the product is also shortened, so the customer will consider cost factor of the product and redundant design of future product upgrade at the beginning of design, and therefore, the customer will tend to make the most use of on-chip resources of the selected chip and the board cards adopt different chip multiplexing modes, namely, the same board card can be compatible with various same-packaged processors with different performances, and the management unit adopts the on-chip resources of the selected chip, for example, a 32-bit architecture microprocessor module embedded in an Intel chip set (Innovation Engine) is used as a management unit, and meanwhile, the flexible configuration can be carried out by matching with different processors, memory capacity, hard disk capacity and the like.
Different processors can be adopted during multiplexing of the mainboard module, great difference can exist in VR (voltage regulator) design specification requirements, great difference can exist in the current magnitude required by processors with different models as main influencing factors, great difference exists in the precision range required by the processors for currents with different magnitudes, especially, VR chips are under different temperature environments, great deviation can be generated in VR current precision due to the difference of the current magnitudes, therefore, the mainboard module needs to be configured according to the processor current and the use environment temperature which are specifically adopted during multiplexing so as to meet the current precision requirement of the processors, otherwise, the processors with different models can have poor performance and great deviation of actual power consumption values under the condition that the processors adopt the same VR temperature current curve. If the mode that different configuration versions are distinguished by different PCBA numbers of the mainboard module is adopted, a large amount of firmware is required to be manually burned off line, and therefore the problems that the debugging flexibility of the mainboard module is poor, the management and control of the firmware version are complicated, the production cost is increased and the like can be caused.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method and an apparatus for adapting processor model and VR parameters, which can reduce the workload of manual off-line burning, improve the flexibility of debugging, and reduce the production cost when a multiplexing motherboard module adopts multiple processor model numbers to generate different configurations.
In view of the above object, an aspect of an embodiment of the present invention provides a method of self-adapting processor model and VR parameters, comprising the steps of:
dividing the storage equipment into a plurality of areas, and storing VR parameters of a type of processor in each area;
the access address corresponding to each area is arranged into an address mapping table, and default VR parameter information and the address mapping table are stored in a processor;
responding to the power-on of the mainboard, the processor acquires the type of the processor in the system and matches the type of the processor with default VR parameter information stored in the processor;
in response to the processor type not matching the default VR parameters stored in the processor, the processor accesses a region corresponding to the processor type through the address mapping table and updates the respective VR chips with the processor VR parameters stored in the corresponding region.
According to one embodiment of the invention, in response to the processor type not matching the default VR parameters stored in the processor, the processor accessing a region corresponding to the processor type through the address mapping table and updating the respective VR chips with the processor VR parameters stored in the corresponding region includes:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains a processor VR parameter;
storing the acquired VR parameters of the processor into the processor and covering default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
According to an embodiment of the present invention, further comprising:
and in response to the processor type being matched with the default VR parameters stored in the processor, updating the default VR parameters to the VR chips in sequence.
According to an embodiment of the present invention, further comprising:
in response to receiving an indication to update a processor VR parameter stored in a storage device, shutting down a write protection function of the storage device;
storing the new processor VR parameters in each area of the storage device in turn;
the write protection function of the storage device is turned on.
According to one embodiment of the invention, processor VR parameters include processor type, current, voltage and temperature of the processor's corresponding VR.
In another aspect of an embodiment of the present invention, there is also provided an apparatus for self-adapting a processor model and VR parameters, the apparatus including:
the dividing module is configured to divide the storage device into a plurality of areas and store VR parameters of one type in each area;
the storage module is configured to arrange the access addresses corresponding to the areas into an address mapping table and store default VR parameter information and the address mapping table into the processor;
the matching module is configured to respond to the electrification of the mainboard, and the processor acquires the type of the processor in the system and matches the type of the processor with default VR parameter information stored in the processor;
and the acquisition module is configured to respond to the fact that the processor type is not matched with the default VR parameters stored in the processor, the processor accesses the area corresponding to the processor type through the address mapping table, and updates each VR chip by using the processor VR parameters stored in the corresponding area.
According to an embodiment of the invention, the obtaining module is further configured to:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains a processor VR parameter;
storing the acquired VR parameters of the processor into the processor and covering default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
According to one embodiment of the invention, the VR system further comprises an update module configured to sequentially update default VR parameters to respective VR chips in response to a processor type matching the default VR parameters stored in the processor.
According to an embodiment of the invention, the system further comprises a refresh module configured to:
in response to receiving an indication to update a processor VR parameter stored in a storage device, shutting down a write protection function of the storage device;
storing the new processor VR parameters in each area of the storage device in turn;
the write protection function of the storage device is turned on.
According to one embodiment of the invention, processor VR parameters include processor type, current, voltage and temperature of the processor's corresponding VR.
The invention has the following beneficial technical effects: the method for adapting the model of the processor and the VR parameter provided by the embodiment of the invention divides the storage equipment into a plurality of areas, and one type of processor VR parameter is stored in each area; the access address corresponding to each area is arranged into an address mapping table, and default VR parameter information and the address mapping table are stored in a processor; responding to the power-on of the mainboard, the processor acquires the type of the processor in the system and matches the type of the processor with default VR parameter information stored in the processor; in response to the fact that the processor type is not matched with default VR parameters stored in the processor, the processor accesses an area corresponding to the processor type through an address mapping table, and updates each VR chip by using the processor VR parameters stored in the corresponding area.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method of self-adapting processor model and VR parameters in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of an apparatus for adapting processor model and VR parameters in accordance with one embodiment of the present invention;
FIG. 3 is a schematic diagram of a circuit for implementing self-adapting VR parameters, according to one embodiment of the present invention;
FIG. 4 is a schematic flow chart diagram of a method of self-adapting processor model and VR parameters in accordance with one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a method of self-adapting processor model and VR parameters. Fig. 1 shows a schematic flow diagram of the method.
As shown in fig. 1, the method may include the steps of:
s1 dividing the storage device into several areas and storing one type of processor VR parameters in each area, the storage device may use EEPROM (electrically erasable and programmable read only memory);
s2, the access address corresponding to each area is arranged into an address mapping table, and the default VR parameter information and the address mapping table are stored in a processor, the processor can use IE, each different area has a corresponding access address, the storage area corresponding to each address contains VR parameter information which needs to be adapted for different types of processing, and the whole address mapping table is formed;
s3, responding to the power-on of the mainboard, the processor acquires the processor type in the system and matches the processor type with default VR parameter information stored in the processor, the default VR parameter information stores the processor type corresponding to the VR parameter, and whether the current processor type is the same as the processor type corresponding to the VR parameter is judged;
s4, in response to the processor type not matching the default VR parameters stored in the processor, the processor accesses the area corresponding to the processor type through the address mapping table, and updates each VR chip by using the processor VR parameters stored in the corresponding area, first looks up the access address of the processor type in the address mapping table in the current system, the processor accesses the address and obtains the processor VR parameters corresponding to the address, and then updates all VR chips.
By adopting the technical scheme of the invention, when the multiplexing mainboard module adopts various processor types to generate different configurations, the workload of manual off-line burning can be reduced, the debugging flexibility is improved, and the production cost is reduced.
In a preferred embodiment of the present invention, in response to the processor type not matching the default VR parameters stored in the processor, the processor accessing a region corresponding to the processor type through the address mapping table and updating the respective VR chips with the processor VR parameters stored in the corresponding region includes:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains a processor VR parameter;
storing the acquired VR parameters of the processor into the processor and covering default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
In a preferred embodiment of the present invention, the method further comprises:
and in response to the processor type being matched with the default VR parameters stored in the processor, updating the default VR parameters to the VR chips in sequence.
In a preferred embodiment of the present invention, the method further comprises:
in response to receiving an indication to update a processor VR parameter stored in a storage device, shutting down a write protection function of the storage device;
storing the new processor VR parameters in each area of the storage device in turn;
the write protection function of the storage device is turned on. And if the processor VR parameters are newly added, storing one processor VR parameter in an area for storing the processor VR parameters, and if the processor VR parameters are completely replaced, deleting the originally stored processor VR parameters and then storing the new parameters in each area.
In a preferred embodiment of the invention, the processor VR parameters include the type of processor, the current, voltage and temperature of the processor's corresponding VR.
FIG. 3 is a schematic circuit diagram of an embodiment of the method of the present invention, in which the entire system uses a management unit processor embedded in a chipset, an SMBUS (system management bus) bus is used to implement VR working state monitoring, read CPLD (complex programmable logic device) version information and CPLD firmware upgrade, and read or upgrade EEPROM; the CPLD realizes the time sequence management of a system power supply, the communication with a chip set and the EEPROM write protection; I2C (Integrated Circuit bus) multiplexer implementing the management unit processor in switched interconnect communication with a plurality of I2C devices; the EEPROM realizes VR parameter storage adapted to processors of different models.
Selecting an EEPROM meeting the requirement of capacity according to the number of specific processing models used by a project, dividing an EEPROM space into n areas, storing VR parameters of 1 type of processor in each area, having corresponding access addresses in different areas, and forming an address mapping table (for example, taking a processor including 3 types, the addresses of the EEPROM are 0x00, 0x20 and 0x30 respectively, the corresponding parameter information is 00011110, 00001010 and 10011110, and the unused area is reserved) as a whole by including the VR parameter information which needs to be adapted for different types of processing in the storage area corresponding to each address, and storing the address mapping table and the default VR parameter information in a mirror file where the processor is located.
On the mainboard module (taking 3 types of processor models as an example), the embedded processor on the chipset outputs a group of SMBUS signals to be connected with the I2C multiplexer. The processor outputs GPIO1 and GPIO2 embedded in the chipset are connected to the CPLD, the GPIO1 is used as a processor self-adaptive processor type completion status indication, and the GPIO2 is used as an EEPROM online upgrade status indication under an operating system. The I2C multiplexer is connected with the CPLD through a path 1I 2C (I2C0) to realize firmware online upgrade and other communication of the CPLD by the processor, the path 1I 2C (I2C1) is connected with all VR chips to realize real-time VR state monitoring and VR parameter automatic adaptation, and the path 1I 2C (I2C2) connector EEPROM realizes VR parameter reading and online update stored in the EEPROM. The EEPROM is selected according to the specific using capacity, the storage space is divided into 3 partial areas, the partial areas indicate that the processor comprises 3 types of processors, the EEPROM addresses are 0x00, 0x20 and 0x30 respectively, the corresponding parameter information is 00011110, 00001010 and 10011110, unused areas are reserved, and the n parameters are similar.
Referring to fig. 3, fig. 4 is a flowchart illustrating an embodiment of a method for implementing the present invention, after the motherboard module is powered on, the processor first completes initialization and sets the GPIO1 to Low, and after the CPLD completes initialization, detects that the state of the GPIO1 is 0, and waits for the processor to perform processor type detection. The processor detects the processor type (one of 0-n models) collocated with the whole system after being started, acquires information, compares whether default information stored in a mirror image is matched with the acquired processor type, if not, acquires an EEPROM access address of VR parameters stored in a matching type processor through an address mapping table stored in a mirror image file, switches an I2C multiplexer channel to an EEPROM after acquiring the address, reads the VR parameters stored in the EEPROM according to the address acquired in the mapping table to cover the processor mirror image area originally reserving the default VR parameter information, switches the I2C multiplexer to a VR I2C channel after finishing, sequentially updates the acquired VR parameters to each VR chip, and then sets a GPIO1 to be High to inform a CPLD to execute sequential power-on; if the acquired information is matched, the processor directly sets the GPIO1 to be High to inform the CPLD to execute the power-on time sequence.
If the content information of the EEPROM needs to be updated, under the operating system, the processor informs the CPLD of setting the GPIO2 to Low to close the EEPROM write protection function, namely, the CPLD sets the write protect signal to High, at the moment, the processor switches the I2C multiplexer to the EEPROM to update the parameter information stored under the operating system to the EEPROM, after the update is completed, the processor sets the GPIO2 to High to inform the CPLD of enabling the EEPROM write protection function, namely, the CPLD sets the write protect signal to Low.
Therefore, the function of self-adapting of VR parameters of different types of processors is realized by detecting the type of the processor through the processor management unit.
By adopting the technical scheme of the invention, when the multiplexing mainboard module adopts various processor types to generate different configurations, the workload of manual off-line burning can be reduced, the debugging flexibility is improved, and the production cost is reduced.
It should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by instructing relevant hardware through a computer program, and the above programs may be stored in a computer-readable storage medium, and when executed, the programs may include the processes of the embodiments of the methods as described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.
In view of the above object, a second aspect of the embodiments of the present invention proposes an apparatus for self-adapting a processor model and VR parameters, as shown in fig. 2, the apparatus 200 includes:
the dividing module is configured to divide the storage device into a plurality of areas and store VR parameters of one type in each area;
the storage module is configured to arrange the access addresses corresponding to the areas into an address mapping table and store default VR parameter information and the address mapping table into the processor;
the matching module is configured to respond to the electrification of the mainboard, and the processor acquires the type of the processor in the system and matches the type of the processor with default VR parameter information stored in the processor;
and the acquisition module is configured to respond to the fact that the processor type is not matched with the default VR parameters stored in the processor, the processor accesses the area corresponding to the processor type through the address mapping table, and updates each VR chip by using the processor VR parameters stored in the corresponding area.
In a preferred embodiment of the present invention, the obtaining module is further configured to:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains a processor VR parameter;
storing the acquired VR parameters of the processor into the processor and covering default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
In a preferred embodiment of the present invention, the VR system further comprises an update module configured to sequentially update default VR parameters to respective VR chips in response to a processor type matching the default VR parameters stored in the processor.
In a preferred embodiment of the present invention, the apparatus further comprises a refresh module configured to:
in response to receiving an indication to update a processor VR parameter stored in a storage device, shutting down a write protection function of the storage device;
storing the new processor VR parameters in each area of the storage device in turn;
the write protection function of the storage device is turned on.
In a preferred embodiment of the invention, the processor VR parameters include the type of processor, the current, voltage and temperature of the processor's corresponding VR.
It should be particularly noted that the embodiment of the system described above employs the embodiment of the method described above to specifically describe the working process of each module, and those skilled in the art can easily think that the modules are applied to other embodiments of the method described above.
Further, the above-described method steps and system elements or modules may also be implemented using a controller and a computer-readable storage medium for storing a computer program for causing the controller to implement the functions of the above-described steps or elements or modules.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The embodiments described above, particularly any "preferred" embodiments, are possible examples of implementations and are presented merely to clearly understand the principles of the invention. Many variations and modifications may be made to the above-described embodiments without departing from the spirit and principles of the technology described herein. All such modifications are intended to be included within the scope of this disclosure and protected by the following claims.
Claims (10)
1. A method of self-adapting processor model and VR parameters, comprising the steps of:
dividing a storage device into a plurality of areas, and storing a type of processor VR parameter in each area;
arranging the access address corresponding to each region into an address mapping table, and storing default VR parameter information and the address mapping table into a processor;
in response to the power-on of a main board, the processor acquires a processor type in a system and matches the processor type with the default VR parameter information stored in the processor;
in response to the processor type not matching the default VR parameters stored in the processor, the processor accesses the region corresponding to the processor type via the address mapping table and updates the respective VR chip with the processor VR parameters stored in the corresponding region.
2. The method of claim 1, wherein, in response to the processor type not matching the default VR parameters stored in the processor, the processor accessing the region corresponding to the processor type via the address mapping table and updating each VR chip with the processor VR parameters stored in the corresponding region comprises:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains the VR parameter of the processor;
storing the acquired VR parameters of the processor into the processor and covering the default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
3. The method of claim 1, further comprising:
in response to the processor type matching the default VR parameters stored in the processor, sequentially updating the default VR parameters to respective VR chips.
4. The method of claim 1, further comprising:
in response to receiving an indication to update processor VR parameters stored in the storage device, turning off a write protection function of the storage device;
storing the new processor VR parameters in each of the regions of the storage device in turn;
and opening the write protection function of the storage device.
5. The method of claim 1, wherein the processor VR parameters include processor type, current, voltage, and temperature of the processor's corresponding VR.
6. An apparatus for self-adapting processor model and VR parameters, the apparatus comprising:
the device comprises a dividing module, a storage module and a processing module, wherein the dividing module is configured to divide a storage device into a plurality of areas and store VR parameters of one type in each area;
the storage module is configured to arrange access addresses corresponding to the regions into an address mapping table and store default VR parameter information and the address mapping table into a processor;
a matching module configured to respond to a power-on of a motherboard, the processor obtaining a processor type in a system and matching the processor type with the default VR parameter information stored in the processor;
an acquisition module configured to, in response to the processor type not matching the default VR parameters stored in the processor, the processor accessing the region corresponding to the processor type through the address mapping table and updating each VR chip with the processor VR parameters stored in the corresponding region.
7. The device of claim 6, wherein the acquisition module is further configured to:
the processor accesses a corresponding area in the storage device corresponding to the processor type through the address mapping table and obtains the VR parameter of the processor;
storing the acquired VR parameters of the processor into the processor and covering the default VR parameter information;
and the processor sequentially updates the acquired VR parameters of the processor to each VR chip.
8. The apparatus of claim 6, further comprising an update module configured to sequentially update the default VR parameters to respective VR chips in response to the processor type matching the default VR parameters stored in the processor.
9. The device of claim 6, further comprising a refresh module configured to:
in response to receiving an indication to update processor VR parameters stored in the storage device, turning off a write protection function of the storage device;
storing the new processor VR parameters in each of the regions of the storage device in turn;
and opening the write protection function of the storage device.
10. The apparatus of claim 6, in which the processor VR parameters include processor type, current, voltage, and temperature of the processor's corresponding VR.
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| CN202010471913.7A CN111708577A (en) | 2020-05-29 | 2020-05-29 | Method and equipment for self-adapting processor model and VR parameter |
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| CN202010471913.7A CN111708577A (en) | 2020-05-29 | 2020-05-29 | Method and equipment for self-adapting processor model and VR parameter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114035842A (en) * | 2022-01-07 | 2022-02-11 | 飞腾信息技术有限公司 | Firmware configuration method, computing system configuration method, computing device and equipment |
| CN114281418A (en) * | 2021-11-30 | 2022-04-05 | 施耐德万高（天津）电气设备有限公司 | Dual-power multi-platform MCU self-adaption method and device |
-
2020
- 2020-05-29 CN CN202010471913.7A patent/CN111708577A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114281418A (en) * | 2021-11-30 | 2022-04-05 | 施耐德万高（天津）电气设备有限公司 | Dual-power multi-platform MCU self-adaption method and device |
| CN114035842A (en) * | 2022-01-07 | 2022-02-11 | 飞腾信息技术有限公司 | Firmware configuration method, computing system configuration method, computing device and equipment |
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Application publication date: 20200925 |