CN111698079A

CN111698079A - Nine-dimensional hyper-chaotic communication encryption circuit

Info

Publication number: CN111698079A
Application number: CN202010608222.7A
Authority: CN
Inventors: 刘美婷; 于文新; 王俊年; 蒋丹; 陈宇; 李燕; 陈娟; 陆洋; 李瑞奇; 周躜波; 卞雨妍; 赵雨晴
Original assignee: Hunan University of Science and Technology
Current assignee: Hunan University of Science and Technology
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-09-22
Anticipated expiration: 2040-06-30
Also published as: CN111698079B

Abstract

The invention discloses a nine-dimensional hyper-chaotic communication encryption circuit, which comprises a signal source, a drive circuit, a response circuit, an encryption circuit and a decryption circuit, wherein the signal source is connected with the drive circuit; the encryption circuit encrypts signals provided by the signal source, the output end of the encryption circuit is connected with the first input end of the decryption circuit, the decryption circuit decrypts the signals encrypted by the encryption circuit, and the output end of the decryption circuit outputs the decrypted signals. The second output end of the driving circuit is connected with the second input end of the encryption circuit to provide a high-dimensional chaotic signal to cover a signal to be encrypted, the second output end of the response circuit is connected with the second input end of the decryption circuit to output a high-dimensional signal for decryption, and the output end of the driving circuit is connected with the input end of the response circuit to realize coupling synchronization. When the parameters change, the nine-dimensional hyper-chaotic communication encryption circuit is in a chaotic state, has a large parameter range and a large secret key space, has higher security and is very suitable for the security transmission of signals.

Description

Nine-dimensional hyper-chaotic communication encryption circuit

Technical Field

The invention relates to the field of communication, in particular to a nine-dimensional hyper-chaotic communication encryption circuit.

Background

Chaos (chaos) refers to unpredictable, random-like motion exhibited by a deterministic dynamical system due to sensitivity to an initial value. Since 1990, chaotic secure communication and chaotic encryption technology have been a hot topic in the field of international electronic communication. To date, the applications of chaos in secure communications can be roughly divided into three categories: the first type is secret communication directly using chaos; the second type is secret communication by using synchronous chaotic signals; the third category is digital encryption communication based on chaotic sequences. The second category is a current research hotspot, which has become a new field of high-tech technology, and with the increasing communication, it is imperative to enhance the communication security.

The complicated dynamic behavior, the sensitivity to the initial condition and the long-term unpredictable behavior of the chaotic system, and the high-capacity dynamic storage capacity, the low power, the low observability and the low equipment cost of the chaotic system make the chaos very suitable for secret communication and suitable for being used as a carrier of the secret communication.

The chaos covering secret communication is proposed by Kocarev and Cuomo, etc., an autonomous chaotic system is used as a coder, an information signal is superposed on a chaotic output signal of the autonomous chaotic system and is transmitted through a channel, a decoder synchronizes another equivalent chaotic system by using a transmitted signal, the equivalent chaotic system outputs a reconstructed chaotic signal, and then the reconstructed chaotic signal is subtracted from the transmitted signal to recover the information signal. In addition, the chaotic system is determined by itself and is completely determined by the equation, parameters and initial conditions of the nonlinear system, so that a plurality of uncorrelated and random-like determined chaotic sequences can be easily generated and reproduced.

The bandwidth of the low-dimensional autonomous chaotic system is narrow, the effect is poor when the low-dimensional autonomous chaotic system is applied to secret communication, and signals are easy to decipher. However, the dynamic behavior of the high-dimensional hyper-chaotic system is more complex and more difficult to predict, and the application of the high-dimensional hyper-chaotic system in secret communication can greatly improve the secret degree of signal transmission and greatly enhance the attack resistance.

Disclosure of Invention

In order to solve the technical problem, the invention provides a nine-dimensional hyper-chaotic communication encryption circuit.

The technical scheme for solving the problems is as follows: a nine-dimensional hyper-chaotic communication encryption circuit comprises a signal source, a power supply, a drive circuit, a response circuit, an encryption circuit and a decryption circuit; the power supply is connected with the driving circuit, the response circuit, the encryption circuit and the decryption circuit to provide stable working voltage for the whole circuit, the signal source is connected with the first input end of the encryption circuit, the second output end of the driving circuit is connected with the second input end of the encryption circuit, the output end of the encryption circuit is connected with the first input end of the decryption circuit, the output end of the response circuit is connected with the second input end of the decryption circuit, the output end of the decryption circuit outputs a decrypted signal, and the output end of the driving circuit is connected with the input end of the response circuit to realize coupling synchronization; the signal source provides a signal S needing to be kept secret for the whole secret communication circuit, the two signals of the high-dimensional hyperchaotic signal Y, the S and the Y are output from the second output end of the driving circuit and are superposed through the encryption circuit to obtain S1= -S-Y, so that the signal S needing to be kept secret is covered by the high-dimensional hyperchaotic signal Y generated by the driving circuit, the encryption circuit outputs an encrypted signal S1 to the first input end of the decryption circuit, the high-dimensional hyperchaotic signal Y _2 output from the response circuit is used for decryption and is input to the second input end of the decryption circuit, the two signals of the S1 and the Y _2 are superposed through the decryption circuit to obtain S2= -S1-Y _2, the output end of the decryption circuit outputs a decrypted signal S2, after the driving system and the response circuit are synchronized, the signal Y _2 generated by the response circuit cancels the signal Y in the encrypted signal S1, the signal S2 obtained after decryption has a waveform identical to the original signal S before encryption.

In the nine-dimensional hyper-chaotic communication encryption circuit, the driving circuit comprises sixty-first to hundred-second resistors, twenty-first to thirty-eighth operational amplifiers, tenth to eighteenth capacitors and sixth to tenth analog multipliers; a sixty-first resistor, a sixty-second resistor, a sixty-third resistor, a sixty-fourth resistor, a sixty-fifth resistor, a twenty-first operational amplifier and a tenth capacitor form a first inverting addition integrator, a sixty-sixth resistor, a sixty-seventh resistor, a twenty-second operational amplifier form a first inverter, and the first inverting addition integrator and the first inverter form a first dimensional circuit; a sixty-eight resistor, a sixty-nine resistor, a seventy-one resistor, a twenty-third operational amplifier, an eleventh capacitor and a sixth analog multiplier form a second inverting addition integrator, a seventy-two resistor, a seventy-three resistor and a twenty-fourth operational amplifier form a second inverter, and the second inverting addition integrator and the second inverter form a second dimensional circuit; a seventy-fourth resistor, a seventy-fifth resistor, a twenty-fifth operational amplifier, a twelfth capacitor and a seventh analog multiplier form a third inverting addition integrator, a seventy-sixth resistor, a seventy-seventh resistor, a twenty-sixth operational amplifier form a third inverter, and the third inverting addition integrator and the third inverter form a third three-dimensional circuit; a seventy-eight resistor, a seventy-nine resistor, a twenty-seventh operational amplifier, a thirteenth capacitor and an eighth analog multiplier form a fourth inverting addition integrator, an eighty resistor, an eighty-first resistor and a twenty-eighth operational amplifier form a fourth inverter, and the fourth inverting addition integrator and the fourth inverter form a fourth dimensional circuit; the eighty-two resistor, the eighty-three resistor, the eighty-four resistor, the twenty-ninth operational amplifier, the fourteenth capacitor and the ninth analog multiplier form a fifth inverting addition integrator, the eighty-five resistor, the eighty-six resistor and the thirty operational amplifier form a fifth inverter, and the fifth inverting addition integrator and the fifth inverter form a fifth dimensional circuit; the eighty-seventh resistor, the eighty-eighth resistor, the eighty-ninth resistor, the thirty-first operational amplifier and the fifteenth capacitor form a sixth inverting addition integrator, the ninety resistor, the ninety-first resistor and the thirty-second operational amplifier form a sixth inverter, and the sixth inverting addition integrator and the sixth inverter form a sixth-dimensional circuit; the ninety-second resistor, the ninety-third resistor, the thirty-third operational amplifier, the sixteenth capacitor and the tenth analog multiplier form a seventh inverting addition integrator, the ninety-fourth resistor, the ninety-fifth resistor, the thirty-fourth operational amplifier form a seventh inverter, and the seventh inverting addition integrator and the seventh inverter form a seventh dimensional circuit; the ninety-sixth resistor, the ninety-seventh resistor, the thirty-fifth operational amplifier and the seventeenth capacitor form an eighth inverting addition integrator, the ninety-eighth resistor, the ninety-ninth resistor, the thirty-sixth operational amplifier form an eighth inverter, and the eighth inverting addition integrator and the eighth inverter form an eighth-dimensional circuit; the first hundredth resistor, the thirty-seventh operational amplifier and the eighteenth capacitor form a ninth inverting addition integrator, the first hundredth resistor and the thirty-eighth operational amplifier form a ninth inverter, and the ninth inverting addition integrator and the ninth inverter form a ninth dimensional circuit.

In the first-dimensional circuit of the nine-dimensional driving circuit, one end of a sixty-first resistor, one end of a sixty-second resistor, one end of a sixty-third resistor, one end of a sixty-fourth resistor and one end of a sixty-fifth resistor are connected together and connected to the inverting input terminal of a twenty-first operational amplifier, the other end of the sixty-first resistor is connected to the output terminal of a thirty-fourth operational amplifier in the seventh-dimensional circuit, the other end of the sixty-second resistor is connected to the output terminal of a thirty-seventh operational amplifier in the ninth-dimensional circuit, the other end of the sixty-third resistor is connected to the output terminal of a twenty-eighth operational amplifier in the fourth-dimensional circuit, the other end of the sixty-fourth resistor is connected to the output terminal of a twenty-fourth operational amplifier in the second-dimensional circuit, the other end of the sixty-fifth resistor is connected to the output terminal of a twenty-first operational amplifier in the first-dimensional circuit, the tenth capacitor is connected between the inverting input end and the output end of the twenty-first operational amplifier in a bridging manner, the output end of the twenty-first operational amplifier is connected to the inverting input end of the twenty-second operational amplifier after being connected with the sixty-sixth resistor, the non-inverting input end of the twenty-second operational amplifier is grounded, and the sixty-seventh resistor is connected between the inverting input end and the output end of the twenty-second operational amplifier in a bridging manner.

In the ninth-dimensional driving circuit, one end of a sixty-eight resistor, one end of a sixty-nine resistor, one end of a seventy resistor and one end of a seventy-first resistor are connected together and connected to the inverting input end of a twenty-third operational amplifier, the other end of the sixty-eight resistor is connected with the output end of the twenty-ninth operational amplifier in the fifth-dimensional circuit, the other end of the sixty-nine resistor is connected with the output end of the twenty-third operational amplifier in the second-dimensional circuit, the other end of the seventy resistor is connected with the output end of a twenty-second operational amplifier in the first-dimensional circuit, the other end of the seventy-first resistor is connected with the output end of a sixth analog multiplier, the other input end of the sixth analog multiplier is connected with the output end of a twenty-fifth operational amplifier in the third-dimensional circuit, one input end of the sixth analog multiplier is connected with the output end of the twenty-first operational amplifier in the, the non-inverting input end of the twenty-third operational amplifier is grounded, the eleventh capacitor is bridged between the inverting input end and the output end of the twenty-third operational amplifier, the output end of the twenty-third operational amplifier is connected to the inverting input end of the twenty-fourth operational amplifier through the seventy-second resistor, the non-inverting input end of the twenty-fourth operational amplifier is grounded, and the seventy-third resistor is bridged between the inverting input end and the output end of the twenty-fourth operational amplifier.

In the ninth-dimensional driving circuit, one end of a seventy-fourth resistor and one end of a seventy-fifth resistor are connected together and connected to the inverting input end of a twenty-fifth operational amplifier, the other end of the seventy-fourth resistor is connected with the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, the other end of the seventy-fifth resistor is connected with the output end of a seventh analog multiplier, the other input end of the seventh analog multiplier is connected with the output end of a twenty-third operational amplifier in the second-dimensional circuit, one input end of the seventh analog multiplier is connected with the output end of a twenty-second operational amplifier in the first-dimensional circuit, the non-inverting input end of the twenty-fifth operational amplifier is grounded, a twelfth crossover capacitor is arranged between the inverting input end and the output end of the twenty-fifth operational amplifier, the output end of the twenty-fifth operational amplifier is connected to the inverting input end of the twenty-sixth operational amplifier through a seventy-sixth resistor, the non-inverting input end of the twenty-sixth operational amplifier is grounded, and the seventy-seventh resistor is connected between the inverting input end and the output end of the twenty-sixth operational amplifier in a bridging manner.

In the ninth-dimensional driving circuit, one end of a seventy-eight resistor and one end of a seventy-nine resistor are connected together and connected to the inverting input end of a twenty-seventh operational amplifier, the other end of the seventy-eight resistor is connected with the output end of a twenty-seventh operational amplifier in the fourth-dimensional circuit, the other end of the seventy-nine resistor is connected with the output end of an eighth analog multiplier, one input end of the eighth analog multiplier is connected with the output end of a twenty-fifth operational amplifier in the third-dimensional circuit, the other input end of the eighth analog multiplier is connected with the output end of a twenty-third operational amplifier in the second-dimensional circuit, the non-inverting input end of the twenty-seventh operational amplifier is grounded, a thirteenth capacitor is connected between the inverting input end and the output end of the twenty-seventh operational amplifier, the output end of the twenty-seventh operational amplifier is connected to the inverting input end of the twenty-eighth operational amplifier through the eighty resistor, the non-inverting input terminal of the twenty-eighth operational amplifier is grounded, and the eighty-first resistor is connected between the inverting input terminal and the output terminal of the twenty-eighth operational amplifier in a bridging manner.

In a fifth-dimensional circuit of the nine-dimensional driving circuit, one end of an eighty-two resistor, one end of an eighty-three resistor and one end of an eighty-four resistor are connected together and connected to an inverting input end of a twenty-ninth operational amplifier, the other end of the eighty-two resistor is connected with an output end of a twenty-third operational amplifier in the second-dimensional circuit, the other end of the eighty-three resistor is connected with an output end of a thirtieth operational amplifier in the fifth-dimensional circuit, the other end of the eighty-four resistor is connected with an output end of a ninth analog multiplier, one input end of the ninth analog multiplier is connected with an output end of a twenty-fifth operational amplifier in the third-dimensional circuit, the other input end of the ninth analog multiplier is connected with an output end of a twenty-fourth operational amplifier in the second-dimensional circuit, a non-inverting input end of the twenty-nine operational amplifier is grounded, and a fourteenth bridging capacitor is arranged between the inverting input, the output end of the twenty-ninth operational amplifier is connected to the inverting input end of the thirtieth operational amplifier through an eighty-fifth resistor, the non-inverting input end of the thirtieth operational amplifier is grounded, and an eighty-sixth resistor is bridged between the inverting input end and the output end of the thirtieth operational amplifier;

in the ninth-dimensional circuit of the ninth-dimensional driving circuit, one end of an eighty-seventh resistor, one end of an eighty-eighth resistor and one end of an eighty-ninth resistor are connected together and connected to the inverting input end of a thirty-first operational amplifier, the other end of the eighty-seventh resistor is connected with the output end of a twenty-ninth operational amplifier in the fifth-dimensional circuit, the other end of the eighty-eighth resistor is connected with the output end of a twenty-eighth operational amplifier in the fourth-dimensional circuit, the other end of the eighty-ninth resistor is connected with the output end of a thirty-first operational amplifier in the sixth-dimensional circuit, the non-inverting input end of the thirty-first operational amplifier is grounded, a fifteenth capacitor is connected between the inverting input end and the output end of the thirty-first operational amplifier in a bridging manner, the output end of the thirty-first operational amplifier is connected to the inverting input end of a thirty-second operational amplifier through a ninety, the ninety-first resistor is connected across the inverting input and the output of the thirty-second operational amplifier.

In the seventh dimension circuit of the nine-dimension driving circuit, one end of a ninety second resistor and one end of a ninety third resistor are connected together and connected to the inverting input end of a thirty third operational amplifier, the other end of the ninety second resistor is connected with the output end of a thirty third operational amplifier in the seventh dimension circuit, the other end of the ninety third resistor is connected with the output end of a tenth analog multiplier, one input end of the tenth analog multiplier is connected with the output end of a twenty seventh operational amplifier in the fourth dimension circuit, the other input end of the tenth analog multiplier is connected with the output end of a twenty third operational amplifier in the second dimension circuit, the non-inverting input end of the thirty third operational amplifier is grounded, a sixteenth capacitor is connected between the inverting input end and the output end of the thirty third operational amplifier, and the output end of the thirty third operational amplifier is connected with the input end of the thirty fourth operational amplifier through the ninety fourth resistor, the non-inverting input terminal of the thirty-fourth operational amplifier is grounded, and the ninety-fifth resistor is connected between the inverting input terminal and the output terminal of the thirty-fourth operational amplifier in a bridge manner.

In the ninth-dimensional circuit, one end of the ninety-sixth resistor, one end of a ninety seventh resistor is connected together and connected to the inverting input end of the thirty-fifth operational amplifier, the other end of a ninety sixth resistor is connected with the output end of a thirty-fifth operational amplifier in the eighth-dimensional circuit, the other end of the ninety seventh resistor is connected with the output end of a twenty-fourth operational amplifier in the second-dimensional circuit, the non-inverting input end of the thirty-fifth operational amplifier is grounded, a seventeenth capacitor is connected between the inverting input end and the output end of the thirty-fifth operational amplifier in a bridging mode, the output end of the thirty-fifth operational amplifier is connected to the input end of the thirty-sixth operational amplifier through a ninety-eighth resistor, the non-inverting input end of the thirty-eighth operational amplifier is grounded, and a ninety-ninth resistor is connected between the inverting input end and the output end of.

In the ninth-dimensional circuit of the nine-dimensional driving circuit, one end of a first hundred resistor is connected with the inverting input end of a thirty-seventh operational amplifier, the other end of the first hundred resistor is connected with the output end of a twenty-second operational amplifier in the first-dimensional circuit, the non-inverting input end of the thirty-seventh operational amplifier is grounded, an eighteenth capacitor is bridged between the inverting input end and the output end of the thirty-seventh operational amplifier, the output end of the thirty-seventh operational amplifier is connected to the input end of a thirty-eighth operational amplifier through a first hundred-zero resistor, the non-inverting input end of the thirty-eighth operational amplifier is grounded, and a first hundred-zero second resistor is bridged between the inverting input end and the output end of the thirty-eighth operational.

In the nine-dimensional hyper-chaotic communication encryption circuit, in the nine-dimensional driving circuit, the output ends of the twenty-second operational amplifier, the twenty-fourth operational amplifier, the twenty-sixth operational amplifier, the twenty-eighth operational amplifier, the thirtieth operational amplifier, the thirty-second operational amplifier, the thirty-fourth operational amplifier, the thirty-sixth operational amplifier and the thirty-eighth operational amplifier are led out to be used as the output end of the driving circuit for coupling synchronization, so that the response system and the driving system are synchronized, and the output end of the twenty-third operational amplifier is led out to be used as the other output end of the driving circuit to be used as a high-dimensional signal to cover a signal to be transmitted.

In the nine-dimensional hyper-chaotic communication encryption circuit, the response circuit includes the first to sixty resistors, the third to twentieth operational amplifiers, the first to ninth capacitors, and the first to fifth analog multipliers, which correspond to the sixty-first to one-to-one: the response circuit is added with a controller on the basis of the drive circuit, and ensures the coupling coefficient required by the synchronization of the two chaotic systems, so that the drive system and the response system are synchronized.

The encryption circuit comprises a third-to-zero resistor, a fourth-to-zero resistor, a fifth-to-zero resistor and a first operational amplifier, wherein one end of the third-to-zero resistor is led out to serve as a first input end of the encryption circuit and is used for receiving effective signals to be encrypted, the other end of the third-to-zero resistor is connected with an inverting input end of the first operational amplifier, one end of the fourth-to-zero resistor is led out to serve as a second input end of the encryption circuit and is used for receiving signals output by a second output end of the driving circuit, the other end of the fourth-to-zero resistor is connected with the inverting input end of the first operational amplifier, a non-inverting input end of the first operational amplifier is grounded, the fifth-to-zero resistor is connected between the inverting input end and the output end of the first operational amplifier in a bridging mode, and the output.

The decryption circuit comprises a first hundred-zero-six resistor, a first hundred-zero-seven resistor, a first hundred-zero-eight resistor and a second operational amplifier, wherein one end of the first hundred-zero-six resistor is led out to serve as a first input end of the decryption circuit and is used for receiving a signal to be decrypted, the other end of the first hundred-zero-six resistor is connected with an inverting input end of the second operational amplifier, one end of the first hundred-zero-seven resistor is led out to serve as a second input end of the decryption circuit and is used for receiving a decryption signal output by the driving system, the other end of the first hundred-zero-seven resistor is connected with an inverting input end of the second operational amplifier, a non-inverting input end of the second operational amplifier is grounded, the first hundred-zero-eight resistor is bridged between the inverting input end and an output end of the second operational amplifier.

The invention has the beneficial effects that: the signal source of the invention is effective information which needs to be transmitted, a signal S which needs to be kept secret is provided for the whole secret communication circuit, a high-dimensional hyperchaotic signal Y is output from a second output end of a driving circuit, the S and the Y are superposed through an encryption circuit to obtain S1= -S-Y, so that the high-dimensional hyperchaotic signal Y generated by the driving circuit covers the signal S which needs to be kept secret, the encryption circuit outputs an encrypted signal S1 to a first input end of a decryption circuit, the high-dimensional hyperchaotic signal Y _2 output from a response circuit is used for decryption and is input to a second input end of the decryption circuit, the S1 and the Y _2 are superposed through the decryption circuit to obtain S2= -S1-Y _2, the output end of the decryption circuit outputs a decrypted signal S2, the high-dimensional hyperchaotic signal Y _2 generated by the response circuit cancels the signal Y in the encrypted signal S1 after the driving system and the response circuit are synchronized, the signal S2 obtained after decryption has a waveform identical to the original signal S before encryption. The invention relates to a high-dimensional hyperchaotic secret communication circuit, which has a large parameter range in a chaotic state and a larger secret key space when parameters change. The nine-dimensional hyper-chaotic communication encryption circuit has complex dynamics property, has higher sensitivity of errors caused by parameters, has faster divergence rate of errors caused by identification, estimation or prediction, has index separation and stretch folding transformation in different directions, has a local chaotic structure, has good confidentiality and safety, and is very suitable for confidential transmission of signals.

Drawings

FIG. 1 is a block diagram of the present invention.

Fig. 2 is a circuit diagram of the driving circuit in fig. 1.

Fig. 3 is a circuit diagram of the response circuit of fig. 1.

Fig. 4 is a circuit diagram of the encryption circuit of fig. 1.

Fig. 5 is a circuit diagram of the decryption circuit of fig. 1.

Detailed Description

The invention is further described below with reference to the figures and examples.

As shown in fig. 1, a nine-dimensional hyper-chaotic communication encryption circuit includes a signal source, a power supply, a driving circuit, a response circuit, an encryption circuit, and a decryption circuit. The encryption circuit is composed of an addition circuit consisting of an operational amplifier and a resistor. The power supply is connected with the driving circuit, the response circuit, the encryption circuit and the decryption circuit to provide a stable working power supply for the whole circuit, the signal source is a signal needing encryption and is connected with the first input end of the encryption circuit, the output end of the driving circuit is connected with the input end of the response circuit, the second output end of the driving circuit is connected with the second input end of the encryption circuit, the second output end of the response circuit is connected with the second input end of the decryption circuit, the output end of the encryption circuit is connected with the first input end of the decryption circuit, the output end of the encryption circuit outputs an encrypted signal, and the output end of the decryption circuit outputs a decrypted signal.

As shown in FIG. 2, the driving circuit includes a twenty-first operational amplifier U21, a twenty-second operational amplifier U22, a twenty-third operational amplifier U23, a twenty-fourth operational amplifier U24, a twenty-fifth operational amplifier U25, a twenty-sixth operational amplifier U26, a twenty-seventh operational amplifier U27, a twenty-eighth operational amplifier U28, a twenty-ninth operational amplifier U29, a thirty-fifth operational amplifier U30, a thirty-eleventh operational amplifier U31, a thirty-second operational amplifier U32, a thirty-third operational amplifier U33, a thirty-fourth operational amplifier U34, a thirty-fifth operational amplifier U35, a thirty-sixth operational amplifier U36, a thirty-seventh operational amplifier U37, a thirty-eighth operational amplifier U38, a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, a sixth resistor R66, Sixty-seventh resistor R67, sixty-eighth resistor R67, sixty-ninth resistor R67, seventy-first resistor R67, seventy-second resistor R67, seventy-third resistor R67, seventy-fourth resistor R67, seventy-fifth resistor R67, seventy-sixth resistor R67, seventy-seventh resistor R67, seventy-eighth resistor R67, seventy-ninth resistor R67, eighty-tenth resistor R67, eighty-twelfth resistor R67, eighty-third resistor R67, eighty-fourth resistor R67, eighty-fifth resistor R67, eighty-sixth resistor R67, eighty-seventh resistor R67, eighty-eighth resistor R67, eighty-tenth resistor R67, ninety-ninth resistor R67, ninety-ninth resistor R67, nineteenth resistor R67, seventy-ninth resistor R67, A first hundred resistor R100, a first hundred-zero resistor R101, a second hundred-zero resistor R102, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a sixth analog multiplier A6, a seventh analog multiplier a7, an eighth analog multiplier A8, a ninth analog multiplier a9, and a tenth analog multiplier a 10; a sixty-first resistor R61, a sixty-second resistor R62, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, a twenty-first operational amplifier U21 and a tenth capacitor C10 form a first inverting addition integrator, a sixty-sixth resistor R66, a sixty-seventh resistor R67 and a twenty-second operational amplifier U22 form a first inverter, and the first inverting addition integrator and the first inverter form a first dimensional circuit; a sixty-eight resistor R68, a sixty-nine resistor R69, a seventy resistor R70, a seventy-one resistor R71, a twenty-third operational amplifier U23, an eleventh capacitor C11 and a sixth analog multiplier A6 form a second inverting addition integrator, a seventy-two resistor R72, a seventy-three resistor R73 and a twenty-fourth operational amplifier U24 form a second inverter, and the second inverting addition integrator and the second inverter form a second dimensional circuit; a seventy-fourth resistor R74, a seventy-fifth resistor R75, a twenty-fifth operational amplifier U25, a twelfth capacitor C12 and a seventh analog multiplier A7 form a third inverting addition integrator, a seventy-sixth resistor R76, a seventy-seventh resistor R77 and a twenty-sixth operational amplifier U26 form a third inverter, and the third inverting addition integrator and the third inverter form a third-dimensional circuit; a seventy-eight resistor R78, a seventy-nine resistor R79, a twenty-seventh operational amplifier U27, a thirteenth capacitor C13 and an eighth analog multiplier A8 form a fourth inverting addition integrator, an eighty resistor R80, an eighty-first resistor R81 and a twenty-eighth operational amplifier U28 form a fourth inverter, and the fourth inverting addition integrator and the fourth inverter form a fourth dimensional circuit; an eighty-two resistor R82, an eighty-three resistor R83, an eighty-four resistor R84, a twenty-ninth operational amplifier U29, a fourteenth capacitor C14 and a ninth analog multiplier A9 form a fifth inverting addition integrator, an eighty-five resistor R85, an eighty-six resistor R86 and a thirtieth operational amplifier U30 form a fifth inverter, and the fifth inverting addition integrator and the fifth inverter form a fifth dimensional circuit; an eighty-seventh resistor R87, an eighty-eighth resistor R88, an eighty-ninth resistor R89, a thirty-first operational amplifier U31 and a fifteenth capacitor C15 form a sixth inverting addition integrator, a ninety resistor R90, a ninety first resistor R91 and a thirty-second operational amplifier U32 form a sixth inverter, and the sixth inverting addition integrator and the sixth inverter form a sixth-dimensional circuit; the ninety-second resistor R92, the ninety-third resistor R93, the thirty-third operational amplifier U33, the sixteenth capacitor C16 and the tenth analog multiplier A10 form a seventh inverting and adding integrator, the ninety-fourth resistor R94, the ninety-fifth resistor R95 and the thirty-fourth operational amplifier U34 form a seventh inverter, and the seventh inverting and adding integrator and the seventh inverter form a seventh dimensional circuit; the ninety-sixth resistor R96, the ninety-seventh resistor R97, the thirty-fifth operational amplifier U35 and the seventeenth capacitor C17 form an eighth inverting and adding integrator, the ninety-eighth resistor R98, the ninety-ninth resistor R99 and the thirty-sixth operational amplifier U36 form an eighth inverter, and the eighth inverting and adding integrator and the eighth inverter form an eighth-dimensional circuit; the first hundred resistor R100, the thirty-seventh operational amplifier U37 and the eighteenth capacitor C18 form a ninth inverting and adding integrator, the first hundred-zero first resistor R101, the first hundred-zero second resistor R102 and the thirty-eighth operational amplifier U38 form a ninth inverter, and the ninth inverting and adding integrator and the ninth inverter form a ninth-dimensional circuit.

In a fifth-dimensional circuit of the nine-dimensional driving circuit, one end of an eighty-two resistor, one end of an eighty-three resistor and one end of an eighty-four resistor are connected together and connected to an inverting input end of a twenty-ninth operational amplifier, the other end of the eighty-two resistor is connected with an output end of a twenty-third operational amplifier in the second-dimensional circuit, the other end of the eighty-three resistor is connected with an output end of a thirtieth operational amplifier in the fifth-dimensional circuit, the other end of the eighty-four resistor is connected with an output end of a ninth analog multiplier, one input end of the ninth analog multiplier is connected with an output end of a twenty-fifth operational amplifier in the third-dimensional circuit, the other input end of the ninth analog multiplier is connected with an output end of a twenty-fourth operational amplifier in the second-dimensional circuit, a non-inverting input end of the twenty-nine operational amplifier is grounded, and a fourteenth bridging capacitor is arranged between the inverting input, the output end of the twenty-ninth operational amplifier is connected to the inverting input end of the thirtieth operational amplifier through an eighty-five resistor, the non-inverting input end of the thirtieth operational amplifier is grounded, and an eighty-six resistor is connected between the inverting input end and the output end of the thirtieth operational amplifier in a bridging mode.

As shown in fig. 3, the response circuit includes fourth resistors R4 to sixty resistors R60 corresponding to sixty-first resistors R61 to sixth one-hundred-second resistors R102, twenty-first operational amplifiers U21 to thirty-eighth operational amplifiers U38, tenth capacitors C10 to eighteenth capacitors C18, and sixth analog multipliers A6 to tenth analog multipliers a10 in the driving circuit, the third operational amplifiers U3 to twentieth operational amplifiers U20, the first capacitors C1 to ninth capacitors C9, and the first analog multipliers a1 to fifth analog multipliers a5, and the connection relationship between the components in the response circuit is substantially the same as the connection relationship between the components in the driving circuit, except that: the response circuit is added with a controller on the basis of the drive circuit, and ensures the coupling coefficient required by the synchronization of the two chaotic systems, so that the drive system and the response system are synchronized. The output of the fifth operational amplifier U5 in the response circuit, Y _2, serves as the output of the response circuit for signal decryption.

As shown in fig. 4, the encryption circuit includes a one hundred zero three resistor R103 and a one hundred zero four resistor R104, one end of a fifth zero resistance R105 and a first operational amplifier U1 is led out to be used as a first input end of an encryption circuit, and is used for receiving an effective signal S to be encrypted, the other end of the third zero resistance R103 is connected with an inverting input end of a first operational amplifier U1, one end of a fourth zero resistance R104 is led out to be used as a second input end of the encryption circuit, and is used for receiving a signal Y output by a second output end of a driving circuit, the other end of the fourth zero resistance R104 is connected with an inverting input end of a first operational amplifier U1, a non-inverting input end of the first operational amplifier U1 is grounded, the fifth zero resistance R105 is connected between the inverting input end and the output end of the first operational amplifier U1 in a bridging mode, and the output end of the first operational amplifier U1 is used as an output end S1 of the encryption circuit.

As shown in fig. 5, the decryption circuit includes a one hundred sixth R106 resistor, a one hundred seventh R107 resistor, one end of a first hundred-zero eight resistor R108 and a second operational amplifier U2 is led out to be used as a first input end of a decryption circuit and is used for receiving a signal S1 to be decrypted, the other end of the first hundred-zero six resistor R106 is connected with an inverting input end of a second operational amplifier U2, one end of a first hundred-zero seven resistor R107 is led out to be used as a second input end of the decryption circuit and is used for receiving a decryption signal Y _2 output in a driving system, the other end of the first hundred-zero seven resistor R107 is connected with an inverting input end of the second operational amplifier U2, a non-inverting input end of the second operational amplifier is grounded, the first hundred-zero eight resistor R108 is connected between the inverting input end and an output end of the second operational amplifier U2 in a bridging mode, and the output end of the second operational amplifier is used as an output end S2 of.

As shown in fig. 1, 4 and 5, a function generator is used as a signal source, which is effective information to be transmitted, to provide a signal S to be kept secret for the whole secret communication circuit, a high-dimensional hyper-chaotic signal Y is output from a driving circuit, and the two signals S and Y are superposed through an encryption circuit to obtain S1= -S-Y, so that the signal S to be kept secret is covered by the high-dimensional hyper-chaotic signal Y generated by the driving circuit, the encryption circuit outputs an encrypted signal S1 to a decryption circuit, the high-dimensional hyper-chaotic signal Y _2 output from a response circuit is used for decrypting the signal, the two signals S1 and Y _2 are superposed through the decryption circuit to obtain S2= -S1-Y _2, the output end of the decryption circuit outputs a decrypted signal S2, after a short time passes and the driving system and the response system are synchronized, the high-dimensional hyper-chaotic signal Y _2 generated by the response circuit cancels the signal Y1 after encryption, the signal S2 obtained after decryption has a waveform identical to the original signal S before encryption.

The first to the thirty-ninth operational amplifiers all adopt TL085, and the first to the tenth analog multipliers all adopt AD 633.

The working principle of the invention is as follows: firstly, a driving system generates signals due to self-excited oscillation, and synchronization is realized by using a coupling synchronization method. Therefore, two high-dimensional hyperchaotic encrypted signals Y and high-dimensional hyperchaotic decrypted signals Y _2 which are consistent after a short time are obtained from the driving system and the response system. The signal source outputs an effective signal S to be transmitted (note that the voltage amplitude of the effective signal S is required to be smaller than or far smaller than the voltage amplitude of the encrypted signal), the effective signal S is superposed with the encrypted signal Y after passing through the encryption circuit to obtain a signal S1= -S-Y, the signal sender sends a signal S1, when the receiver receives S1, the effective signal S2= -S1-Y _2 is superposed with Y _2 through the decryption circuit to obtain a decrypted signal S2= -S1-Y _2, after a short time, the driving system and the response system are synchronized to obtain Y _2=Y, then S2= S is received, then decryption is achieved, resulting in a valid signal. Wherein, the 220V alternating current of the common household power can be converted into the alternating current of the common household power through the voltage stabilizing rectification circuit

The direct current voltage provides power for the whole circuit, and the practicability of the system is enhanced.

The dimensionless mathematical model of the system related by the invention is as follows:

（1）

in the formula (1), the reaction mixture is,

is a variable of the state of the system,

are system parameters, the values of which are respectively

。

In order to facilitate circuit implementation and oscilloscope display, the above dimensionless mathematical model is modified into the following model:

（2）

the circuit equation of the driving system of the present invention can be obtained according to equation (2):

（3）

combining formula (2) and formula (3) to make the capacitor

The values of all resistances can be found as:

。

Claims

1. a nine-dimensional hyper-chaotic communication encryption circuit is characterized in that: the device comprises a signal source, a power supply, a driving circuit, a response circuit, an encryption circuit and a decryption circuit; the power supply is connected with the driving circuit, the response circuit, the encryption circuit and the decryption circuit to provide stable working voltage for the whole circuit, the signal source is connected with the first input end of the encryption circuit, the second output end of the driving circuit is connected with the second input end of the encryption circuit, the output end of the encryption circuit is connected with the first input end of the decryption circuit, the output end of the response circuit is connected with the second input end of the decryption circuit, the output end of the decryption circuit outputs a decrypted signal, and the output end of the driving circuit is connected with the input end of the response circuit to realize coupling synchronization; the signal source provides a signal S needing to be kept secret for the whole secret communication circuit, the two signals of the high-dimensional hyperchaotic signal Y, the S and the Y are output from the second output end of the driving circuit and are superposed through the encryption circuit to obtain S1= -S-Y, so that the signal S needing to be kept secret is covered by the high-dimensional hyperchaotic signal Y generated by the driving circuit, the encryption circuit outputs an encrypted signal S1 to the first input end of the decryption circuit, the high-dimensional hyperchaotic signal Y _2 output from the response circuit is used for decryption and is input to the second input end of the decryption circuit, the two signals of the S1 and the Y _2 are superposed through the decryption circuit to obtain S2= -S1-Y _2, the output end of the decryption circuit outputs a decrypted signal S2, after the driving system and the response circuit are synchronized, the signal Y _2 generated by the response circuit cancels the signal Y in the encrypted signal S1, the signal S2 obtained after decryption has a waveform identical to the original signal S before encryption.

2. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 1, characterized in that: the driving circuit comprises sixty-first to hundred-second resistors, twenty-first to thirty-eighth operational amplifiers, tenth to eighteenth capacitors and sixth to tenth analog multipliers; a sixty-first resistor, a sixty-second resistor, a sixty-third resistor, a sixty-fourth resistor, a sixty-fifth resistor, a twenty-first operational amplifier and a tenth capacitor form a first inverting addition integrator, a sixty-sixth resistor, a sixty-seventh resistor, a twenty-second operational amplifier form a first inverter, and the first inverting addition integrator and the first inverter form a first dimensional circuit; a sixty-eight resistor, a sixty-nine resistor, a seventy-one resistor, a twenty-third operational amplifier, an eleventh capacitor and a sixth analog multiplier form a second inverting addition integrator, a seventy-two resistor, a seventy-three resistor and a twenty-fourth operational amplifier form a second inverter, and the second inverting addition integrator and the second inverter form a second dimensional circuit; a seventy-fourth resistor, a seventy-fifth resistor, a twenty-fifth operational amplifier, a twelfth capacitor and a seventh analog multiplier form a third inverting addition integrator, a seventy-sixth resistor, a seventy-seventh resistor, a twenty-sixth operational amplifier form a third inverter, and the third inverting addition integrator and the third inverter form a third three-dimensional circuit; a seventy-eight resistor, a seventy-nine resistor, a twenty-seventh operational amplifier, a thirteenth capacitor and an eighth analog multiplier form a fourth inverting addition integrator, an eighty resistor, an eighty-first resistor and a twenty-eighth operational amplifier form a fourth inverter, and the fourth inverting addition integrator and the fourth inverter form a fourth dimensional circuit; the eighty-two resistor, the eighty-three resistor, the eighty-four resistor, the twenty-ninth operational amplifier, the fourteenth capacitor and the ninth analog multiplier form a fifth inverting addition integrator, the eighty-five resistor, the eighty-six resistor and the thirty operational amplifier form a fifth inverter, and the fifth inverting addition integrator and the fifth inverter form a fifth dimensional circuit; the eighty-seventh resistor, the eighty-eighth resistor, the eighty-ninth resistor, the thirty-first operational amplifier and the fifteenth capacitor form a sixth inverting addition integrator, the ninety resistor, the ninety-first resistor and the thirty-second operational amplifier form a sixth inverter, and the sixth inverting addition integrator and the sixth inverter form a sixth-dimensional circuit; the ninety-second resistor, the ninety-third resistor, the thirty-third operational amplifier, the sixteenth capacitor and the tenth analog multiplier form a seventh inverting addition integrator, the ninety-fourth resistor, the ninety-fifth resistor, the thirty-fourth operational amplifier form a seventh inverter, and the seventh inverting addition integrator and the seventh inverter form a seventh dimensional circuit; the ninety-sixth resistor, the ninety-seventh resistor, the thirty-fifth operational amplifier and the seventeenth capacitor form an eighth inverting addition integrator, the ninety-eighth resistor, the ninety-ninth resistor, the thirty-sixth operational amplifier form an eighth inverter, and the eighth inverting addition integrator and the eighth inverter form an eighth-dimensional circuit; the first hundredth resistor, the thirty-seventh operational amplifier and the eighteenth capacitor form a ninth inverting addition integrator, the first hundredth resistor and the thirty-eighth operational amplifier form a ninth inverter, and the ninth inverting addition integrator and the ninth inverter form a ninth dimensional circuit.

3. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 2, characterized in that: in the first-dimensional circuit of the nine-dimensional driving circuit, one end of a sixty-first resistor, one end of a sixty-second resistor, one end of a sixty-third resistor, one end of a sixty-fourth resistor and one end of a sixty-fifth resistor are connected together and connected to the inverting input end of a twenty-first operational amplifier, the other end of the sixty-first resistor is connected with the output end of a thirty-fourth operational amplifier in the seventh-dimensional circuit, the other end of the sixty-second resistor is connected with the output end of a thirty-seventh operational amplifier in the ninth-dimensional circuit, the other end of the sixty-third resistor is connected with the output end of a twenty-eighth operational amplifier in the fourth-dimensional circuit, the other end of the sixty-fourth resistor is connected with the output end of a twenty-fourth operational amplifier in the second-dimensional circuit, the other end of the sixty-fifth resistor is connected with the output end of a twenty-first operational amplifier in the first-dimensional circuit, the tenth capacitor is bridged between the inverting input end and the output end of the twenty-first operational amplifier, the output end of the twenty-first operational amplifier is connected to the inverting input end of the twenty-second operational amplifier after being connected with the sixty-sixth resistor, the non-inverting input end of the twenty-second operational amplifier is grounded, and the sixty-seventh resistor is bridged between the inverting input end and the output end of the twenty-second operational amplifier;

in the ninth-dimensional driving circuit, one end of a sixty-eight resistor, one end of a sixty-nine resistor, one end of a seventy resistor and one end of a seventy-first resistor are connected together and connected to the inverting input end of a twenty-third operational amplifier, the other end of the sixty-eight resistor is connected with the output end of the twenty-ninth operational amplifier in the fifth-dimensional circuit, the other end of the sixty-nine resistor is connected with the output end of the twenty-third operational amplifier in the second-dimensional circuit, the other end of the seventy resistor is connected with the output end of a twenty-second operational amplifier in the first-dimensional circuit, the other end of the seventy-first resistor is connected with the output end of a sixth analog multiplier, the other input end of the sixth analog multiplier is connected with the output end of a twenty-fifth operational amplifier in the third-dimensional circuit, one input end of the sixth analog multiplier is connected with the output end of the twenty-first operational amplifier in the, the non-inverting input end of the twenty-third operational amplifier is grounded, the eleventh capacitor is bridged between the inverting input end and the output end of the twenty-third operational amplifier, the output end of the twenty-third operational amplifier is connected to the inverting input end of the twenty-fourth operational amplifier through the seventy-second resistor, the non-inverting input end of the twenty-fourth operational amplifier is grounded, and the seventy-third resistor is bridged between the inverting input end and the output end of the twenty-fourth operational amplifier;

in the ninth-dimensional driving circuit, one end of a seventy-fourth resistor and one end of a seventy-fifth resistor are connected together and connected to the inverting input end of a twenty-fifth operational amplifier, the other end of the seventy-fourth resistor is connected with the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, the other end of the seventy-fifth resistor is connected with the output end of a seventh analog multiplier, the other input end of the seventh analog multiplier is connected with the output end of a twenty-third operational amplifier in the second-dimensional circuit, one input end of the seventh analog multiplier is connected with the output end of a twenty-second operational amplifier in the first-dimensional circuit, the non-inverting input end of the twenty-fifth operational amplifier is grounded, a twelfth crossover capacitor is arranged between the inverting input end and the output end of the twenty-fifth operational amplifier, the output end of the twenty-fifth operational amplifier is connected to the inverting input end of the twenty-sixth operational amplifier through a seventy-sixth resistor, the non-inverting input end of the twenty-sixth operational amplifier is grounded, and the seventy-seventh resistor is bridged between the inverting input end and the output end of the twenty-sixth operational amplifier;

4. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 3, wherein: in a fifth-dimensional circuit of the nine-dimensional driving circuit, one end of an eighty-two resistor, one end of an eighty-three resistor and one end of an eighty-four resistor are connected together and connected to an inverting input end of a twenty-ninth operational amplifier, the other end of the eighty-two resistor is connected with an output end of a twenty-third operational amplifier in the second-dimensional circuit, the other end of the eighty-three resistor is connected with an output end of a thirtieth operational amplifier in the fifth-dimensional circuit, the other end of the eighty-four resistor is connected with an output end of a ninth analog multiplier, one input end of the ninth analog multiplier is connected with an output end of a twenty-fifth operational amplifier in the third-dimensional circuit, the other input end of the ninth analog multiplier is connected with an output end of a twenty-fourth operational amplifier in the second-dimensional circuit, a non-inverting input end of the twenty-nine operational amplifier is grounded, and a fourteenth bridging capacitor is arranged between the inverting input, the output end of the twenty-ninth operational amplifier is connected to the inverting input end of the thirtieth operational amplifier through an eighty-fifth resistor, the non-inverting input end of the thirtieth operational amplifier is grounded, and an eighty-sixth resistor is bridged between the inverting input end and the output end of the thirtieth operational amplifier;

5. The chaotic-masking-based nine-dimensional hyper-chaotic communication encryption circuit according to claim 4, wherein: in the seventh dimension circuit of the nine-dimension driving circuit, one end of a ninety second resistor and one end of a ninety third resistor are connected together and connected to the inverting input end of a thirty third operational amplifier, the other end of the ninety second resistor is connected with the output end of a thirty third operational amplifier in the seventh dimension circuit, the other end of the ninety third resistor is connected with the output end of a tenth analog multiplier, one input end of the tenth analog multiplier is connected with the output end of a twenty seventh operational amplifier in the fourth dimension circuit, the other input end of the tenth analog multiplier is connected with the output end of a twenty third operational amplifier in the second dimension circuit, the non-inverting input end of the thirty third operational amplifier is grounded, a sixteenth capacitor is connected between the inverting input end and the output end of the thirty third operational amplifier, and the output end of the thirty third operational amplifier is connected with the input end of the thirty fourth operational amplifier through the ninety fourth resistor, the non-inverting input end of the thirty-fourth operational amplifier is grounded, and the ninety-fifth resistor is connected between the inverting input end and the output end of the thirty-fourth operational amplifier in a bridging manner;

in the ninth-dimensional circuit, one end of the ninety-sixth resistor, one end of a ninety-seventh resistor is connected together and connected to the inverting input end of the thirty-fifth operational amplifier, the other end of a ninety-sixth resistor is connected with the output end of a thirty-fifth operational amplifier in the eighth-dimensional circuit, the other end of the ninety-seventh resistor is connected with the output end of a twenty-fourth operational amplifier in the second-dimensional circuit, the non-inverting input end of the thirty-fifth operational amplifier is grounded, a seventeenth capacitor is connected between the inverting input end and the output end of the thirty-fifth operational amplifier in a bridging manner, the output end of the thirty-fifth operational amplifier is connected to the input end of the thirty-sixth operational amplifier through a ninety-eighth resistor, the non-inverting input end of the thirty-eighth operational amplifier is grounded, and a ninety-ninth resistor is connected between the inverting input end and the;

6. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 5, wherein: in the nine-dimensional driving circuit, the output ends of the twenty-second operational amplifier, the twenty-fourth operational amplifier, the twenty-sixth operational amplifier, the twenty-eighth operational amplifier, the thirty-sixth operational amplifier, the thirty-second operational amplifier, the thirty-fourth operational amplifier, the thirty-sixth operational amplifier and the thirty-eighth operational amplifier are led out to be used as the output end of the driving circuit for coupling synchronization, so that the response system and the driving system are synchronized, and the output end of the twenty-third operational amplifier is led out to be used as the other output end of the driving circuit to be used as a high-dimensional signal to cover a signal to be transmitted.

7. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 6, wherein: the response circuit comprises first to sixty resistors, third to twentieth operational amplifiers, first to ninth capacitors and first to fifth analog multipliers, which correspond to sixty-first to one-hundred-second resistors, twenty-first to thirty-eighth operational amplifiers, tenth to eighteenth capacitors and sixth to tenth analog multipliers, and the difference between the connection relationship of the components in the response circuit and the connection relationship of the components in the drive circuit is only that: the response circuit is added with a controller on the basis of the drive circuit, and ensures the coupling coefficient required by the synchronization of the two chaotic systems, so that the drive system and the response system are synchronized.

8. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 7, wherein: the encryption circuit comprises a third-to-zero resistor, a fourth-to-zero resistor, a fifth-to-zero resistor and a first operational amplifier, wherein one end of the third-to-zero resistor is led out to serve as a first input end of the encryption circuit and is used for receiving effective signals to be encrypted, the other end of the third-to-zero resistor is connected with an inverting input end of the first operational amplifier, one end of the fourth-to-zero resistor is led out to serve as a second input end of the encryption circuit and is used for receiving signals output by a second output end of the driving circuit, the other end of the fourth-to-zero resistor is connected with the inverting input end of the first operational amplifier, a non-inverting input end of the first operational amplifier is grounded, the fifth-to-zero resistor is connected between the inverting input end and the output end of the first operational amplifier in a bridging mode, and the output.

9. The nine-dimensional hyper-chaotic communication encryption circuit according to claim 8, wherein: the decryption circuit comprises a first hundred-zero-six resistor, a first hundred-zero-seven resistor, a first hundred-zero-eight resistor and a second operational amplifier, wherein one end of the first hundred-zero-six resistor is led out to serve as a first input end of the decryption circuit and is used for receiving a signal to be decrypted, the other end of the first hundred-zero-six resistor is connected with an inverting input end of the second operational amplifier, one end of the first hundred-zero-seven resistor is led out to serve as a second input end of the decryption circuit and is used for receiving a decryption signal output by the driving system, the other end of the first hundred-zero-seven resistor is connected with an inverting input end of the second operational amplifier, a non-inverting input end of the second operational amplifier is grounded, the first hundred-zero-eight resistor is bridged between the inverting input end and an output end of the second operational amplifier.