CN111698079A - Nine-dimensional hyper-chaotic communication encryption circuit - Google Patents
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Abstract
本发明公开了一种九维超混沌通信加密电路，包括信号源、驱动电路、响应电路、加密电路、解密电路；加密电路为信号源提供的信号进行加密，加密电路的输出端与解密电路的第一输入端相连，解密电路为加密电路加密后的信号进行解密，解密电路的输出端输出解密后信号。驱动电路的第二输出端与加密电路的第二输入端相连，提供高维混沌信号，对需加密的信号进行遮掩，响应电路的第二输出端与解密电路的第二输入端相连，输出高维信号用于解密，驱动电路的输出端与响应电路的输入端相连，实现耦合同步。九维超混沌通信加密电路在当参数变化时，处于混沌状态的参数范围大，具有较大的秘钥空间，因此具有更高的保密安全性，十分适用于信号的保密传输。The invention discloses a nine-dimensional super-chaotic communication encryption circuit, comprising a signal source, a driving circuit, a response circuit, an encryption circuit and a decryption circuit; the encryption circuit encrypts the signal provided by the signal source, and the output end of the encryption circuit is connected with the decryption circuit. The first input end is connected, the decryption circuit decrypts the signal encrypted by the encryption circuit, and the output end of the decryption circuit outputs the decrypted signal. The second output end of the drive circuit is connected with the second input end of the encryption circuit, and provides a high-dimensional chaotic signal to cover the signal to be encrypted. The second output end of the response circuit is connected with the second input end of the decryption circuit, and the output is high. The dimension signal is used for decryption, and the output end of the drive circuit is connected with the input end of the response circuit to realize coupling synchronization. When the parameters of the nine-dimensional hyperchaotic communication encryption circuit change, the parameter range in the chaotic state is large and the key space is large, so it has higher security and is very suitable for the secure transmission of signals.
Description
技术领域technical field
本发明涉及通信领域，特别涉及一种九维超混沌通信加密电路。The invention relates to the field of communication, in particular to a nine-dimensional hyperchaotic communication encryption circuit.
背景技术Background technique
混沌（chaos）是指确定性动力学系统因对初值敏感而表现出的不可预测的、类似随机性的运动。1990年以来，混沌保密通信和混沌加密技术已成为国际电子通信领域的一个热门课题。迄今为止，混沌在保密通信中的应用大致可分为三类：第一类是直接利用混沌进行秘密通信；第二类是利用同步的混沌信号进行秘密通信；第三类是基于混沌序列的数字加密通信。第二类是当前的一大研究热点，已成为高新技术的新领域，并且随着通讯的日益增多，加强通讯保密性已经势在必行。Chaos refers to the unpredictable, random-like motion of a deterministic dynamic system because it is sensitive to initial values. Since 1990, chaotic secure communication and chaotic encryption technology have become a hot topic in the field of international electronic communication. So far, the applications of chaos in secure communication can be roughly divided into three categories: the first category is to use chaos directly for secret communication; the second category is to use synchronized chaotic signals for secret communication; the third category is digital based on chaotic sequences Encrypted communication. The second category is a major research hotspot at present, and has become a new field of high-tech. With the increasing number of communications, it is imperative to strengthen the confidentiality of communications.
混沌系统复杂的动力学行为、对初始条件的敏感性以及动力学行为的长期不可预测，以及其所具有的高容量的动态存储能力、低功率、低观察性、设备成本低廉，使得混沌很适用于保密通信，适合作为保密通信的载体。The complex dynamic behavior, sensitivity to initial conditions, and long-term unpredictability of dynamic behavior of chaotic systems, as well as its high-capacity dynamic storage capacity, low power, low observability, and low equipment cost, make chaos very suitable. For confidential communication, it is suitable as the carrier of confidential communication.
混沌遮掩保密通信由Kocarev和Cuomo等提出，利用一个自治混沌系统作为编码器，在它的混沌输出信号上叠加上信息信号，通过信道发送，解码器利用着用传输的信号来同步另一个等价的混沌系统，这个等价的混沌系统输出一个重构的混沌信号，然后从所传输信号中减去这个重构的混沌信号，来恢复信息信号。另外，混沌系统本身是确定的，由非线性系统的方程、参数和初始条件所完全决定，从而易于产生和复制出数量众多、非相关、类随机而又确定的混沌序列。The chaotic masked secure communication was proposed by Kocarev and Cuomo, etc., using an autonomous chaotic system as an encoder, superimposing an information signal on its chaotic output signal, and sending it through a channel, the decoder uses the transmitted signal to synchronize another equivalent. The chaotic system, the equivalent chaotic system outputs a reconstructed chaotic signal, and then subtracts the reconstructed chaotic signal from the transmitted signal to recover the information signal. In addition, the chaotic system itself is deterministic and completely determined by the equations, parameters and initial conditions of the nonlinear system, so it is easy to generate and reproduce a large number of non-correlated, quasi-random and deterministic chaotic sequences.
低维自治混沌系统的带宽比较窄, 应用在保密通信中效果差, 信号容易被破译。但是高维超混沌系统动力学行为更复杂更难预测，将其应用在保密通信中将大大提高信号传输的保密程度，大大加强了抗攻击性。The bandwidth of the low-dimensional autonomous chaotic system is relatively narrow, and the effect of application in secure communication is poor, and the signal is easy to be deciphered. However, the dynamic behavior of high-dimensional hyperchaotic systems is more complex and difficult to predict, and its application in secure communication will greatly improve the confidentiality of signal transmission and greatly enhance the anti-attack.
发明内容SUMMARY OF THE INVENTION
为了解决上述技术问题，本发明提供一种九维超混沌通信加密电路。In order to solve the above technical problems, the present invention provides a nine-dimensional hyperchaotic communication encryption circuit.
本发明解决上述问题的技术方案是：一种九维超混沌通信加密电路，包括信号源、电源、驱动电路、响应电路、加密电路、解密电路；所述电源与驱动电路、响应电路、加密电路、解密电路相连，为整个电路提供稳定工作电压，信号源与加密电路的第一输入端相连，驱动电路的第二输出端与加密电路的第二输入端相连，加密电路的输出端与解密电路的第一输入端相连，响应电路的输出端与解密电路的第二输入端相连，解密电路的输出端输出解密后信号，驱动电路的输出端与响应电路的输入端相连，实现耦合同步；信号源为整个保密通讯电路提供需要保密的信号S，驱动电路第二输出端中输出高维超混沌信号Y，S和Y两个信号经过加密电路进行叠加得到S1=- S-Y，使得驱动电路产生的高维超混沌信号Y遮掩住需要保密的信号S，加密电路输出加密信号S1至解密电路的第一输入端，从响应电路输出的高维超混沌信号Y_2用于解密，输入至解密电路的第二输入端，S1和Y_2两个信号经过解密电路进行叠加得到S2= -S1- Y_2，解密电路的输出端输出解密后信号S2，驱动系统和响应系统相同步后，响应电路产生的高维超混沌信号Y_2抵消掉加密后信号S1中的信号Y，解密后得到的信号S2与加密前的原始信号S波形一致。The technical scheme of the present invention to solve the above problems is: a nine-dimensional hyperchaotic communication encryption circuit, comprising a signal source, a power supply, a driving circuit, a response circuit, an encryption circuit, and a decryption circuit; the power supply and the driving circuit, the response circuit, and the encryption circuit , the decryption circuit is connected to provide a stable working voltage for the entire circuit, the signal source is connected to the first input end of the encryption circuit, the second output end of the drive circuit is connected to the second input end of the encryption circuit, and the output end of the encryption circuit is connected to the decryption circuit. The output end of the response circuit is connected to the second input end of the decryption circuit, the output end of the decryption circuit outputs the decrypted signal, and the output end of the drive circuit is connected to the input end of the response circuit to realize coupling synchronization; The source provides a signal S that needs to be kept secret for the entire secure communication circuit, and the second output terminal of the drive circuit outputs a high-dimensional hyperchaotic signal Y. The two signals S and Y are superimposed by the encryption circuit to obtain S1=- S-Y, which makes the high-dimensional hyperchaotic signal generated by the drive circuit. The signal Y conceals the signal S that needs to be kept secret, the encryption circuit outputs the encrypted signal S1 to the first input end of the decryption circuit, the high-dimensional hyperchaotic signal Y_2 output from the response circuit is used for decryption, and is input to the second input end of the decryption circuit, S1 and The two signals Y_2 are superimposed by the decryption circuit to obtain S2= -S1- Y_2. The output end of the decryption circuit outputs the decrypted signal S2. After the drive system and the response system are synchronized, the high-dimensional hyperchaotic signal Y_2 generated by the response circuit cancels the encrypted signal. The signal Y in S1 and the signal S2 obtained after decryption are consistent with the original signal S before encryption.
上述九维超混沌通信加密电路中，所述驱动电路包括第六十一至第一百零二电阻、第二十一至第三十八运算放大器、第十至第十八电容、第六至第十模拟乘法器；第六十一电阻、第六十二电阻、第六十三电阻、第六十四电阻、第六十五电阻与第二十一运算放大器、第十电容构成第一反相加法积分器，第六十六电阻、第六十七电阻与第二十二运算放大器构成第一反相器，第一反相加法积分器和第一反相器构成第一维电路；第六十八电阻、第六十九电阻、第七十电阻、第七十一电阻与第二十三运算放大器、第十一电容、第六模拟乘法器构成第二反相加法积分器，第七十二电阻、第七十三电阻与第二十四运算放大器构成第二反相器，第二反相加法积分器和第二反相器构成第二维电路；第七十四电阻、第七十五电阻与第二十五运算放大器、第十二电容、第七模拟乘法器构成第三反相加法积分器，第七十六电阻、第七十七电阻与第二十六运算放大器构成第三反相器，第三反相加法积分器和第三反相器构成第三维电路；第七十八电阻、第七十九电阻与第二十七运算放大器、第十三电容、第八模拟乘法器构成第四反相加法积分器，第八十电阻、第八十一电阻与第二十八运算放大器构成第四反相器，第四反相加法积分器和第四反相器构成第四维电路；第八十二电阻、第八十三电阻、第八十四电阻与第二十九运算放大器、第十四电容、第九模拟乘法器构成第五反相加法积分器，第八十五电阻、第八十六电阻与第三十运算放大器构成第五反相器，第五反相加法积分器和第五反相器构成第五维电路；第八十七电阻、第八十八电阻、第八十九电阻与第三十一运算放大器、第十五电容构成第六反相加法积分器，第九十电阻、第九十一电阻与第三十二运算放大器构成第六反相器，第六反相加法积分器和第六反相器构成第六维电路；第九十二电阻、第九十三电阻与第三十三运算放大器、第十六电容、第十模拟乘法器构成第七反相加法积分器，第九十四电阻、第九十五电阻与第三十四运算放大器构成第七反相器，第七反相加法积分器和第七反相器构成第七维电路；第九十六电阻、第九十七电阻与第三十五运算放大器、第十七电容构成第八反相加法积分器，第九十八电阻、第九十九电阻与第三十六运算放大器构成第八反相器，第八反相加法积分器和第八反相器构成第八维电路；第一百电阻与第三十七运算放大器、第十八电容构成第九反相加法积分器，第一百零一电阻、第一百零二电阻与第三十八运算放大器构成第九反相器，第九反相加法积分器和第九反相器构成第九维电路。In the above-mentioned nine-dimensional hyperchaotic communication encryption circuit, the drive circuit includes the sixty-first to one-hundred-second resistors, the twenty-first to thirty-eighth operational amplifiers, the tenth to eighteenth capacitors, and the sixth to the eighteenth capacitors. The tenth analog multiplier; the sixty-first resistor, the sixty-second resistor, the sixty-third resistor, the sixty-fourth resistor, the sixty-fifth resistor, the twenty-first operational amplifier, and the tenth capacitor form the first inverse The adding integrator, the sixty-sixth resistor, the sixty-seventh resistor and the twenty-second operational amplifier form a first inverter, and the first inverting adding integrator and the first inverter form a first-dimensional circuit; The sixty-eighth resistor, the sixty-ninth resistor, the seventieth resistor, the seventy-first resistor, the twenty-third operational amplifier, the eleventh capacitor, and the sixth analog multiplier constitute the second inverting addition integrator, and the seventh The 12th resistor, the 73rd resistor and the 24th operational amplifier form the second inverter, the second inverting addition integrator and the second inverter form the second dimension circuit; the 74th resistor, the 7th The fifteenth resistor, the twenty-fifth operational amplifier, the twelfth capacitor, and the seventh analog multiplier constitute the third inverting adding integrator, and the seventy-sixth resistor, the seventy-seventh resistor and the twenty-sixth operational amplifier constitute the first integrator. The three inverters, the third inverting adding integrator and the third inverter form a third-dimensional circuit; the seventy-eighth resistor, the seventy-ninth resistor and the twenty-seventh operational amplifier, the thirteenth capacitor, and the eighth analog The multiplier constitutes the fourth inverting adding integrator, the eightieth resistor, the eighty-first resistor and the twenty-eighth operational amplifier constitute the fourth inverter, and the fourth inverting adding integrator and the fourth inverter constitute the fourth inverter. Four-dimensional circuit; the eighty-second resistor, the eighty-third resistor, the eighty-fourth resistor and the twenty-ninth operational amplifier, the fourteenth capacitor, and the ninth analog multiplier constitute the fifth inverting addition integrator, and the eighth The 15th resistor, the 86th resistor and the 30th operational amplifier constitute the fifth inverter, the fifth inverting adding integrator and the fifth inverter constitute the fifth dimensional circuit; the 87th resistor, the 80th resistor The eighth resistor, the eighty-ninth resistor, the thirty-first operational amplifier and the fifteenth capacitor constitute the sixth inverting adding integrator, and the ninth resistor, the ninety-first resistor and the thirty-second operational amplifier constitute the sixth inverting Inverter, sixth inverting addition integrator and sixth inverter form the sixth dimension circuit; the 92nd resistor, the 93rd resistor and the 33rd operational amplifier, the 16th capacitor and the 10th analog multiplication The ninth-fourth resistor, the ninety-fifth resistor and the thirty-fourth operational amplifier form the seventh inverter, the seventh inverting adding integrator and the seventh inverter form the seventh inverter. Seven-dimensional circuit; the ninety-sixth resistor, the ninety-seventh resistor, the thirty-fifth operational amplifier, and the seventeenth capacitor constitute the eighth inverting adding integrator, the ninety-eighth resistor, the ninety-ninth resistor and the third The sixteenth operational amplifier constitutes the eighth inverter, the eighth inverting addition integrator and the eighth inverter constitute the eighth-dimensional circuit; the hundredth resistor, the thirty-seventh operational amplifier and the eighteenth capacitor constitute the ninth inverter The addition integrator, the 101st resistor, the 102nd resistor and the 38th operational amplifier form the ninth inverter, and the ninth inverting addition integrator and the ninth inverter form the ninth inverter dimensional circuit.
上述九维驱动电路第一维电路中，第六十一电阻的一端、第六十二电阻的一端、第六十三电阻的一端、第六十四电阻的一端、第六十五电阻的一端连接在一起并接至第二十一运算放大器的反相输入端，第六十一电阻的另一端连接第七维电路中的第三十四运算放大器的输出端，第六十二电阻的另一端连接第九维电路中的第三十七运算放大器的输出端，第六十三电阻的另一端连接第四维电路中的第二十八运算放大器的输出端，第六十四电阻的另一端连接第二维电路中的第二十四运算放大器的输出端，第六十五电阻的另一端连接第一维电路中的第二十一运算放大器的输出端，第二十一运算放大器的同相输入端接地，所述第十电容跨接在第二十一运算放大器的反相输入端与输出端之间，第二十一运算放大器的输出端接第六十六电阻后接至第二十二运算放大器的反相输入端，第二十二运算放大器的同相输入端接地，所述第六十七电阻跨接在第二十二运算放大器的反相输入端与输出端之间。In the first-dimensional circuit of the nine-dimensional drive circuit, one end of the sixty-first resistor, one end of the sixty-second resistor, one end of the sixty-third resistor, one end of the sixty-fourth resistor, and one end of the sixty-fifth resistor Connected together and connected to the inverting input terminal of the twenty-first operational amplifier, the other end of the sixty-first resistor is connected to the output terminal of the thirty-fourth operational amplifier in the seventh-dimensional circuit, and the other end of the sixty-second resistor is connected. One end is connected to the output end of the thirty-seventh operational amplifier in the ninth dimension circuit, the other end of the sixty-third resistor is connected to the output end of the twenty-eighth operational amplifier in the fourth dimension circuit, and the other end of the sixty-fourth resistor is connected to the output end of the twenty-eighth operational amplifier in the fourth dimension circuit. One end is connected to the output end of the twenty-fourth operational amplifier in the second-dimensional circuit, the other end of the sixty-fifth resistor is connected to the output end of the twenty-first operational amplifier in the first-dimensional circuit, and the The non-inverting input terminal is grounded, the tenth capacitor is connected across the inverting input terminal and the output terminal of the twenty-first operational amplifier, and the output terminal of the twenty-first operational amplifier is connected to the sixty-sixth resistor and then connected to the second The inverting input terminal of the twelve operational amplifiers, the non-inverting input terminal of the twenty-second operational amplifier is grounded, and the sixty-seventh resistor is connected across the inverting input terminal and the output terminal of the twenty-second operational amplifier.
所述九维驱动电路第二维电路中，第六十八电阻的一端、第六十九电阻的一端、第七十电阻、第七十一电阻的一端连接在一起并接至第二十三运算放大器的反相输入端，第六十八电阻的另一端与第五维电路中的第二十九运算放大器的输出端相连，第六十九电阻的另一端连接第二维电路中的第二十三运算放大器的输出端，第七十电阻的另一端连接第一维电路中的第二十二运算放大器的输出端，第七十一电阻的另一端与第六模拟乘法器的输出端相连，第六模拟乘法器的另一个输入端连接第三维电路中的第二十五运算放大器的输出端，第六模拟乘法器的其中一个输入端与第一维电路中第二十一运算放大器的输出端相连，所述第二十三运算放大器的同相输入端接地，第十一电容跨接在第二十三运算放大器的反相输入端与输出端之间，第二十三运算放大器的输出端经第七十二电阻后接至第二十四运算放大器的反相输入端，第二十四运算放大器的同相输入端接地，第七十三电阻跨接在第二十四运算放大器的反相输入端与输出端之间。In the second-dimensional circuit of the nine-dimensional drive circuit, one end of the sixty-eighth resistor, one end of the sixty-ninth resistor, one end of the seventieth resistor, and one end of the seventy-first resistor are connected together and connected to the twenty-third The inverting input terminal of the operational amplifier, the other end of the sixty-eighth resistor is connected to the output terminal of the twenty-ninth operational amplifier in the fifth-dimensional circuit, and the other end of the sixty-ninth resistor is connected to the second-dimensional circuit. The output terminal of the twenty-third operational amplifier, the other end of the seventieth resistor is connected to the output terminal of the twenty-second operational amplifier in the first-dimensional circuit, and the other end of the seventy-first resistor is connected to the output terminal of the sixth analog multiplier connected, the other input terminal of the sixth analog multiplier is connected to the output terminal of the twenty-fifth operational amplifier in the third-dimensional circuit, and one of the input terminals of the sixth analog multiplier is connected to the twenty-first operational amplifier in the first-dimensional circuit. The non-inverting input terminal of the twenty-third operational amplifier is connected to the ground, the eleventh capacitor is connected across the inverting input terminal and the output terminal of the twenty-third operational amplifier, and the The output terminal is connected to the inverting input terminal of the twenty-fourth operational amplifier through the seventy-second resistor, the non-inverting input terminal of the twenty-fourth operational amplifier is grounded, and the seventy-third resistor is connected across the twenty-fourth operational amplifier. between the inverting input and the output.
所述九维驱动电路第三维电路中，第七十四电阻的一端、第七十五电阻的一端连接在一起并接至第二十五运算放大器的反相输入端，第七十四电阻的另一端与第三维电路中的第二十五运算放大器的输出端相连，第七十五电阻的另一端与第七模拟乘法器的输出端相连，第七模拟乘法器的另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第七模拟乘法器的其中一个输入端与第一维电路中的第二十二运算放大器的输出端相连，所述第二十五运算放大器的同相输入端接地，第十二电容跨接在第二十五运算放大器的反相输入端与输出端之间，第二十五运算放大器的输出端经第七十六电阻后接至第二十六运算放大器的反相输入端，第二十六运算放大器的同相输入端接地，第七十七电阻跨接在第二十六运算放大器的反相输入端与输出端之间。In the third-dimensional circuit of the nine-dimensional drive circuit, one end of the seventy-fourth resistor and one end of the seventy-fifth resistor are connected together and connected to the inverting input terminal of the twenty-fifth operational amplifier, and one end of the seventy-fourth resistor is connected to the inverting input of the twenty-fifth operational amplifier. The other end is connected to the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, the other end of the seventy-fifth resistor is connected to the output end of the seventh analog multiplier, and the other input end of the seventh analog multiplier is connected to the seventh analog multiplier. The output terminal of the twenty-third operational amplifier in the two-dimensional circuit is connected, and one of the input terminals of the seventh analog multiplier is connected to the output terminal of the twenty-second operational amplifier in the first-dimensional circuit. The non-inverting input terminal of the operational amplifier is grounded, the twelfth capacitor is connected between the inverting input terminal and the output terminal of the twenty-fifth operational amplifier, and the output terminal of the twenty-fifth operational amplifier is connected to the seventy-sixth resistor. The inverting input terminal of the twenty-sixth operational amplifier, the non-inverting input terminal of the twenty-sixth operational amplifier is grounded, and the seventy-seventh resistor is connected across the inverting input terminal and the output terminal of the twenty-sixth operational amplifier.
所述九维驱动电路第四维电路中，第七十八电阻的一端、第七十九电阻的一端连接在一起并接至第二十七运算放大器的反相输入端，第七十八电阻的另一端与第四维电路中的第二十七运算放大器的输出端连接，第七十九电阻的另一端与第八模拟乘法器的输出端连接，第八模拟乘法器的一个输入端与第三维电路中的第二十五运算放大器的输出端相连，第八模拟乘法器的其中另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第二十七运算放大器的同相输入端接地，第十三电容跨接在第二十七运算放大器的反相输入端与输出端之间，第二十七运算放大器的输出端经第八十电阻后接至第二十八运算放大器的反相输入端，第二十八运算放大器的同相输入端接地，第八十一电阻跨接在第二十八运算放大器的反相输入端与输出端之间。In the fourth-dimensional circuit of the nine-dimensional drive circuit, one end of the seventy-eighth resistor and one end of the seventy-ninth resistor are connected together and connected to the inverting input terminal of the twenty-seventh operational amplifier, and the seventy-eighth resistor The other end is connected to the output end of the twenty-seventh operational amplifier in the fourth-dimensional circuit, the other end of the seventy-ninth resistor is connected to the output end of the eighth analog multiplier, and one input end of the eighth analog multiplier is connected to the output end of the eighth analog multiplier. The output terminal of the twenty-fifth operational amplifier in the third-dimensional circuit is connected, the other input terminal of the eighth analog multiplier is connected to the output terminal of the twenty-third operational amplifier in the second-dimensional circuit, and the twenty-seventh operational amplifier The non-inverting input terminal of the amplifier is grounded, the thirteenth capacitor is connected between the inverting input terminal and the output terminal of the twenty-seventh operational amplifier, and the output terminal of the twenty-seventh operational amplifier is connected to the second The inverting input terminal of the eighteenth operational amplifier, the non-inverting input terminal of the twenty-eighth operational amplifier are grounded, and the eighty-first resistor is connected across the inverting input terminal and the output terminal of the twenty-eighth operational amplifier.
所述九维驱动电路第五维电路中，第八十二电阻的一端、第八十三电阻、第八十四电阻的一端连接在一起并接至第二十九运算放大器的反相输入端，第八十二电阻的另一端连接第二维电路中的第二十三运算放大器的输出端，第八十三电阻的另一端连接第五维电路中的第三十运算放大器的输出端，第八十四电阻的另一端与第九模拟乘法器的输出端相连，第九模拟乘法器的一个输入端与第三维电路中的第二十五运算放大器的输出端连接，第九模拟乘法器的其中另一个输入端与第二维电路中的第二十四运算放大器的输出端连接，第二十九运算放大器的同相输入端接地，第十四电容跨接在第二十九运算放大器的反相输入端与输出端之间，第二十九运算放大器的输出端经第八十五电阻连接到第三十运算放大器的反相输入端，第三十运算放大器的同相输入端接地，第八十六电阻跨接在第三十运算放大器的反相输入端与输出端之间；In the fifth-dimensional circuit of the nine-dimensional drive circuit, one end of the eighty-second resistor, one end of the eighty-third resistor, and one end of the eighty-fourth resistor are connected together and connected to the inverting input terminal of the twenty-ninth operational amplifier , the other end of the eighty-second resistor is connected to the output end of the twenty-third operational amplifier in the second-dimensional circuit, and the other end of the eighty-third resistor is connected to the output end of the thirtieth operational amplifier in the fifth-dimensional circuit, The other end of the eighty-fourth resistor is connected to the output end of the ninth analog multiplier, and one input end of the ninth analog multiplier is connected to the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, and the ninth analog multiplier is One of the other input terminals is connected to the output terminal of the twenty-fourth operational amplifier in the second-dimensional circuit, the non-inverting input terminal of the twenty-ninth operational amplifier is grounded, and the fourteenth capacitor is connected across the twenty-ninth operational amplifier. Between the inverting input terminal and the output terminal, the output terminal of the twenty-ninth operational amplifier is connected to the inverting input terminal of the thirtieth operational amplifier through the eighty-fifth resistor, the non-inverting input terminal of the thirtieth operational amplifier is grounded, and the The eighty-six resistors are connected across the inverting input terminal and the output terminal of the thirtieth operational amplifier;
所述九维驱动电路第六维电路中，第八十七电阻的一端、第八十八电阻、第八十九电阻的一端连接在一起并接至第三十一运算放大器的反相输入端，第八十七电阻的另一端连接第五维电路中的第二十九运算放大器的输出端，第八十八电阻的另一端连接第四维电路中的第二十八运算放大器的输出端，第八十九电阻的另一端连接第六维电路中的第三十一运算放大器的输出端，第三十一运算放大器的同相输入端接地，第十五电容跨接在第三十一运算放大器的反相输入端与输出端之间，第三十一运算放大器的输出端经第九十电阻连接到第三十二运算放大器的反相输入端，第三十二运算放大器的同相输入端接地，第九十一电阻跨接在第三十二运算放大器的反相输入端与输出端之间。In the sixth-dimensional circuit of the nine-dimensional driving circuit, one end of the eighty-seventh resistor, one end of the eighty-eighth resistor, and one end of the eighty-ninth resistor are connected together and connected to the inverting input end of the thirty-first operational amplifier , the other end of the eighty-seventh resistor is connected to the output of the twenty-ninth operational amplifier in the fifth-dimensional circuit, and the other end of the eighty-eighth resistor is connected to the output of the twenty-eighth operational amplifier in the fourth-dimensional circuit , the other end of the eighty-ninth resistor is connected to the output terminal of the thirty-first operational amplifier in the sixth-dimensional circuit, the non-inverting input terminal of the thirty-first operational amplifier is grounded, and the fifteenth capacitor is connected across the thirty-first operational amplifier Between the inverting input terminal and the output terminal of the amplifier, the output terminal of the thirty-first operational amplifier is connected to the inverting input terminal of the thirty-second operational amplifier through the ninetieth resistor, and the non-inverting input terminal of the thirty-second operational amplifier Ground, the ninety-first resistor is connected across the inverting input terminal and the output terminal of the thirty-second operational amplifier.
所述九维驱动电路第七维电路中，第九十二电阻的一端、第九十三电阻的一端连接在一起并接至第三十三运算放大器的反相输入端，第九十二电阻的另一端连接第七维电路中的第三十三运算放大器的输出端，第九十三电阻的另一端与第十模拟乘法器的输出端相连，第十模拟乘法器的一个输入端与第四维电路中的第二十七运算放大器的输出端连接，第十模拟乘法器的其中另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第三十三运算放大器的同相输入端接地，第十六电容跨接在第三十三运算放大器的反相输入端与输出端之间，第三十三运算放大器的输出端经第九十四电阻连接到第三十四运算放大器的输入端，第三十四运算放大器的同相输入端接地，第九十五电阻跨接在第三十四运算放大器的反相输入端与输出端之间。In the seventh-dimensional circuit of the nine-dimensional drive circuit, one end of the ninety-second resistor and one end of the ninety-third resistor are connected together and connected to the inverting input of the thirty-third operational amplifier, and the ninety-second resistor is connected to the inverting input terminal of the thirty-third operational amplifier. The other end of the resistor is connected to the output end of the thirty-third operational amplifier in the seventh-dimensional circuit, the other end of the ninety-third resistor is connected to the output end of the tenth analog multiplier, and one input end of the tenth analog multiplier is connected to the output end of the tenth analog multiplier. The output terminal of the twenty-seventh operational amplifier in the four-dimensional circuit is connected, and the other input terminal of the tenth analog multiplier is connected to the output terminal of the twenty-third operational amplifier in the second-dimensional circuit. The non-inverting input terminal of the amplifier is grounded, the sixteenth capacitor is connected between the inverting input terminal and the output terminal of the thirty-third operational amplifier, and the output terminal of the thirty-third operational amplifier is connected to the third operational amplifier through the ninety-fourth resistor. The input terminal of the fourteenth operational amplifier, the non-inverting input terminal of the thirty-fourth operational amplifier is grounded, and the ninety-fifth resistor is connected across the inverting input terminal and the output terminal of the thirty-fourth operational amplifier.
所述九维驱动电路第八维电路中，第九十六电阻的一端、第九十七电阻的一端连接在一起并接至第三十五运算放大器的反相输入端，第九十六电阻的另一端连接第八维电路中的第三十五运算放大器的输出端，第九十七电阻的另一端与第二维电路中的第二十四运算放大器的输出端连接，第三十五运算放大器的同相输入端接地，第十七电容跨接在第三十五运算放大器的反相输入端与输出端之间，第三十五运算放大器的输出端经第九十八电阻连接到第三十六运算放大器的输入端，第三十八运算放大器的同相输入端接地，第九十九电阻跨接在第三十六运算放大器的反相输入端与输出端之间。In the eighth-dimensional circuit of the nine-dimensional drive circuit, one end of the ninety-sixth resistor and one end of the ninety-seventh resistor are connected together and connected to the inverting input of the thirty-fifth operational amplifier, and the ninety-sixth resistor The other end of the resistor is connected to the output of the thirty-fifth operational amplifier in the eighth-dimensional circuit, the other end of the ninety-seventh resistor is connected to the output of the twenty-fourth operational amplifier in the second-dimensional circuit, and the thirty-fifth The non-inverting input terminal of the operational amplifier is grounded, the seventeenth capacitor is connected between the inverting input terminal and the output terminal of the thirty-fifth operational amplifier, and the output terminal of the thirty-fifth operational amplifier is connected to the sixth operational amplifier through the ninety-eighth resistor. The input terminal of the thirty-sixth operational amplifier, the non-inverting input terminal of the thirty-eighth operational amplifier are grounded, and the ninety-ninth resistor is connected across the inverting input terminal and the output terminal of the thirty-sixth operational amplifier.
所述九维驱动电路第九维电路中，第一百电阻的一端连接第三十七运算放大器的反相输入端，第一百电阻的另一端与第一维电路中的第二十二运算放大器的输出端相连，第三十七运算放大器的同相输入端接地，第十八电容跨接在第三十七运算放大器的反相输入端与输出端之间，第三十七运算放大器的输出端经第一百零一电阻连接到第三十八运算放大器的输入端，第三十八运算放大器的同相输入端接地，第一百零二电阻跨接在第三十八运算放大器的反相输入端与输出端之间。In the ninth-dimensional circuit of the nine-dimensional drive circuit, one end of the one hundredth resistor is connected to the inverting input terminal of the thirty-seventh operational amplifier, and the other end of the one hundredth resistor is connected to the twenty-second operational amplifier in the first-dimensional circuit. The output terminal of the amplifier is connected, the non-inverting input terminal of the thirty-seventh operational amplifier is grounded, the eighteenth capacitor is connected across the inverting input terminal and the output terminal of the thirty-seventh operational amplifier, and the output of the thirty-seventh operational amplifier is connected to the ground. The terminal is connected to the input terminal of the thirty-eighth operational amplifier through the 101st resistor, the non-inverting input terminal of the 38th operational amplifier is grounded, and the 102nd resistor is connected across the inverting phase of the 38th operational amplifier. between the input and output.
上述的九维超混沌通信加密电路，所述九维驱动电路中，第二十二运算放大器、第二十四运算放大器、第二十六运算放大器、第二十八运算放大器、第三十运算放大器、第三十二运算放大器、第三十四运算放大器、第三十六运算放大器、第三十八运算放大器的输出端引出作为驱动电路的输出端，用于耦合同步，使得响应系统与驱动系统实现同步，第二十三运算放大器的输出端引出并作为驱动电路的另一个输出端，作为高维信号来遮掩需要传递的信号。The above-mentioned nine-dimensional hyperchaotic communication encryption circuit, in the nine-dimensional drive circuit, the twenty-second operational amplifier, the twenty-fourth operational amplifier, the twenty-sixth operational amplifier, the twenty-eighth operational amplifier, and the thirtieth operational amplifier The output terminals of the amplifier, the thirty-second operational amplifier, the thirty-fourth operational amplifier, the thirty-sixth operational amplifier, and the thirty-eighth operational amplifier are drawn out as the output terminal of the driving circuit for coupling synchronization, so that the response system and the driving The system realizes synchronization, and the output end of the twenty-third operational amplifier is drawn out and used as another output end of the drive circuit, which is used as a high-dimensional signal to mask the signal to be transmitted.
上述的九维超混沌通信加密电路，所述响应电路包括与第六十一至第一百零二电阻、第二十一至第三十八运算放大器、第十至第十八电容、第六至第十模拟乘法器一一相对应的第一至第六十电阻、第三至第二十运算放大器、第一至第九电容、第一至第五模拟乘法器，且响应电路中各元器件之间的连接关系与驱动电路中各元器件之间的连接关系的区别仅在于：响应电路在驱动电路的基础上加上了一个控制器，并确保两个混沌系统同步所需要的耦合系数，使驱动系统与响应系统同步。The above-mentioned nine-dimensional hyper-chaotic communication encryption circuit, the response circuit includes the sixty-first to one-hundred-second resistors, the twenty-first to thirty-eighth operational amplifiers, the tenth to eighteenth capacitors, the sixth The first to sixtieth resistors, the third to twentieth operational amplifiers, the first to ninth capacitors, and the first to fifth analog multipliers correspond to the tenth analog multipliers one by one, and each element in the response circuit The only difference between the connection relationship between the devices and the connection relationship between the components in the drive circuit is that the response circuit adds a controller to the drive circuit and ensures the coupling coefficient required for the synchronization of the two chaotic systems. , to synchronize the drive system with the response system.
所述加密电路包括第一百零三电阻、第一百零四电阻、第一百零五电阻、第一运算放大器，第一百零三电阻的一端引出作为加密电路的第一输入端，用来接收需要加密的有效信号，第一百零三电阻的另一端与第一运算放大器的反相输入端连接，第一百零四电阻的一端引出作为加密电路的第二输入端，用来接收驱动电路的第二输出端输出的信号，第一百零四电阻的另一端与第一运算放大器的反相输入端连接，第一运算放大器的同相输入端接地，第一百零五电阻跨接在第一运算放大器的反相输入端与输出端之间，第一运算放大器的输出端作为加密电路的输出端。The encryption circuit includes the one-hundred-third resistor, the one-hundred-fourth resistor, the one-hundred-fifth resistor, and the first operational amplifier. To receive the valid signal that needs to be encrypted, the other end of the 103rd resistor is connected to the inverting input end of the first operational amplifier, and one end of the 104th resistor is drawn out as the second input end of the encryption circuit for receiving For the signal output by the second output end of the drive circuit, the other end of the one hundred and fourth resistor is connected to the inverting input end of the first operational amplifier, the non-inverting input end of the first operational amplifier is grounded, and the one hundred and fifth resistor is connected across Between the inverting input terminal and the output terminal of the first operational amplifier, the output terminal of the first operational amplifier serves as the output terminal of the encryption circuit.
所述解密电路包括第一百零六电阻、第一百零七电阻、第一百零八电阻、第二运算放大器，第一百零六电阻的一端引出作为解密电路的第一输入端，用来接收待解密的信号，第一百零六电阻的另一端与第二运算放大器的反相输入端连接，第一百零七电阻的一端引出作为解密电路的第二输入端，用来接收驱动系统中输出的解密信号，第一百零七电阻的另一端与第二运算放大器的反相输入端连接，第二运算放大器的同相输入端接地，第一百零八电阻跨接在第二运算放大器的反相输入端与输出端之间，第二运算放大器的输出端作为解密电路的输出端。The decryption circuit includes the 106th resistor, the 107th resistor, the 108th resistor, and the second operational amplifier. To receive the signal to be decrypted, the other end of the 106th resistor is connected to the inverting input end of the second operational amplifier, and one end of the 107th resistor is drawn out as the second input end of the decryption circuit to receive the drive For the decryption signal output from the system, the other end of the 107th resistor is connected to the inverting input end of the second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, and the 108th resistor is connected across the second operational amplifier. Between the inverting input terminal and the output terminal of the amplifier, the output terminal of the second operational amplifier serves as the output terminal of the decryption circuit.
本发明的有益效果在于：本发明的信号源为需要传递的有效信息，为整个保密通讯电路提供需要保密的信号S，驱动电路第二输出端中输出高维超混沌信号Y，S和Y两个信号经过加密电路进行叠加得到S1=- S-Y，使得驱动电路产生的高维超混沌信号Y遮掩住需要保密的信号S，加密电路输出加密信号S1至解密电路的第一输入端，从响应电路输出的高维超混沌信号Y_2用于解密，输入至解密电路的第二输入端，S1和Y_2两个信号经过解密电路进行叠加得到S2= -S1- Y_2，解密电路的输出端输出解密后信号S2，驱动系统和响应系统相同步后，响应电路产生的高维超混沌信号Y_2抵消掉加密后信号S1中的信号Y，解密后得到的信号S2与加密前的原始信号S波形一致。本发明是高维超混沌保密通信电路，在当参数变化时，处于混沌状态的参数范围大，具有较大的秘钥空间。九维超混沌通信加密电路具有复杂的动力学性质，其参数带来误差的敏感性更大，辨识、估计或预测所造成的误差的发散速率越快，具有不同方向上的指数分离和拉伸折叠变换，且其具有局部混乱的结构，因此具有很好的保密安全性，十分适用于信号的保密传输。The beneficial effects of the present invention are as follows: the signal source of the present invention is the effective information that needs to be transmitted, and provides the signal S that needs to be kept confidential for the entire secure communication circuit, and the second output end of the drive circuit outputs a high-dimensional hyperchaotic signal Y, two signals of S and Y After the encryption circuit is superimposed to obtain S1=- S-Y, the high-dimensional hyperchaotic signal Y generated by the driving circuit can cover the signal S that needs to be kept secret. The encryption circuit outputs the encrypted signal S1 to the first input of the decryption circuit, and the high-dimensional hyperchaotic output from the response circuit The signal Y_2 is used for decryption and is input to the second input terminal of the decryption circuit. The two signals S1 and Y_2 are superimposed by the decryption circuit to obtain S2=-S1- Y_2. The output terminal of the decryption circuit outputs the decrypted signal S2, which drives the system and responds After the system is synchronized, the high-dimensional hyperchaotic signal Y_2 generated by the response circuit cancels the signal Y in the encrypted signal S1, and the signal S2 obtained after decryption is consistent with the original signal S before encryption. The invention is a high-dimensional super-chaotic secret communication circuit, when the parameters change, the parameter range in the chaotic state is large, and the secret key space is large. The nine-dimensional hyperchaotic communication encryption circuit has complex dynamic properties, its parameters are more sensitive to errors, and the faster the divergence rate of errors caused by identification, estimation or prediction, it has exponential separation and stretching in different directions. Folding transformation, and it has a partially chaotic structure, so it has good security and security, and is very suitable for the secure transmission of signals.
附图说明Description of drawings
图1为本发明的结构框图。FIG. 1 is a structural block diagram of the present invention.
图2为图1中驱动电路的电路图。FIG. 2 is a circuit diagram of the driving circuit in FIG. 1 .
图3为图1中响应电路的电路图。FIG. 3 is a circuit diagram of the response circuit in FIG. 1 .
图4为图1中加密电路的电路图。FIG. 4 is a circuit diagram of the encryption circuit in FIG. 1 .
图5为图1中解密电路的电路图。FIG. 5 is a circuit diagram of the decryption circuit in FIG. 1 .
具体实施方式Detailed ways
下面结合附图和实施例对本发明作进一步的说明。The present invention will be further described below with reference to the accompanying drawings and embodiments.
如图1所示，一种九维超混沌通信加密电路，包括信号源、电源、驱动电路、响应电路、加密电路、解密电路。加密电路由运算放大器和电阻组成的加法电路构成。所述电源与驱动电路、响应电路、加密电路、解密电路相连，为整个电路提供稳定工作电源，信号源为需要加密的信号，与加密电路的第一输入端相连，驱动电路的输出端与响应电路的输入端相连，驱动电路的第二输出端与加密电路的第二输入端相连，响应电路的第二输出端与解密电路的第二输入端相连，加密电路的输出端与解密电路的第一输入端相连，加密电路的输出端输出加密后信号，解密电路的输出端输出解密后信号。As shown in Figure 1, a nine-dimensional hyperchaotic communication encryption circuit includes a signal source, a power supply, a drive circuit, a response circuit, an encryption circuit, and a decryption circuit. The encryption circuit consists of an addition circuit composed of an operational amplifier and a resistor. The power supply is connected with the drive circuit, the response circuit, the encryption circuit and the decryption circuit, and provides a stable working power supply for the whole circuit. The signal source is the signal that needs to be encrypted, and is connected with the first input end of the encryption circuit. The input end of the circuit is connected, the second output end of the drive circuit is connected to the second input end of the encryption circuit, the second output end of the response circuit is connected to the second input end of the decryption circuit, and the output end of the encryption circuit is connected to the second input end of the decryption circuit. An input end is connected, the output end of the encryption circuit outputs the encrypted signal, and the output end of the decryption circuit outputs the decrypted signal.
如图2所示，所述驱动电路包括第二十一运算放大器U21、第二十二运算放大器U22、第二十三运算放大器U23、第二十四运算放大器U24、第二十五运算放大器U25、第二十六运算放大器U26、第二十七运算放大器U27、第二十八运算放大器U28、第二十九运算放大器U29、第三十运算放大器U30、第三十一运算放大器U31、第三十二运算放大器U32、第三十三运算放大器U33、第三十四运算放大器U34、第三十五运算放大器U35、第三十六运算放大器U36、第三十七运算放大器U37、第三十八运算放大器U38、第六十一电阻R61、第六十二电阻R62、第六十三电阻R63、第六十四电阻R64、第六十五电阻R65、第六十六电阻R66、第六十七电阻R67、第六十八电阻R68、第六十九电阻R69、第七十电阻R70、第七十一电阻R71、第七十二电阻R72、第七十三电阻R73、第七十四电阻R74、第七十五电阻R75、第七十六电阻R76、第七十七电阻R77、第七十八电阻R78、第七十九电阻R79、第八十电阻R80、第八十一电阻R81、第八十二电阻R82、第八十三电阻R83、第八十四电阻R84、第八十五电阻R85、第八十六电阻R86、第八十七电阻R87、第八十八电阻R88、第八十九电阻R89、第九十电阻R90、第九十一电阻R91、第九十二电阻R92、第九十三电阻R93、第九十四电阻R94、第九十五电阻R95、第九十六电阻R96、第九十七电阻R97、第九十八电阻R98、第九十九电阻R99、第一百电阻R100、第一百零一电阻R101、第一百零二电阻R102、第十电容C10、第十一电容C11、第十二电容C12、第十三电容C13、第十四电容C14、第十五电容C15、第十六电容C16、第十七电容C17、第十八电容C18、第六模拟乘法器A6、第七模拟乘法器A7、第八模拟乘法器A8、第九模拟乘法器A9、第十模拟乘法器A10；第六十一电阻R61、第六十二电阻R62、第六十三电阻R63、第六十四电阻R64、第六十五电阻R65与第二十一运算放大器U21、第十电容C10构成第一反相加法积分器，第六十六电阻R66、第六十七电阻R67与第二十二运算放大器U22构成第一反相器，第一反相加法积分器和第一反相器构成第一维电路；第六十八电阻R68、第六十九电阻R69、第七十电阻R70、第七十一电阻R71与第二十三运算放大器U23、第十一电容C11、第六模拟乘法器A6构成第二反相加法积分器，第七十二电阻R72、第七十三电阻R73与第二十四运算放大器U24构成第二反相器，第二反相加法积分器和第二反相器构成第二维电路；第七十四电阻R74、第七十五电阻R75与第二十五运算放大器U25、第十二电容C12、第七模拟乘法器A7构成第三反相加法积分器，第七十六电阻R76、第七十七电阻R77与第二十六运算放大器U26构成第三反相器，第三反相加法积分器和第三反相器构成第三维电路；第七十八电阻R78、第七十九电阻R79与第二十七运算放大器U27、第十三电容C13、第八模拟乘法器A8构成第四反相加法积分器，第八十电阻R80、第八十一电阻R81与第二十八运算放大器U28构成第四反相器，第四反相加法积分器和第四反相器构成第四维电路；第八十二电阻R82、第八十三电阻R83、第八十四电阻R84与第二十九运算放大器U29、第十四电容C14、第九模拟乘法器A9构成第五反相加法积分器，第八十五电阻R85、第八十六电阻R86与第三十运算放大器U30构成第五反相器，第五反相加法积分器和第五反相器构成第五维电路；第八十七电阻R87、第八十八电阻R88、第八十九电阻R89与第三十一运算放大器U31、第十五电容C15构成第六反相加法积分器，第九十电阻R90、第九十一电阻R91与第三十二运算放大器U32构成第六反相器，第六反相加法积分器和第六反相器构成第六维电路；第九十二电阻R92、第九十三电阻R93与第三十三运算放大器U33、第十六电容C16、第十模拟乘法器A10构成第七反相加法积分器，第九十四电阻R94、第九十五电阻R95与第三十四运算放大器U34构成第七反相器，第七反相加法积分器和第七反相器构成第七维电路；第九十六电阻R96、第九十七电阻R97与第三十五运算放大器U35、第十七电容C17构成第八反相加法积分器，第九十八电阻R98、第九十九电阻R99与第三十六运算放大器U36构成第八反相器，第八反相加法积分器和第八反相器构成第八维电路；第一百电阻R100与第三十七运算放大器U37、第十八电容C18构成第九反相加法积分器，第一百零一电阻R101、第一百零二电阻R102与第三十八运算放大器U38构成第九反相器，第九反相加法积分器和第九反相器构成第九维电路。As shown in FIG. 2 , the driving circuit includes a twenty-first operational amplifier U21, a twenty-second operational amplifier U22, a twenty-third operational amplifier U23, a twenty-fourth operational amplifier U24, and a twenty-fifth operational amplifier U25 , the twenty-sixth operational amplifier U26, the twenty-seventh operational amplifier U27, the twenty-eighth operational amplifier U28, the twenty-ninth operational amplifier U29, the thirtieth operational amplifier U30, the thirty-first operational amplifier U31, the third Twelve operational amplifier U32, thirty-third operational amplifier U33, thirty-fourth operational amplifier U34, thirty-fifth operational amplifier U35, thirty-sixth operational amplifier U36, thirty-seventh operational amplifier U37, thirty-eighth Operational amplifier U38, sixty-first resistor R61, sixty-second resistor R62, sixty-third resistor R63, sixty-fourth resistor R64, sixty-fifth resistor R65, sixty-sixth resistor R66, sixty-seventh resistor Resistor R67, sixty-eighth resistor R68, sixty-ninth resistor R69, seventieth resistor R70, seventy-first resistor R71, seventy-second resistor R72, seventy-third resistor R73, seventy-fourth resistor R74 , the seventy-fifth resistor R75, the seventy-sixth resistor R76, the seventy-seventh resistor R77, the seventy-eighth resistor R78, the seventy-ninth resistor R79, the eightieth resistor R80, the eighty-first resistor R81, the seventh Eighty-second resistor R82, eighty-third resistor R83, eighty-fourth resistor R84, eighty-fifth resistor R85, eighty-sixth resistor R86, eighty-seventh resistor R87, eighty-eighth resistor R88, eighth Nineteenth resistor R89, ninetieth resistor R90, ninety-first resistor R91, ninety-second resistor R92, ninety-third resistor R93, ninety-fourth resistor R94, ninety-fifth resistor R95, ninety-sixth resistor Resistor R96, ninety-seventh resistor R97, ninety-eighth resistor R98, ninety-ninth resistor R99, one-hundred resistor R100, one-hundred-first resistor R101, one-hundred-second resistor R102, tenth capacitor C10 , the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the seventeenth capacitor C17, the eighteenth capacitor C18, the Six analog multipliers A6, seventh analog multiplier A7, eighth analog multiplier A8, ninth analog multiplier A9, tenth analog multiplier A10; sixty-first resistor R61, sixty-second resistor R62, sixth analog multiplier The thirteenth resistor R63, the sixty-fourth resistor R64, the sixty-fifth resistor R65, the twenty-first operational amplifier U21, and the tenth capacitor C10 form the first inverting adding integrator, the sixty-sixth resistor R66, the sixtieth The seventh resistor R67 and the twenty-second operational amplifier U22 form the first inverter, the first inverting addition integrator and the first inverter form the first dimension circuit; the sixty-eighth resistor R68 and the sixty-ninth resistor R69 , the seventieth resistor R70, the seventy-first resistor R71 and the twenty-third operational amplifier U23, the eleventh resistor The capacitor C11 and the sixth analog multiplier A6 form the second inverting adding integrator, the seventy-second resistor R72, the seventy-third resistor R73 and the twenty-fourth operational amplifier U24 form the second inverter, and the second inverting The adding integrator and the second inverter form a second-dimensional circuit; the seventy-fourth resistor R74, the seventy-fifth resistor R75, the twenty-fifth operational amplifier U25, the twelfth capacitor C12, and the seventh analog multiplier A7 form The third inverting adding integrator, the seventy-sixth resistor R76, the seventy-seventh resistor R77 and the twenty-sixth operational amplifier U26 form the third inverter, and the third inverting adding integrator and the third inverter form The third three-dimensional circuit; the seventy-eighth resistor R78, the seventy-ninth resistor R79, the twenty-seventh operational amplifier U27, the thirteenth capacitor C13, and the eighth analog multiplier A8 form the fourth inverting adding integrator, the eighty The resistor R80, the eighty-first resistor R81 and the twenty-eighth operational amplifier U28 form a fourth inverter, and the fourth inverting adding integrator and the fourth inverter form a fourth-dimensional circuit; the eighty-second resistor R82, The eighty-third resistor R83, the eighty-fourth resistor R84, the twenty-ninth operational amplifier U29, the fourteenth capacitor C14, and the ninth analog multiplier A9 form the fifth inverting adding integrator. The eighty-fifth resistor R85, The eighty-sixth resistor R86 and the thirtieth operational amplifier U30 form the fifth inverter, the fifth inverting addition integrator and the fifth inverter form the fifth-dimensional circuit; the eighty-seventh resistor R87, the eighty-eighth The resistor R88, the eighty-ninth resistor R89 and the thirty-first operational amplifier U31 and the fifteenth capacitor C15 form the sixth inverting adding integrator, the ninetieth resistor R90, the ninety-first resistor R91 and the thirty-second operation The amplifier U32 forms the sixth inverter, the sixth inverting addition integrator and the sixth inverter form the sixth dimension circuit; the ninety-second resistor R92, the ninety-third resistor R93 and the thirty-third operational amplifier U33, The sixteenth capacitor C16 and the tenth analog multiplier A10 form the seventh inverting adding integrator. The ninety-fourth resistor R94, the ninety-fifth resistor R95 and the thirty-fourth operational amplifier U34 form the seventh inverter. The seven-inverting adding integrator and the seventh inverter form the seventh-dimensional circuit; the ninety-sixth resistor R96, the ninety-seventh resistor R97, the thirty-fifth operational amplifier U35, and the seventeenth capacitor C17 form the eighth inverting circuit The adding integrator, the ninety-eighth resistor R98, the ninety-ninth resistor R99 and the thirty-sixth operational amplifier U36 form the eighth inverter, and the eighth inverting adding integrator and the eighth inverter form the eighth-dimensional circuit ; The 100th resistor R100 and the 37th operational amplifier U37 and the 18th capacitor C18 constitute the ninth inverting adding integrator, the 101st resistor R101, the 102nd resistor R102 and the 38th operation The amplifier U38 constitutes a ninth inverter, and the ninth inverting adding integrator and the ninth inverter constitute a ninth dimension circuit.
上述九维驱动电路第一维电路中，第六十一电阻的一端、第六十二电阻的一端、第六十三电阻的一端、第六十四电阻的一端、第六十五电阻的一端连接在一起并接至第二十一运算放大器的反相输入端，第六十一电阻的另一端连接第七维电路中的第三十四运算放大器的输出端，第六十二电阻的另一端连接第九维电路中的第三十七运算放大器的输出端，第六十三电阻的另一端连接第四维电路中的第二十八运算放大器的输出端，第六十四电阻的另一端连接第二维电路中的第二十四运算放大器的输出端，第六十五电阻的另一端连接第一维电路中的第二十一运算放大器的输出端，第二十一运算放大器的同相输入端接地，所述第十电容跨接在第二十一运算放大器的反相输入端与输出端之间，第二十一运算放大器的输出端接第六十六电阻后接至第二十二运算放大器的反相输入端，第二十二运算放大器的同相输入端接地，所述第六十七电阻跨接在第二十二运算放大器的反相输入端与输出端之间。In the first-dimensional circuit of the nine-dimensional drive circuit, one end of the sixty-first resistor, one end of the sixty-second resistor, one end of the sixty-third resistor, one end of the sixty-fourth resistor, and one end of the sixty-fifth resistor Connected together and connected to the inverting input terminal of the twenty-first operational amplifier, the other end of the sixty-first resistor is connected to the output terminal of the thirty-fourth operational amplifier in the seventh-dimensional circuit, and the other end of the sixty-second resistor is connected. One end is connected to the output end of the thirty-seventh operational amplifier in the ninth dimension circuit, the other end of the sixty-third resistor is connected to the output end of the twenty-eighth operational amplifier in the fourth dimension circuit, and the other end of the sixty-fourth resistor is connected to the output end of the twenty-eighth operational amplifier in the fourth dimension circuit. One end is connected to the output end of the twenty-fourth operational amplifier in the second-dimensional circuit, the other end of the sixty-fifth resistor is connected to the output end of the twenty-first operational amplifier in the first-dimensional circuit, and the The non-inverting input terminal is grounded, the tenth capacitor is connected across the inverting input terminal and the output terminal of the twenty-first operational amplifier, and the output terminal of the twenty-first operational amplifier is connected to the sixty-sixth resistor and then connected to the second The inverting input terminal of the twelve operational amplifiers, the non-inverting input terminal of the twenty-second operational amplifier is grounded, and the sixty-seventh resistor is connected across the inverting input terminal and the output terminal of the twenty-second operational amplifier.
所述九维驱动电路第二维电路中，第六十八电阻的一端、第六十九电阻的一端、第七十电阻、第七十一电阻的一端连接在一起并接至第二十三运算放大器的反相输入端，第六十八电阻的另一端与第五维电路中的第二十九运算放大器的输出端相连，第六十九电阻的另一端连接第二维电路中的第二十三运算放大器的输出端，第七十电阻的另一端连接第一维电路中的第二十二运算放大器的输出端，第七十一电阻的另一端与第六模拟乘法器的输出端相连，第六模拟乘法器的另一个输入端连接第三维电路中的第二十五运算放大器的输出端，第六模拟乘法器的其中一个输入端与第一维电路中第二十一运算放大器的输出端相连，所述第二十三运算放大器的同相输入端接地，第十一电容跨接在第二十三运算放大器的反相输入端与输出端之间，第二十三运算放大器的输出端经第七十二电阻后接至第二十四运算放大器的反相输入端，第二十四运算放大器的同相输入端接地，第七十三电阻跨接在第二十四运算放大器的反相输入端与输出端之间。In the second-dimensional circuit of the nine-dimensional drive circuit, one end of the sixty-eighth resistor, one end of the sixty-ninth resistor, one end of the seventieth resistor, and one end of the seventy-first resistor are connected together and connected to the twenty-third The inverting input terminal of the operational amplifier, the other end of the sixty-eighth resistor is connected to the output terminal of the twenty-ninth operational amplifier in the fifth-dimensional circuit, and the other end of the sixty-ninth resistor is connected to the second-dimensional circuit. The output terminal of the twenty-third operational amplifier, the other end of the seventieth resistor is connected to the output terminal of the twenty-second operational amplifier in the first-dimensional circuit, and the other end of the seventy-first resistor is connected to the output terminal of the sixth analog multiplier connected, the other input terminal of the sixth analog multiplier is connected to the output terminal of the twenty-fifth operational amplifier in the third-dimensional circuit, and one of the input terminals of the sixth analog multiplier is connected to the twenty-first operational amplifier in the first-dimensional circuit. The non-inverting input terminal of the twenty-third operational amplifier is connected to the ground, the eleventh capacitor is connected across the inverting input terminal and the output terminal of the twenty-third operational amplifier, and the The output terminal is connected to the inverting input terminal of the twenty-fourth operational amplifier through the seventy-second resistor, the non-inverting input terminal of the twenty-fourth operational amplifier is grounded, and the seventy-third resistor is connected across the twenty-fourth operational amplifier. between the inverting input and the output.
所述九维驱动电路第三维电路中，第七十四电阻的一端、第七十五电阻的一端连接在一起并接至第二十五运算放大器的反相输入端，第七十四电阻的另一端与第三维电路中的第二十五运算放大器的输出端相连，第七十五电阻的另一端与第七模拟乘法器的输出端相连，第七模拟乘法器的另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第七模拟乘法器的其中一个输入端与第一维电路中的第二十二运算放大器的输出端相连，所述第二十五运算放大器的同相输入端接地，第十二电容跨接在第二十五运算放大器的反相输入端与输出端之间，第二十五运算放大器的输出端经第七十六电阻后接至第二十六运算放大器的反相输入端，第二十六运算放大器的同相输入端接地，第七十七电阻跨接在第二十六运算放大器的反相输入端与输出端之间。In the third-dimensional circuit of the nine-dimensional drive circuit, one end of the seventy-fourth resistor and one end of the seventy-fifth resistor are connected together and connected to the inverting input terminal of the twenty-fifth operational amplifier, and one end of the seventy-fourth resistor is connected to the inverting input of the twenty-fifth operational amplifier. The other end is connected to the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, the other end of the seventy-fifth resistor is connected to the output end of the seventh analog multiplier, and the other input end of the seventh analog multiplier is connected to the seventh analog multiplier. The output terminal of the twenty-third operational amplifier in the two-dimensional circuit is connected, and one of the input terminals of the seventh analog multiplier is connected to the output terminal of the twenty-second operational amplifier in the first-dimensional circuit. The non-inverting input terminal of the operational amplifier is grounded, the twelfth capacitor is connected between the inverting input terminal and the output terminal of the twenty-fifth operational amplifier, and the output terminal of the twenty-fifth operational amplifier is connected to the seventy-sixth resistor. The inverting input terminal of the twenty-sixth operational amplifier, the non-inverting input terminal of the twenty-sixth operational amplifier is grounded, and the seventy-seventh resistor is connected across the inverting input terminal and the output terminal of the twenty-sixth operational amplifier.
所述九维驱动电路第四维电路中，第七十八电阻的一端、第七十九电阻的一端连接在一起并接至第二十七运算放大器的反相输入端，第七十八电阻的另一端与第四维电路中的第二十七运算放大器的输出端连接，第七十九电阻的另一端与第八模拟乘法器的输出端连接，第八模拟乘法器的一个输入端与第三维电路中的第二十五运算放大器的输出端相连，第八模拟乘法器的其中另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第二十七运算放大器的同相输入端接地，第十三电容跨接在第二十七运算放大器的反相输入端与输出端之间，第二十七运算放大器的输出端经第八十电阻后接至第二十八运算放大器的反相输入端，第二十八运算放大器的同相输入端接地，第八十一电阻跨接在第二十八运算放大器的反相输入端与输出端之间。In the fourth-dimensional circuit of the nine-dimensional drive circuit, one end of the seventy-eighth resistor and one end of the seventy-ninth resistor are connected together and connected to the inverting input terminal of the twenty-seventh operational amplifier, and the seventy-eighth resistor The other end is connected to the output end of the twenty-seventh operational amplifier in the fourth-dimensional circuit, the other end of the seventy-ninth resistor is connected to the output end of the eighth analog multiplier, and one input end of the eighth analog multiplier is connected to the output end of the eighth analog multiplier. The output terminal of the twenty-fifth operational amplifier in the third-dimensional circuit is connected, the other input terminal of the eighth analog multiplier is connected to the output terminal of the twenty-third operational amplifier in the second-dimensional circuit, and the twenty-seventh operational amplifier The non-inverting input terminal of the amplifier is grounded, the thirteenth capacitor is connected between the inverting input terminal and the output terminal of the twenty-seventh operational amplifier, and the output terminal of the twenty-seventh operational amplifier is connected to the second The inverting input terminal of the eighteenth operational amplifier, the non-inverting input terminal of the twenty-eighth operational amplifier are grounded, and the eighty-first resistor is connected across the inverting input terminal and the output terminal of the twenty-eighth operational amplifier.
所述九维驱动电路第五维电路中，第八十二电阻的一端、第八十三电阻、第八十四电阻的一端连接在一起并接至第二十九运算放大器的反相输入端，第八十二电阻的另一端连接第二维电路中的第二十三运算放大器的输出端，第八十三电阻的另一端连接第五维电路中的第三十运算放大器的输出端，第八十四电阻的另一端与第九模拟乘法器的输出端相连，第九模拟乘法器的一个输入端与第三维电路中的第二十五运算放大器的输出端连接，第九模拟乘法器的其中另一个输入端与第二维电路中的第二十四运算放大器的输出端连接，第二十九运算放大器的同相输入端接地，第十四电容跨接在第二十九运算放大器的反相输入端与输出端之间，第二十九运算放大器的输出端经第八十五电阻连接到第三十运算放大器的反相输入端，第三十运算放大器的同相输入端接地，第八十六电阻跨接在第三十运算放大器的反相输入端与输出端之间。In the fifth-dimensional circuit of the nine-dimensional drive circuit, one end of the eighty-second resistor, one end of the eighty-third resistor, and one end of the eighty-fourth resistor are connected together and connected to the inverting input terminal of the twenty-ninth operational amplifier , the other end of the eighty-second resistor is connected to the output end of the twenty-third operational amplifier in the second-dimensional circuit, and the other end of the eighty-third resistor is connected to the output end of the thirtieth operational amplifier in the fifth-dimensional circuit, The other end of the eighty-fourth resistor is connected to the output end of the ninth analog multiplier, and one input end of the ninth analog multiplier is connected to the output end of the twenty-fifth operational amplifier in the third-dimensional circuit, and the ninth analog multiplier is One of the other input terminals is connected to the output terminal of the twenty-fourth operational amplifier in the second-dimensional circuit, the non-inverting input terminal of the twenty-ninth operational amplifier is grounded, and the fourteenth capacitor is connected across the twenty-ninth operational amplifier. Between the inverting input terminal and the output terminal, the output terminal of the twenty-ninth operational amplifier is connected to the inverting input terminal of the thirtieth operational amplifier through the eighty-fifth resistor, the non-inverting input terminal of the thirtieth operational amplifier is grounded, and the The eighty-six resistors are connected across the inverting input terminal and the output terminal of the thirtieth operational amplifier.
所述九维驱动电路第六维电路中，第八十七电阻的一端、第八十八电阻、第八十九电阻的一端连接在一起并接至第三十一运算放大器的反相输入端，第八十七电阻的另一端连接第五维电路中的第二十九运算放大器的输出端，第八十八电阻的另一端连接第四维电路中的第二十八运算放大器的输出端，第八十九电阻的另一端连接第六维电路中的第三十一运算放大器的输出端，第三十一运算放大器的同相输入端接地，第十五电容跨接在第三十一运算放大器的反相输入端与输出端之间，第三十一运算放大器的输出端经第九十电阻连接到第三十二运算放大器的反相输入端，第三十二运算放大器的同相输入端接地，第九十一电阻跨接在第三十二运算放大器的反相输入端与输出端之间。In the sixth-dimensional circuit of the nine-dimensional driving circuit, one end of the eighty-seventh resistor, one end of the eighty-eighth resistor, and one end of the eighty-ninth resistor are connected together and connected to the inverting input end of the thirty-first operational amplifier , the other end of the eighty-seventh resistor is connected to the output of the twenty-ninth operational amplifier in the fifth-dimensional circuit, and the other end of the eighty-eighth resistor is connected to the output of the twenty-eighth operational amplifier in the fourth-dimensional circuit , the other end of the eighty-ninth resistor is connected to the output terminal of the thirty-first operational amplifier in the sixth-dimensional circuit, the non-inverting input terminal of the thirty-first operational amplifier is grounded, and the fifteenth capacitor is connected across the thirty-first operational amplifier Between the inverting input terminal and the output terminal of the amplifier, the output terminal of the thirty-first operational amplifier is connected to the inverting input terminal of the thirty-second operational amplifier through the ninetieth resistor, and the non-inverting input terminal of the thirty-second operational amplifier Ground, the ninety-first resistor is connected across the inverting input terminal and the output terminal of the thirty-second operational amplifier.
所述九维驱动电路第七维电路中，第九十二电阻的一端、第九十三电阻的一端连接在一起并接至第三十三运算放大器的反相输入端，第九十二电阻的另一端连接第七维电路中的第三十三运算放大器的输出端，第九十三电阻的另一端与第十模拟乘法器的输出端相连，第十模拟乘法器的一个输入端与第四维电路中的第二十七运算放大器的输出端连接，第十模拟乘法器的其中另一个输入端与第二维电路中的第二十三运算放大器的输出端连接，第三十三运算放大器的同相输入端接地，第十六电容跨接在第三十三运算放大器的反相输入端与输出端之间，第三十三运算放大器的输出端经第九十四电阻连接到第三十四运算放大器的输入端，第三十四运算放大器的同相输入端接地，第九十五电阻跨接在第三十四运算放大器的反相输入端与输出端之间。In the seventh-dimensional circuit of the nine-dimensional drive circuit, one end of the ninety-second resistor and one end of the ninety-third resistor are connected together and connected to the inverting input of the thirty-third operational amplifier, and the ninety-second resistor is connected to the inverting input terminal of the thirty-third operational amplifier. The other end of the resistor is connected to the output end of the thirty-third operational amplifier in the seventh-dimensional circuit, the other end of the ninety-third resistor is connected to the output end of the tenth analog multiplier, and one input end of the tenth analog multiplier is connected to the output end of the tenth analog multiplier. The output terminal of the twenty-seventh operational amplifier in the four-dimensional circuit is connected, and the other input terminal of the tenth analog multiplier is connected to the output terminal of the twenty-third operational amplifier in the second-dimensional circuit. The non-inverting input terminal of the amplifier is grounded, the sixteenth capacitor is connected between the inverting input terminal and the output terminal of the thirty-third operational amplifier, and the output terminal of the thirty-third operational amplifier is connected to the third operational amplifier through the ninety-fourth resistor. The input terminal of the fourteenth operational amplifier, the non-inverting input terminal of the thirty-fourth operational amplifier is grounded, and the ninety-fifth resistor is connected across the inverting input terminal and the output terminal of the thirty-fourth operational amplifier.
所述九维驱动电路第八维电路中，第九十六电阻的一端、第九十七电阻的一端连接在一起并接至第三十五运算放大器的反相输入端，第九十六电阻的另一端连接第八维电路中的第三十五运算放大器的输出端，第九十七电阻的另一端与第二维电路中的第二十四运算放大器的输出端连接，第三十五运算放大器的同相输入端接地，第十七电容跨接在第三十五运算放大器的反相输入端与输出端之间，第三十五运算放大器的输出端经第九十八电阻连接到第三十六运算放大器的输入端，第三十八运算放大器的同相输入端接地，第九十九电阻跨接在第三十六运算放大器的反相输入端与输出端之间。In the eighth-dimensional circuit of the nine-dimensional drive circuit, one end of the ninety-sixth resistor and one end of the ninety-seventh resistor are connected together and connected to the inverting input of the thirty-fifth operational amplifier, and the ninety-sixth resistor The other end of the resistor is connected to the output of the thirty-fifth operational amplifier in the eighth-dimensional circuit, the other end of the ninety-seventh resistor is connected to the output of the twenty-fourth operational amplifier in the second-dimensional circuit, and the thirty-fifth The non-inverting input terminal of the operational amplifier is grounded, the seventeenth capacitor is connected between the inverting input terminal and the output terminal of the thirty-fifth operational amplifier, and the output terminal of the thirty-fifth operational amplifier is connected to the sixth operational amplifier through the ninety-eighth resistor. The input terminal of the thirty-sixth operational amplifier, the non-inverting input terminal of the thirty-eighth operational amplifier are grounded, and the ninety-ninth resistor is connected across the inverting input terminal and the output terminal of the thirty-sixth operational amplifier.
所述九维驱动电路第九维电路中，第一百电阻的一端连接第三十七运算放大器的反相输入端，第一百电阻的另一端与第一维电路中的第二十二运算放大器的输出端相连，第三十七运算放大器的同相输入端接地，第十八电容跨接在第三十七运算放大器的反相输入端与输出端之间，第三十七运算放大器的输出端经第一百零一电阻连接到第三十八运算放大器的输入端，第三十八运算放大器的同相输入端接地，第一百零二电阻跨接在第三十八运算放大器的反相输入端与输出端之间。In the ninth-dimensional circuit of the nine-dimensional drive circuit, one end of the one hundredth resistor is connected to the inverting input terminal of the thirty-seventh operational amplifier, and the other end of the one hundredth resistor is connected to the twenty-second operational amplifier in the first-dimensional circuit. The output terminal of the amplifier is connected, the non-inverting input terminal of the thirty-seventh operational amplifier is grounded, the eighteenth capacitor is connected across the inverting input terminal and the output terminal of the thirty-seventh operational amplifier, and the output of the thirty-seventh operational amplifier is connected to the ground. The terminal is connected to the input terminal of the thirty-eighth operational amplifier through the 101st resistor, the non-inverting input terminal of the 38th operational amplifier is grounded, and the 102nd resistor is connected across the inverting phase of the 38th operational amplifier. between the input and output.
上述的九维超混沌通信加密电路，所述九维驱动电路中，第二十二运算放大器、第二十四运算放大器、第二十六运算放大器、第二十八运算放大器、第三十运算放大器、第三十二运算放大器、第三十四运算放大器、第三十六运算放大器、第三十八运算放大器的输出端引出作为驱动电路的输出端，用于耦合同步，使得响应系统与驱动系统实现同步，第二十三运算放大器的输出端引出并作为驱动电路的另一个输出端，作为高维信号来遮掩需要传递的信号。The above-mentioned nine-dimensional hyperchaotic communication encryption circuit, in the nine-dimensional drive circuit, the twenty-second operational amplifier, the twenty-fourth operational amplifier, the twenty-sixth operational amplifier, the twenty-eighth operational amplifier, and the thirtieth operational amplifier The output terminals of the amplifier, the thirty-second operational amplifier, the thirty-fourth operational amplifier, the thirty-sixth operational amplifier, and the thirty-eighth operational amplifier are drawn out as the output terminal of the driving circuit for coupling synchronization, so that the response system and the driving The system realizes synchronization, and the output end of the twenty-third operational amplifier is drawn out and used as another output end of the drive circuit, which is used as a high-dimensional signal to mask the signal to be transmitted.
如图3所示，所述响应电路包括与驱动电路中的第六十一电阻R61至第六一百零二电阻R102、第二十一运算放大器U21至第三十八运算放大器U38、第十电容C10至第十八电容C18、第六模拟乘法器A6至第十模拟乘法器A10一一相对应的第四电阻R4至第六十电阻R60、第三运算放大器U3至第二十运算放大器U20、第一电容C1至第九电容C9、第一模拟乘法器A1至第五模拟乘法器A5，且响应电路中各元器件之间的连接关系与驱动电路中各元器件之间的连接关系大致相同，其区别在于：响应电路在驱动电路的基础上加上了一个控制器，并确保两个混沌系统同步所需要的耦合系数，使驱动系统与响应系统同步。响应电路中第五运算放大器U5的输出端，即Y_2作为响应电路的输出端，用于信号解密。As shown in FIG. 3 , the response circuit includes the sixty-first resistor R61 to the sixty-second resistor R102, the twenty-first operational amplifier U21 to the thirty-eighth operational amplifier U38, the tenth The capacitors C10 to the eighteenth capacitor C18, the sixth analog multiplier A6 to the tenth analog multiplier A10 correspond one by one to the fourth resistor R4 to the sixtieth resistor R60, and the third operational amplifier U3 to the twentieth operational amplifier U20 , the first capacitor C1 to the ninth capacitor C9, the first analog multiplier A1 to the fifth analog multiplier A5, and the connection relationship between the components in the response circuit is roughly the same as the connection relationship between the components in the drive circuit The same, the difference is that the response circuit adds a controller to the driving circuit, and ensures the coupling coefficient required for the synchronization of the two chaotic systems, so that the driving system and the response system are synchronized. The output terminal of the fifth operational amplifier U5 in the response circuit, that is, Y_2, is used as the output terminal of the response circuit for signal decryption.
如图4所示，所述加密电路包括第一百零三电阻R103、第一百零四电阻R104、第一百零五电阻R105、第一运算放大器U1，第一百零三电阻R103的一端引出作为加密电路的第一输入端，用来接收需要加密的有效信号S，第一百零三R103电阻的另一端与第一运算放大器U1的反相输入端连接，第一百零四电阻R104的一端引出作为加密电路的第二输入端，用来接收驱动电路的第二输出端输出的信号Y，第一百零四电阻R104的另一端与第一运算放大器U1的反相输入端连接，第一运算放大器U1的同相输入端接地，第一百零五电阻R105跨接在第一运算放大器U1的反相输入端与输出端之间，第一运算放大器U1的输出端作为加密电路的输出端S1。As shown in FIG. 4 , the encryption circuit includes the one-hundred and third resistor R103, the one-hundred and fourth resistor R104, the one-hundred and fifth resistor R105, the first operational amplifier U1, and one end of the one-hundred and third resistor R103 Lead out as the first input terminal of the encryption circuit to receive the valid signal S that needs to be encrypted. The other end of the one hundred and three resistor R103 is connected to the inverting input terminal of the first operational amplifier U1, and the one hundred and fourth resistor R104 One end of the R104 is led out as the second input end of the encryption circuit, which is used to receive the signal Y output by the second output end of the driving circuit, and the other end of the one hundred and fourth resistor R104 is connected to the inverting input end of the first operational amplifier U1, The non-inverting input terminal of the first operational amplifier U1 is grounded, the one hundred and fifth resistor R105 is connected across the inverting input terminal and the output terminal of the first operational amplifier U1, and the output terminal of the first operational amplifier U1 is used as the output of the encryption circuit terminal S1.
如图5所示，所述解密电路包括第一百零六R106电阻、第一百零七电阻R107、第一百零八电阻R108、第二运算放大器U2，第一百零六电阻R106的一端引出作为解密电路的第一输入端，用来接收待解密的信号S1，第一百零六电阻R106的另一端与第二运算放大器U2的反相输入端连接，第一百零七电阻R107的一端引出作为解密电路的第二输入端，用来接收驱动系统中输出的解密信号Y_2，第一百零七电阻R107的另一端与第二运算放大器U2的反相输入端连接，第二运算放大器的同相输入端接地，第一百零八电阻R108跨接在第二运算放大器U2的反相输入端与输出端之间，第二运算放大器的输出端作为解密电路的输出端S2。As shown in FIG. 5 , the decryption circuit includes the one-hundred and sixth resistor R106, the one-hundred and seventh resistor R107, the one-hundred and eighth resistor R108, the second operational amplifier U2, and one end of the one-hundred and sixth resistor R106 The first input terminal of the decryption circuit is led out to receive the signal S1 to be decrypted. The other end of the one hundred and sixth resistor R106 is connected to the inverting input terminal of the second operational amplifier U2. One end leads to the second input end of the decryption circuit, which is used to receive the decryption signal Y_2 output in the drive system, and the other end of the one hundred and seventh resistor R107 is connected to the inverting input end of the second operational amplifier U2. The non-inverting input terminal of the 108 is grounded, and the one hundred and eighth resistor R108 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier is used as the output terminal S2 of the decryption circuit.
如图1、图4、图5所示，图中以函数发生器指代信号源，此为需要传递的有效信息，为整个保密通讯电路提供需要保密的信号S，从驱动电路中输出高维超混沌信号Y，S和Y两个信号经过加密电路进行叠加得到S1=-S-Y，使得驱动电路产生的高维超混沌信号Y遮掩住需要保密的信号S，加密电路输出加密后信号S1至解密电路，从响应电路输出的高维超混沌信号Y_2用于解密信号，S1和Y_2两个信号经过解密电路进行叠加得到S2= -S1- Y_2，解密电路的输出端输出解密后信号S2，在经过短暂时间后，驱动系统和响应系统相同步后，响应电路产生的高维超混沌信号Y_2抵消掉加密后信号S1中的信号Y，解密后得到的信号S2与加密前的原始信号S波形一致。As shown in Figure 1, Figure 4, and Figure 5, the function generator is used to refer to the signal source, which is the effective information to be transmitted, provides the signal S that needs to be kept secret for the entire secure communication circuit, and outputs high-dimensional hyperchaos from the drive circuit Signals Y, S and Y are superimposed by the encryption circuit to obtain S1=-S-Y, so that the high-dimensional hyperchaotic signal Y generated by the drive circuit covers the signal S that needs to be kept secret, and the encryption circuit outputs the encrypted signal S1 to the decryption circuit, from the response The high-dimensional hyperchaotic signal Y_2 output by the circuit is used to decrypt the signal. The two signals S1 and Y_2 are superimposed by the decryption circuit to obtain S2=-S1- Y_2. The output of the decryption circuit outputs the decrypted signal S2. After a short time, the drive system After synchronizing with the response system, the high-dimensional hyperchaotic signal Y_2 generated by the response circuit cancels the signal Y in the encrypted signal S1, and the signal S2 obtained after decryption is consistent with the original signal S before encryption.
所述第一至第三十九运算放大器均采用TL085，第一至第十模拟乘法器均采用AD633。The first to thirty-ninth operational amplifiers all use TL085, and the first to tenth analog multipliers all use AD633.
本发明的工作原理如下：首先驱动系统因自激振荡产生信号，利用耦合同步方法实现同步。从而从驱动系统和响应系统中得到两个在短暂时间后便一致的高维超混沌加密信号Y和高维超混沌解密信号Y_2。信号源输出需要传递的有效信号S（需要注意的是有效信号S的电压幅值需小于或远小于加密信号电压幅值），经过加密电路后与加密信号Y叠加，得到信号S1=-S-Y，信号发送方发出信号S1，当接收方收到S1，经过解密电路与Y_2叠加，得到解密后信号S2= -S1- Y_2，在经过短暂时间后，驱动系统和响应系统达到同步，可得到Y_2=Y，则接收到的S2=S，则实现了解密，得到了有效信号。其中，通过稳压整流电路，可将普通家庭用电220V交流电转换为
本发明所涉及的系统无量纲数学模型如下：The system dimensionless mathematical model involved in the present invention is as follows:
式（1）中, 
为方便电路实现以及方便示波器显示，将以上无量纲数学模型修改成如下模型：In order to facilitate circuit implementation and facilitate oscilloscope display, the above dimensionless mathematical model is modified into the following model:
按照式（2）可得出本发明驱动系统的电路方程为：According to formula (2), the circuit equation of the driving system of the present invention can be obtained as:
综合式（2）、式（3），使电容
可以求得所有电阻的值分别为：The values of all resistors can be obtained as:
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