CN111697050B - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same Download PDF

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Publication number
CN111697050B
CN111697050B CN201910189050.1A CN201910189050A CN111697050B CN 111697050 B CN111697050 B CN 111697050B CN 201910189050 A CN201910189050 A CN 201910189050A CN 111697050 B CN111697050 B CN 111697050B
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gate electrode
well region
semiconductor device
conductivity type
forming
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CN111697050A (en
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李文山
李宗晔
陈富信
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Abstract

The invention provides a semiconductor device and a method of forming the same, the semiconductor device comprising a substrate of a first conductivity type, an epitaxial layer of the first conductivity type disposed on the substrate and having a trench therein, a first well region disposed in the epitaxial layer and below the trench and of a second conductivity type different from the first conductivity type, a first gate electrode disposed in the trench and of the second conductivity type, and a second gate electrode disposed in the trench and above the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer. The invention also provides a method for manufacturing the semiconductor device. The invention has the advantages of less process steps, low cost and capability of reducing the size of elements.

Description

Semiconductor device and method of forming the same
Technical Field
The present invention relates to semiconductor technologies, and in particular, to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a trench gate (trench gate) and a super junction (super junction) structure and a method for forming the MOSFET.
Background
In order to achieve high voltage and high current, the flow of driving current in conventional power transistors is developed from a planar direction to a vertical direction. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) having trench gates and super junction structures have been developed to increase the doping concentration of the n-type epitaxial drift doped region, thereby improving the on-resistance of the device.
Conventionally, a multi-layer epitaxy (multi-epi) technique, which requires multiple process cycles including epitaxy, implantation of p-type dopants, and high temperature diffusion, is used to form superjunction structures. Therefore, the above multilayer epitaxy technique has the disadvantages of multiple process steps, high cost, etc. In addition, the device size of the conventional vertical diffused metal oxide semiconductor field effect transistor is difficult to be miniaturized.
Therefore, there is a need for a mosfet having a trenched gate and a super junction structure and a method of forming the same that can solve or improve the above-mentioned problems.
Disclosure of Invention
In some embodiments, a semiconductor device is provided, which has a reduced number of process steps, a reduced cost, and a reduced device size, and includes a substrate having a first conductivity type; the epitaxial layer is provided with a first conductive type, is arranged on the substrate and is internally provided with a groove; the first well region is arranged in the epitaxial layer and below the groove, and has a second conduction type different from the first conduction type; a first gate electrode disposed in the trench and having a second conductivity type; and a second gate electrode disposed in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer.
In some other embodiments, a method of forming a semiconductor device is provided, the method including providing a substrate having a first conductivity type; forming an epitaxial layer having a first conductivity type on a substrate; forming a trench in the epitaxial layer; forming a first well region having a second conductivity type in the epitaxial layer and below the trench, wherein the second conductivity type is different from the first conductivity type; forming a first gate electrode having a second conductivity type in the trench; and forming a second gate electrode in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer.
In the embodiment of the invention, the first well region is arranged below the bottom of the groove by an ion implantation process and a thermal drive-in process, so that process cycles including epitaxy, implantation of p-type dopants and high-temperature diffusion are not required to be carried out for many times. Therefore, the process for forming the first well region is simple and does not need to bear expensive epitaxy cost. Moreover, because the first well region is positioned below the bottom of the groove, the first well region does not occupy additional space, so that the unit space can be reduced, and the resistance of the channel region can be further reduced.
Drawings
Embodiments of the invention will be understood more fully from the detailed description given below, taken together with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of illustration.
Fig. 1-15 are cross-sectional views of various stages of a process for forming a semiconductor device, in accordance with some embodiments.
Description of the symbols:
100. a semiconductor device;
101. a substrate;
102. an epitaxial layer;
103. patterning the mask;
103a, 114a are open;
104. a trench;
105. a first well region;
106. 110 an insulating layer;
107. a first heavily doped region;
108. a first gate electrode;
109. a mask layer;
111. a second gate electrode;
112. a second well region;
113. a second heavily doped region;
114. a dielectric layer;
115. a contact point;
116. a contact doping region;
117. a metal layer.
Detailed Description
The following disclosure provides many different embodiments or examples for implementing different components of the provided high voltage semiconductor device. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments.
Referring to fig. 1-15, cross-sectional views of various stages of a process for forming the semiconductor device 100 of fig. 15 are shown, in accordance with some embodiments. Additional operations may be provided before, during, and/or after the stages described in fig. 1-15. In various embodiments, some of the operations described above may be removed, deleted, or replaced. Additional components may be added to the semiconductor device. In various embodiments, some of the components described below may be removed, deleted, or replaced.
According to some embodiments, as shown in fig. 1, a substrate 101 having a first conductivity type is provided and used as a Drain (Drain, D) of the semiconductor device 100. In some embodiments, the substrate 101 may be made of silicon or other semiconductor materials, or the substrate 101 may comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 101 may be made of a compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the substrate 101 includes a silicon-on-insulator (SOI) substrate or other suitable substrate. In this embodiment, the first conductivity type is n-type, but is not limited thereto. In some other embodiments, the first conductivity type can also be p-type.
Subsequently, according to some embodiments, an epitaxial growth (epitaxial growth) process is performed to form an epitaxial layer 102 on the substrate 101, wherein the substrate 101 and the epitaxial layer 102 have the same conductivity type, such as the first conductivity type. In the present embodiment, epitaxial layer 102 is n-type. In some embodiments, the doping concentration of epitaxial layer 102 is less than the doping concentration of substrate 101. In some embodiments, the epitaxial growth process may be Metal Organic Chemical Vapor Deposition (MOCVD), plasma-enhanced CVD (PECVD), molecular Beam Epitaxy (MBE), hydride Vapor Phase Epitaxy (HVPE), liquid Phase Epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable processes, or a combination thereof.
Next, according to some embodiments, as shown in fig. 2, a patterned mask 103 is formed on the epitaxial layer 102 by a photolithography patterning process, wherein the patterned mask 103 has an opening 103a. In the present embodiment, the material of the patterned mask 103 may be a photoresist material. In some other embodiments, the material of the patterning mask 103 may be a hard mask (hard mask) composed of an oxide layer and a nitride layer. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or a combination of the foregoing.
According to some embodiments, as shown in fig. 3, after forming the patterned mask 103, an etching process is performed on the epitaxial layer 102 through the opening 103a of the patterned mask 103 to form a trench 104 in the epitaxial layer 102. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof. It should be understood that the size, shape, and location of the trench 104 shown in fig. 3 are merely exemplary, and are not intended to limit the embodiments of the present invention.
Next, according to some embodiments, as shown in fig. 4, an ion implantation process and a thermal drive-in (drive in) process are performed on the trench 104 by using the patterned mask 103 as a protection mask to form a first well region 105. In the present embodiment, the first well region 105 is disposed below the trench 104, and the first well region 105 vertically overlaps the trench 104. In the present embodiment, the first well 105 has a different conductivity type, such as a second conductivity type, from the substrate 101 and the epitaxial layer 102. That is, in this documentIn an embodiment, the first well region 105 is p-type. In some embodiments, the dopant of the first well region 105 may be boron (B). In some embodiments, the first well 105 is doped at a concentration of about 1E15atoms/cm 3 To about 1E18atoms/cm 3 Within the range of (1).
In the present embodiment, by disposing the first well region 105 under the bottom of the trench 104 through an ion implantation process and a thermal drive-in process, a plurality of process cycles including epitaxy, implantation of p-type dopants, and high temperature diffusion are not required. Therefore, the process of forming the first well region 105 is simple and does not need to incur expensive epitaxial cost. Furthermore, since the first well region 105 is located below the bottom of the trench 104, the first well region 105 does not occupy additional space (e.g., space of the lateral epitaxial layer 102), so that the cell pitch (cell pitch) can be reduced, thereby reducing the channel resistance. In the present embodiment, the first well 105 of the second conductive type serves as a reduced surface field (RESURF) region, thereby increasing the breakdown voltage of the subsequently completed semiconductor device 100. That is, the first well region 105 can improve the voltage endurance of the semiconductor device 100.
According to some embodiments, as shown in FIG. 5, an insulating layer 106 is formed in the trench 104 and on the first well region 105 by an oxidation process, and a thermal drive-in process is performed on the insulating layer 106 to increase the densification of the insulating layer 106. In some embodiments, insulating layer 106 covers the portions of epitaxial layer 102 exposed by trenches 104. In some embodiments, the insulating layer 106 may be silicon oxide, germanium oxide, other suitable semiconductor oxide materials, or a combination of the foregoing. In some embodiments, the oxidation process may be a thermal oxidation process, a radical oxidation process, or other suitable process. In some embodiments, the thermal drive-in process may be a Rapid Thermal Annealing (RTA) process.
According to some embodiments, an etching process is performed to remove the bottom of the insulating layer 106, thereby exposing the first well 105, as shown in fig. 6. In some embodiments, sidewall portions of insulating layer 106 remain after the etching process. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
Next, according to some embodiments, the trench 104 is subjected to an ion implantation process using the patterned mask 103 and the sidewall portions of the remaining insulating layer 106 as a protection mask to form a first heavily doped region 107. In the present embodiment, the first heavily doped region 107 is in the upper portion of the first well 105. In the present embodiment, the first heavily doped region 107 and the first well 105 have the same conductivity type, such as the second conductivity type. That is, in the present embodiment, the first heavily doped region 107 is p-type. In some embodiments, the dopant of the first heavily doped region 107 may be boron difluoride (BF 2). In some embodiments, the doping concentration of first heavily doped region 107 is greater than the doping concentration of first well region 105. In some embodiments, the first heavily doped region 107 has a doping concentration of about 1E19atoms/cm 3 To about 1E21atoms/cm 3 Within the range of (1). In the present embodiment, the first heavily doped region 107 of the second conductivity type also serves as a surface field reduction (RESURF) region to further enhance the surface field reduction effect.
According to some embodiments, a first gate electrode material is formed in the trench 104 by a deposition process, a lithographic patterning process and an etching process, as illustrated in fig. 7. Next, an ion implantation process and a thermal drive-in process are performed on the first gate electrode material using the patterned mask 103 and the sidewall portions of the remaining insulating layer 106 as a protection mask to form a first gate electrode 108. In the present embodiment, the first gate electrode 108 fills the lower portion of the trench 104 without filling the trench 104, and the insulating layer 106 surrounds the first gate electrode 108. In the present embodiment, the insulating layer 106 is disposed between the first gate electrode 108 and the epitaxial layer 102. In the present embodiment, the first gate electrode 108 vertically overlaps the first well 105.
In some embodiments, the first gate electrode 108 may be one or more layers and may be formed of amorphous silicon, polysilicon, or a combination thereof, in some embodiments, the deposition process may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination thereof. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing.
In the present embodiment, the first gate electrode 108 and the first well 105 have the same conductivity type, such as the second conductivity type. That is, in the present embodiment, the first gate electrode 108 is p-type. In some embodiments, the dopant of the first gate electrode 108 may be boron difluoride (BF) 2 ). In some embodiments, the doping concentration of the first gate electrode 108 is greater than the doping concentration of the first well region 105. In some embodiments, the doping concentration of the first gate electrode 108 is about 1E19atoms/cm 3 To about 1E21atoms/cm 3 Within the range of (1). In the present embodiment, the first gate electrode 108 of the second conductivity type also serves as a surface field reduction (RESURF) region to further enhance the surface field reduction effect.
In the present embodiment, the first gate electrode 108, the first heavily doped region 107 and the first well 105 of the second conductivity type can be used together as a surface field reduction (RESURF) region to extend the length of the P-N junction depletion region and reduce the maximum electric field below the electrode, thereby increasing the breakdown voltage of the subsequently completed semiconductor device 100. That is, the first gate electrode 108, the first heavily doped region 107 and the first well region 105 can improve the voltage endurance capability of the semiconductor device 100. Moreover, compared to forming the resurf region only by the ion implantation process, in the present embodiment, the depth of the resurf region can be greatly increased by the first gate electrode 108, the first heavily doped region 107 and the first well region 105, and the voltage endurance capability of the semiconductor device 100 can be further greatly increased.
Next, according to some embodiments, as shown in fig. 8, an upper portion of the insulating layer 106 is removed by an etching process. In some embodiments, after the etching process, the top surface of the insulating layer 106 is higher than the top surface of the first gate electrode 108. In some other embodiments, after the etching process, the top surface of the insulating layer 106 is lower than the top surface of the first gate electrode 108. In some other embodiments, after the etching process, a top surface of the insulating layer 106 is coplanar with a top surface of the first gate electrode 108. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing.
According to some embodiments, a mask layer 109 is formed on the first gate electrode 108 in the trench 104, as shown in fig. 9. In the present embodiment, the mask layer 109 covers the insulating layer 106 and the first gate electrode 108. In some embodiments, the material of the mask layer 109 is the same as the material of the patterned mask 103. In some other embodiments, the material of the mask layer 109 is different from the material of the patterning mask 103. In some embodiments, the mask layer 109 is formed by a deposition process or a coating process to form a mask material, followed by an etch back process.
Next, according to some embodiments, after forming the mask layer 109, the patterned mask 103 is removed, as shown in FIG. 10. During the removal of the patterning mask 103, the mask layer 109 covers the first gate electrode 108, so that the mask layer 109 may prevent the first gate electrode 108 from being damaged by the removal process of the patterning mask 103.
Next, according to some embodiments, as shown in fig. 11, after removing the patterned mask 103, the mask layer 109 is removed to expose the first gate electrode 108 and the insulating layer 106. According to some embodiments, a cleaning process may optionally be performed after removing the mask layer 109.
In accordance with some embodiments, as shown in fig. 12, an insulating layer 110 is formed on the epitaxial layer 102, the insulating layer 106, and the first gate electrode 108 by a deposition process. In some embodiments, insulating layer 110 extends from the top surface of epitaxial layer 102 into trench 104 and covers the sidewalls of epitaxial layer 102 as well as the top surfaces of insulating layer 106 and first gate electrode 108. In the present embodiment, the insulating layer 110 does not fill the trench 104. That is, after the insulating layer 110 is formed, there is a space above the insulating layer 110 in the trench 104. In some embodiments, the insulating layer 110 may be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high dielectric constant (high-k) dielectric materials, or combinations of the foregoing. In some embodiments, the material of the insulating layer 110 is different from the material of the first insulating layer 106. In some other embodiments, the material of the insulating layer 110 is the same as the material of the insulating layer 106. In the present embodiment, the deposition process is a compliant deposition process, and may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination thereof.
Next, according to some embodiments, a second gate electrode 111 is formed on the insulating layer 110 in the trench 104 by a deposition process, a lithographic patterning process and an etching process. In some embodiments, the second gate electrode 111 fills the space previously on the insulating layer 110 in the trench 104. In the present embodiment, the second gate electrode 111 is located on the first gate electrode 108, and the second gate electrode 111 is separated from the first gate electrode 108 by the insulating layer 110. In the present embodiment, the second gate electrode 111 vertically overlaps the first well 105. In some embodiments, as shown in fig. 12, the lateral width of the second gate electrode 111 is greater than the lateral width of the first gate electrode 108.
In some embodiments, the second gate electrode 111 may be one or more layers and formed of amorphous silicon, polysilicon, one or more metals, metal nitrides, metal silicides, conductive metal oxides, or combinations thereof. Specifically, the aforementioned metals may include, but are not limited to, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), or hafnium (Hf). The metal nitride may include, but is not limited to, molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The aforementioned metal silicide may include, but is not limited to, tungsten silicide (WSix). The aforementioned conductive metal oxide may include, but is not limited to, ruthenium metal oxide (RuO) 2 ) And Indium Tin Oxide (ITO). In some embodiments, the deposition process may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, lithographic patterningThe process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post exposure baking, photoresist developing, cleaning and drying (e.g., hard baking), other suitable processes, or a combination thereof. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
In the present embodiment, by disposing the first gate electrode 108 below the second gate electrode 111, the gate-drain capacitance (Cgd) at the bottom of the trench of the conventional super junction trench mosfet can be eliminated, and the gate-drain charge (Qgd) can be effectively reduced.
In addition, in the embodiment, the first well region 105 is disposed at the bottom of the trench 104 and below the first gate electrode 108 and the second gate electrode 111, so as to avoid a Junction Field Effect Transistor (JFET) effect of a conventional super junction power mosfet, and further effectively reduce an on-resistance (Rds).
According to some embodiments, an ion implantation process is performed to form a second well region 112 in the epitaxial layer 102, as shown in fig. 13. Next, another ion implantation process is performed to form a second heavily doped region 113 over the second well region 112. In some embodiments, the second well region 112 serves as a channel region of the semiconductor device 100, and the second heavily doped region 113 serves as a Source (S) of the semiconductor device 100. In the present embodiment, the second well region 112 and the second heavily doped region 113 surround the second gate electrode 111. In this embodiment, the second well region 112 is isolated from the first well region 105. In some embodiments, the bottom surface of the second well region 112 is higher than the top surface of the first gate electrode 108. That is, the interface between the second well region 112 and the epitaxial layer 102 is higher than the top surface of the first gate electrode 108.
In this embodiment, the second well region 112 and the first well region 105 have the same conductivity type, such as a second conductivity type. That is, in the present embodiment, the second well region 112 is p-type. In the present embodiment, the second heavily doped region 113 and the epitaxial layer 102 have the same conductivity type, for example, the first conductivity type. Also can be usedThat is, in the present embodiment, the second heavily doped region 113 is n-type. In some embodiments, the doping concentration of the second heavily doped region 113 is greater than that of the epitaxial layer 102. In some embodiments, the second well region 112 is doped at a concentration of about 1E16atoms/cm 3 To about 1E18atoms/cm 3 Within the range of (1). In some embodiments, the doping concentration of the second heavily doped region 113 is about 1E18atoms/cm 3 To about 1E21atoms/cm 3 In the presence of a surfactant.
In the present embodiment, since the second well region 112 is separated from the first well region 105, it is able to avoid the leakage of the first well region 105 due to high electric field impact ionization (ionization), and to directly introduce the breakdown current (avalanche current) into the second heavily doped region 113 as the source for discharging, thereby avoiding the problem of gate oxide charging/gate oxide injection (gate oxide charging/gate oxide injection) of the surrounding insulating layer 110 caused by the breakdown current entering the second well region 112 through the first well region 105, and further improving the gate oxide reliability. Furthermore, since the second well region 112 is isolated from the first well region 105, leakage can be avoided, and thus, a parasitic Bipolar Junction Transistor (BJT) can be prevented from being turned on due to leakage, thereby avoiding a problem of ruggedness (ruggedness) of an Unclamped Inductive Load (UIL).
Next, according to some embodiments, as shown in fig. 14, a dielectric layer 114 is formed on the second gate electrode 111 by a deposition process, a photolithography patterning process, and an etching process. In the present embodiment, the dielectric layer 114 covers the second gate electrode 111 and the insulating layer 110, and has an opening 114a exposing the second well 112 and the second heavily doped region 113.
In some embodiments, the dielectric layer 114 may be silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high dielectric constant (high-k) dielectric materials, or combinations of the foregoing. In some embodiments, the material of the dielectric layer 114 is different from the material of the insulating layer 110. In some other embodiments, the material of the dielectric layer 114 is the same as the material of the insulating layer 110. In some embodiments, the deposition process may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination of the foregoing. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or a combination of the foregoing. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
According to some embodiments, as shown in fig. 15, a contact 115 is formed in the opening 114a of the dielectric layer 114 by a deposition process, a lithographic patterning process, and an etching process. In some embodiments, the contact 115 extends through the dielectric layer 114 and the second heavily doped region 113, and extends into the second well region 112 to electrically connect to the second well region 112 and the second heavily doped region 113. In some embodiments, the contacts 115 may comprise copper, silver, gold, aluminum, tungsten, or combinations of the foregoing or other suitable conductive materials. In some embodiments, the deposition process may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination of the preceding. In some embodiments, the lithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination thereof.
According to some embodiments, as shown in FIG. 15, an ion implantation process may be performed to form contact doping regions 116 in the second well region 112 before forming the contacts 115. In some embodiments, the contact doped region 116 is located under the contact 115, and the contact doped region 116 and the second well region 112 have the same conductivity type, such as a second conductivity type. That is, in the present embodiment, the contact doping region 116 is p-type. In some embodiments, the doped concentration of the contact doping region 116 is about 1E19atoms/cm 3 To about 1E21atoms/cm 3 Within the range of (1).
In some embodiments, a barrier layer (not shown) may be formed between the contact 115 and the dielectric layer 114 by a deposition process, a photolithographic patterning process, and an etching process. In some embodiments, the barrier layer may comprise titanium nitride (TiN), aluminum oxide (Al) 2 O 3 ) Magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta) 2 O 5 ) Silicon dioxide (SiO) 2 ) Hafnium oxide (HfO) 2 ) Zirconium dioxide (ZrO) 2 ) Magnesium fluoride (MgF) 2 ) Calcium fluoride (CaF) 2 ) Or a combination of the foregoing.
According to some embodiments, as shown in fig. 15, after forming the contact 115, a metal layer 117 may be formed on the contact 115 by a deposition process. In some embodiments, metal layer 117 covers dielectric layer 114 and contact 115, and is electrically connected to contact 115. In some embodiments, the metal layer 117 may include copper, silver, gold, aluminum, tungsten, or combinations of the foregoing or other suitable conductive materials. In some embodiments, the material of the metal layer 117 is the same as the material of the contacts 115. In some other embodiments, the material of metal layer 117 is different from the material of contact 115. In some embodiments, the deposition process may be a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, other suitable processes, or a combination of the preceding. In some embodiments, after forming metal layer 117, the process of semiconductor device 100 is completed.
According to some embodiments of the present invention, by disposing the first well region under the bottom of the trench by an ion implantation process and a thermal drive-in process, a process cycle including epitaxy, implantation of a p-type dopant, and high temperature diffusion need not be performed a plurality of times. Therefore, the process for forming the first well region is simple, and expensive epitaxy cost is not required to be borne. Furthermore, since the first well region is located below the bottom of the trench, the first well region does not occupy additional space (e.g., space of the lateral epitaxial layer 102), so that the cell pitch can be reduced, and the channel resistance can be further reduced.
In addition, the first gate electrode, the first heavily doped region and the first well region can collectively serve as a reduced surface field (RESURF) region, thereby increasing the breakdown voltage of the semiconductor device, i.e., improving the voltage endurance capability of the semiconductor device. Moreover, compared to the resurf region formed by the ion implantation process, in the embodiment, the depth of the resurf region can be greatly increased by the first gate electrode, the first heavily doped region and the first well region, and the voltage endurance capability of the semiconductor device can be further greatly increased.
In addition, because the second well region is separated from the first well region, the first well region can be prevented from generating electric leakage due to impact ionization of a high electric field, the breakdown current can be directly led into the second heavily doped region serving as the source to be discharged, the problems of grid oxide charging/grid oxide charging injection are avoided, and the reliability of the grid oxide is further improved. Furthermore, since the second well region is isolated from the first well region, leakage can be avoided, and thus the parasitic bipolar junction field effect transistor (BJT) can be prevented from being turned on due to leakage, thereby avoiding the problem of ruggedness of the Unclamped Inductive Load (UIL).
The foregoing outlines features of a number of embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present disclosure. Those skilled in the art may readily devise many other varied processes and structures that are equally effective to achieve the same objects and/or achieve the same advantages of the embodiments of the invention. It should also be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments of the invention and that such equivalents are not to be excluded from the spirit and scope of the embodiments of the invention.

Claims (17)

1. A semiconductor device, comprising:
a substrate having a first conductivity type;
an epitaxial layer of the first conductivity type disposed on the substrate, the epitaxial layer having a trench therein;
a first well region disposed in the epitaxial layer and below the trench, and having a second conductivity type different from the first conductivity type;
a first gate electrode disposed in the trench and having the second conductivity type; and
a second gate electrode disposed in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer;
the doping concentration of the first grid electrode is greater than that of the first well region.
2. The semiconductor device of claim 1, wherein the first gate electrode and the second gate electrode vertically overlap the first well region.
3. The semiconductor device of claim 1, further comprising:
the first heavily doped region is arranged in the upper part of the first well region and has the second conduction type.
4. The semiconductor device of claim 3, wherein a doping concentration of the first heavily doped region is greater than a doping concentration of the first well region.
5. The semiconductor device of claim 1, further comprising:
a second insulating layer disposed between the first gate electrode and the epitaxial layer.
6. The semiconductor device of claim 1, further comprising:
a second well region surrounding the second gate electrode and having the second conductivity type.
7. The semiconductor device of claim 6, wherein the second well region is spaced apart from the first well region.
8. The semiconductor device of claim 6, further comprising:
and a second heavily doped region surrounding the second gate electrode and located above the second well region and having the first conductivity type.
9. The semiconductor device of claim 8, further comprising:
a dielectric layer disposed on the second gate electrode; and
a contact extending through the dielectric layer and electrically connected to the second well region and the second heavily doped region.
10. The semiconductor device of claim 9, further comprising:
a contact doped region disposed in the second well region and below the contact, and having the second conductivity type.
11. The semiconductor device of claim 9, further comprising:
a metal layer disposed on the contact and the dielectric layer; and
a barrier layer disposed between the contact and the dielectric layer.
12. A method of forming a semiconductor device, comprising:
providing a substrate with a first conductive type;
forming an epitaxial layer of the first conductivity type on the substrate;
forming a trench in the epitaxial layer;
forming a first well region of a second conductivity type in the epitaxial layer and below the trench, wherein the second conductivity type is different from the first conductivity type;
forming a first gate electrode having the second conductivity type in the trench; and
forming a second gate electrode in the trench and over the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer;
the doping concentration of the first grid electrode is greater than that of the first well region.
13. The method of forming a semiconductor device according to claim 12, wherein the step of forming the trench comprises:
forming a patterned mask with a first opening on the epitaxial layer; and
an etching process is performed on the epitaxial layer through the first opening.
14. The method of claim 13, wherein forming the first well region comprises:
and performing an ion implantation process and a thermal drive-in process on the trench by using the patterned mask as a protective mask.
15. The method of forming a semiconductor device according to claim 12, further comprising:
after the first well region is formed and before the first gate electrode is formed, an ion implantation process is performed to form a first heavily doped region having the second conductive type in an upper portion of the first well region.
16. The method of forming a semiconductor device according to claim 13, further comprising:
forming a mask layer over the first gate electrode in the trench after forming the first gate electrode and before forming the second gate electrode;
removing the patterned mask; and
the mask layer is removed.
17. The method of forming a semiconductor device of claim 12, further comprising:
forming a second well region of the second conductivity type surrounding the second gate electrode, and
a second heavily doped region of the first conductivity type is formed over the second well region, the second heavily doped region surrounding the second gate electrode.
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TW201423995A (en) * 2012-12-12 2014-06-16 Beyond Innovation Tech Co Ltd Trench gate MOSFET and method of forming the same

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