CN111697007A - Display panel and preparation method thereof - Google Patents
Display panel and preparation method thereof Download PDFInfo
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- CN111697007A CN111697007A CN202010513498.7A CN202010513498A CN111697007A CN 111697007 A CN111697007 A CN 111697007A CN 202010513498 A CN202010513498 A CN 202010513498A CN 111697007 A CN111697007 A CN 111697007A
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- metal layer
- layer
- metal
- drain electrode
- display panel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention provides a display panel, which adopts a wiring structure prepared by a three-layer metal structure, wherein the materials of a first metal layer and a third metal layer comprise molybdenum alloy materials, so that galvanic corrosion can be prevented. And the surface of the third metal layer forms an uneven surface, so that the roughness of the surface is increased, the visible light reflectivity can be reduced, the visual effect is improved, and the method is suitable for low-reflection high-order products.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
At present, the metal wiring of a large-size Thin Film Transistor (TFT) display panel mostly adopts a copper (Cu) process, and particularly, the number of copper wires of the current hot ultra-high definition display product with 8K resolution is very large; the reflectivity of a film formed by Cu preparation under visible light reaches 80%, the Cu film is not shielded above, and the visible light reaches the surface of the Cu film to cause reflection, so that the reflectivity of a product is high, the visual effect is influenced, and the requirement of a high-order product cannot be met.
Disclosure of Invention
A first object of the present invention is to provide a display panel capable of reducing the reflectance of the panel.
In order to achieve the above object, a display panel includes: a plurality of metal traces, wherein at least one metal trace includes: a first metal layer; the second metal layer is arranged on the first metal layer; the third metal layer is arranged on the second metal layer; and one side of the third metal layer, which is far away from the second metal layer, is provided with continuous bulges, and the bulges are used for forming an uneven surface on one side of the third metal layer, which is far away from the second metal layer.
Furthermore, the metal wirings form a source drain electrode wiring and a gate wiring.
Further, the display panel further includes: a substrate; the grid routing is arranged on the substrate; the grid insulation layer is arranged on the substrate and covers the grid routing; a semiconductor layer disposed on the gate insulating layer; the source drain electrode routing is arranged on the grid electrode insulating layer and connected with the semiconductor layer; and the passivation layer is arranged on the source drain electrode routing and the semiconductor layer.
Further, the materials of the first metal layer and the three metal layers comprise molybdenum alloy materials; the molybdenum alloy material comprises at least one of Ti, Ni, Ta and W.
Further, the material of the second metal layer includes copper.
Furthermore, the display panel further comprises a pixel electrode which is arranged on the passivation layer and connected with the source-drain electrode wiring.
Further, the source drain electrode trace comprises a source electrode trace and a drain electrode trace; the source wire and the drain wire are respectively arranged at two ends of the semiconductor layer.
Furthermore, the passivation layer is provided with a through hole, the through hole extends downwards to the surface of the source drain electrode wiring, and the pixel electrode is connected with the source drain electrode wiring through the through hole.
A second object of the present invention is to provide a method for preparing the display panel, comprising at least one step of: preparing at least one metal wire; the step of preparing at least one metal wire comprises: forming a metal wire, wherein the step of forming the metal wire specifically comprises: forming the first metal layer; forming the second metal layer on the first metal layer; forming the third metal layer on the second metal layer; and carrying out plasma treatment on the surface of the third metal layer on the side far away from the second metal layer to increase the roughness of the surface.
Further, the preparation method further comprises the following steps: providing a substrate; depositing the first metal layer, the second metal layer and the third metal layer on the substrate in sequence, and forming a gate wire after patterning; forming a gate insulating layer on the substrate and covering the gate wire; forming a semiconductor layer on the gate insulating layer; depositing the first metal layer, the second metal layer and the third metal layer on the gate insulating layer in sequence, and forming a source-drain electrode wire after patterning, wherein the source-drain electrode wire is connected with the semiconductor layer; and forming a passivation layer on the source drain electrode wiring and the semiconductor layer.
The invention has the beneficial effects that: the invention provides a display panel, wherein metal wires of the display panel are prepared from three layers of metals, and the materials of a first metal layer and a third metal layer comprise molybdenum alloy materials, so that galvanic corrosion can be prevented. And the surface of the third metal layer forms an uneven surface, so that the roughness of the surface is increased, the visible light reflectivity can be reduced, the visual effect is improved, and the method is suitable for low-reflection high-order products.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a metal trace provided in the present invention.
Fig. 2 is a schematic structural diagram of a display panel provided in the present invention.
Fig. 3 is a schematic structural view of the metal trace provided by the present invention performing plasma processing.
A display panel 100;
a metal trace 110; a first metal layer 111; a second metal layer 112;
a third metal layer 113; a projection 114; a source drain electrode trace 105;
a gate trace 102; a substrate 101; a gate insulating layer 103;
a semiconductor layer 104; a passivation layer 106; a pixel electrode 107;
a source line 1051; drain trace 1052; through hole 1061.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "integrated," "connected," and "connected" may be directly connected or indirectly connected through an intermediate, or may be a connection between two elements or an interaction relationship between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
As shown in fig. 1 and 2, the present invention provides a display panel 100, including: a number of metal traces 110.
At least one metal trace 110 is made of three layers of metal. For example, the at least one metal trace 110 has: a first metal layer 111, a second metal layer 112, and a third metal layer 113.
In the present embodiment, each metal trace 110 is made of three layers of metal. That is, each metal trace 110 has a first metal layer 111, a second metal layer 112, and a third metal layer 113.
The first metal layer 111 includes a molybdenum alloy material further including at least one metal element of Ti, Ni, Ta, and W.
The second metal layer 112 is disposed on the first metal layer 111. The material of the second metal layer 112 includes copper.
The third metal layer 113 is disposed on the second metal layer 112; the material of the third metal layer 113 includes a molybdenum alloy material, and the molybdenum alloy material further includes at least one metal element of Ti, Ni, Ta, and W.
The wiring structure is prepared by adopting a three-layer metal structure, and the materials of the first metal layer 111 and the third metal layer 113 comprise molybdenum alloy materials, so that galvanic corrosion can be prevented.
The side of the third metal layer 113 away from the second metal layer 112 has a continuous protrusion 114, and the protrusion 114 is used to form an uneven surface on the side of the third metal layer 113 away from the second metal layer 112.
The surface of the third metal layer 113 (i.e. the surface on the light incident side) is formed into an uneven surface, so that the roughness of the surface is increased, the visible light reflectivity can be reduced (by 10% at least), the visual effect is improved, and the method is suitable for low-reflection high-order products.
As shown in fig. 2, the metal trace 110 includes a source-drain electrode trace 105 and a gate trace 102, and of course, the metal trace 110 further includes a scan line and a data line.
With continued reference to fig. 2, in an embodiment, the display panel 100 further includes: a substrate 101, a gate insulating layer 103, a semiconductor layer 104, a passivation layer 106, and a pixel electrode 107.
The gate trace 102 is disposed on the substrate 101. The gate insulating layer 103 is disposed on the substrate 101 and covers the gate trace 102.
The semiconductor layer 104 is provided on the gate insulating layer 103.
The source-drain electrode trace 105 is disposed on the gate insulating layer 103 and connected to the semiconductor layer 104. The source drain electrode trace 105 includes a source trace 1051 and a drain trace 1052;
the source trace 1051 and the drain trace 1052 are disposed at two ends of the semiconductor layer 104, respectively.
The passivation layer 106 is disposed on the source/drain electrode trace 105 and the semiconductor layer 104.
And the pixel electrode 107 is arranged on the passivation layer 106 and connected with the source drain electrode routing 105.
The passivation layer 106 is provided with a through hole 1061, the through hole 1061 extends downward to the surface of the source/drain electrode trace 105, the pixel electrode 107 is connected to the source/drain electrode trace 105 through the through hole 1061, and specifically, the pixel electrode 107 is connected to the second metal layer 112 of the source/drain electrode trace 105.
The present invention also provides a manufacturing method for manufacturing the display panel 100, including at least one step, such as: at least one metal trace 110 is prepared.
The step of preparing the at least one metal trace 110 specifically includes the following steps:
as shown in fig. 3, the first metal layer 111 is formed. The material of the first metal layer 111 comprises a molybdenum alloy material; the molybdenum alloy material comprises at least one of Ti, Ni, Ta and W.
The second metal layer 112 is formed on the first metal layer 111. The material of the second metal layer 112 includes copper.
The third metal layer 113 is formed on the second metal layer 112. The material of the third metal layer 113 includes a molybdenum alloy material; the molybdenum alloy material comprises at least one of Ti, Ni, Ta and W.
And performing plasma (Heplasma or Ar plasma) treatment on the surface of the third metal layer 113 on the side far away from the second metal layer 112 to increase the surface roughness, so as to form the uneven surface structure shown in fig. 1. So that the reflectivity of the light incident surface of the third metal layer 113 is reduced to 10% at least;
in one embodiment, the preparation method further comprises the following steps.
Providing a substrate 101;
depositing the first metal layer 111, the second metal layer 112 and the third metal layer 113 on the substrate 101 in sequence, and forming a gate trace 102 after patterning, wherein the thickness of the gate trace 102 is 100-1000 angstroms;
forming a gate insulating layer 103 on the substrate 101 and covering the gate trace 102; specifically, the gate insulating layer 103 is formed by depositing an insulating material on the substrate 101, and the gate insulating layer 103 covers the gate trace 102;
forming a semiconductor layer 104 on the gate insulating layer 103; specifically, a semiconductor layer 104 is formed by depositing a semiconductor material on the gate insulating layer 103 and patterning the semiconductor material;
depositing the first metal layer 111, the second metal layer 112, and the third metal layer 113 on the gate insulating layer 103 in sequence, and forming a source/drain electrode trace 105 after patterning, where the source/drain electrode trace 105 is connected to the semiconductor layer 104; and
a passivation layer 106 is formed on the source/drain electrode trace 105 and the semiconductor layer 104. Specifically, the passivation layer 106 is formed by depositing an insulating material on the substrate 101, and the passivation layer 106 covers the source/drain trace and the semiconductor layer 104.
The preparation method further comprises the following steps:
a through hole 1061 is formed in the passivation layer 106, and the through hole 1061 extends downward to the surface of the source/drain electrode trace 105; and
depositing an indium tin oxide material on the passivation layer 106 to obtain the pixel electrode 107 by patterning, wherein the pixel electrode 107 is connected to the source/drain electrode trace 105 through the through hole 1061.
The present invention has been described in detail, and the principle and the implementation of the present invention are explained by applying specific examples, and the description of the above examples is only used to help understanding the technical scheme and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A display panel, comprising: a plurality of metal traces, wherein at least one metal trace has:
a first metal layer; and
the second metal layer is arranged on the first metal layer;
the third metal layer is arranged on the second metal layer;
and one side of the third metal layer, which is far away from the second metal layer, is provided with continuous bulges, and the bulges are used for forming an uneven surface on one side of the third metal layer, which is far away from the second metal layer.
2. The display panel of claim 1,
the metal wires comprise source drain electrode wires and grid electrode wires.
3. The display panel of claim 2, further comprising:
a substrate;
the grid routing is arranged on the substrate;
the grid insulation layer is arranged on the substrate and covers the grid routing;
a semiconductor layer disposed on the gate insulating layer;
the source drain electrode routing is arranged on the grid electrode insulating layer and connected with the semiconductor layer;
and the passivation layer is arranged on the source drain electrode routing and the semiconductor layer.
4. The display panel of claim 1,
the materials of the first metal layer and the third metal layer comprise molybdenum alloy materials;
the molybdenum alloy material also comprises at least one metal element of Ti, Ni, Ta and W.
5. The display panel of claim 1,
the material of the second metal layer comprises copper.
6. The display panel of claim 3, further comprising
And the pixel electrode is arranged on the passivation layer and is connected with the source drain electrode wiring.
7. The display panel of claim 3,
the source drain electrode routing comprises a source electrode routing and a drain electrode routing;
the source wire and the drain wire are respectively arranged at two ends of the semiconductor layer.
8. The display panel of claim 6,
the passivation layer is provided with a through hole, the through hole extends downwards to the surface of the source drain electrode wiring, and the pixel electrode is connected with the source drain electrode wiring through the through hole.
9. A method for manufacturing a display panel according to claim 1, comprising at least one step of: preparing at least one metal wire;
the step of preparing at least one metal wire comprises:
forming the first metal layer;
forming the second metal layer on the first metal layer;
forming the third metal layer on the second metal layer; and
and carrying out plasma treatment on the surface of one side of the third metal layer, which is far away from the second metal layer, so as to increase the surface roughness.
10. The method of claim 9, further comprising:
providing a substrate;
depositing the first metal layer, the second metal layer and the third metal layer on the substrate in sequence, and forming a gate wire after patterning;
forming a gate insulating layer on the substrate and covering the gate wire;
forming a semiconductor layer on the gate insulating layer;
depositing the first metal layer, the second metal layer and the third metal layer on the gate insulating layer in sequence, and forming a source-drain electrode wire after patterning, wherein the source-drain electrode wire is connected with the semiconductor layer;
and forming a passivation layer on the source drain electrode wiring and the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513498.7A CN111697007A (en) | 2020-06-08 | 2020-06-08 | Display panel and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010513498.7A CN111697007A (en) | 2020-06-08 | 2020-06-08 | Display panel and preparation method thereof |
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| CN111697007A true CN111697007A (en) | 2020-09-22 |
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| CN202010513498.7A Pending CN111697007A (en) | 2020-06-08 | 2020-06-08 | Display panel and preparation method thereof |
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Citations (7)
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| JP2003241222A (en) * | 2002-02-15 | 2003-08-27 | Matsushita Electric Ind Co Ltd | Reflection type liquid crystal display device |
| JP2004013176A (en) * | 2003-10-03 | 2004-01-15 | Mitsubishi Electric Corp | Reflection type liquid crystal display device |
| CN1716637A (en) * | 2004-06-30 | 2006-01-04 | 三星Sdi株式会社 | Thin film transistor (TFT) and flat panel display including the tft and their methods of manufacture |
| CN104681567A (en) * | 2013-12-02 | 2015-06-03 | 乐金显示有限公司 | Thin Film Transistor Substrate Having Metal Oxide Semiconductor And Manufacturing Method Thereof |
| CN106229344A (en) * | 2016-08-19 | 2016-12-14 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), its preparation method and display device |
| CN110854069A (en) * | 2019-10-31 | 2020-02-28 | 深圳市华星光电半导体显示技术有限公司 | Preparation method of array substrate and array substrate |
| CN111081766A (en) * | 2019-12-13 | 2020-04-28 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
-
2020
- 2020-06-08 CN CN202010513498.7A patent/CN111697007A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003241222A (en) * | 2002-02-15 | 2003-08-27 | Matsushita Electric Ind Co Ltd | Reflection type liquid crystal display device |
| JP2004013176A (en) * | 2003-10-03 | 2004-01-15 | Mitsubishi Electric Corp | Reflection type liquid crystal display device |
| CN1716637A (en) * | 2004-06-30 | 2006-01-04 | 三星Sdi株式会社 | Thin film transistor (TFT) and flat panel display including the tft and their methods of manufacture |
| CN104681567A (en) * | 2013-12-02 | 2015-06-03 | 乐金显示有限公司 | Thin Film Transistor Substrate Having Metal Oxide Semiconductor And Manufacturing Method Thereof |
| CN106229344A (en) * | 2016-08-19 | 2016-12-14 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), its preparation method and display device |
| CN110854069A (en) * | 2019-10-31 | 2020-02-28 | 深圳市华星光电半导体显示技术有限公司 | Preparation method of array substrate and array substrate |
| CN111081766A (en) * | 2019-12-13 | 2020-04-28 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
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