CN111696462A

CN111696462A - Output buffer and operation method thereof

Info

Publication number: CN111696462A
Application number: CN201910192183.4A
Authority: CN
Inventors: 钱佳驹
Original assignee: Himax Technologies Ltd
Current assignee: Himax Technologies Ltd
Priority date: 2019-03-14
Filing date: 2019-03-14
Publication date: 2020-09-22
Anticipated expiration: 2039-03-14
Also published as: CN111696462B

Abstract

An output buffer and a method of operating the same. The output buffer includes an input stage circuit, an output stage circuit, a rise control circuit, and a fall control circuit. The input stage circuit correspondingly generates a first gating voltage and a second gating voltage according to the input voltage of the output buffer. The output stage circuit generates an output voltage of the output buffer according to the first gate control voltage and the second gate control voltage. When the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage during the first transient period. When the output voltage is to be pulled down, the fall control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

Description

Output buffer and operation method thereof

Technical Field

The present invention relates to an electronic circuit, and more particularly, to an output buffer and a method for operating the same.

Background

Generally, a source driver is configured with an output buffer. In the source driver, the output buffer can output the analog voltage gain of the digital-to-analog converter to the data line (or called source line) of the display panel. As the resolution and/or Frame rate (Frame rate) of the display panel is higher, the charging time for one scan line is shorter. In order to drive (charge or discharge) one pixel (pixel) in a short time, the output buffer needs a sufficiently high driving capability. That is, the output buffer needs to have a sufficiently high Slew Rate (Slew Rate). In order to increase slew rate, tail current (tail current) of the known output buffer is increased. An increase in the tail current means an increase in power consumption.

Disclosure of Invention

The invention provides an output buffer and an operation method thereof, which are used for improving the slew rate of an output voltage.

An embodiment of the invention provides an output buffer. The output buffer includes an input stage circuit, an output stage circuit, a rise control circuit, and a fall control circuit. The input stage circuit is configured to receive an input voltage of the output buffer. The input stage circuit correspondingly generates a first gate control voltage and a second gate control voltage according to the input voltage. The output stage circuit is coupled to the input stage circuit to receive the first gate control voltage and the second gate control voltage. The output stage circuit is configured to generate an output voltage of the output buffer according to the first gate voltage and the second gate voltage. The rise control circuit is configured to compare the input voltage and the output voltage to obtain a first comparison result. When the first comparison result indicates that the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage during a first transient period. The droop control circuit is configured to compare the input voltage and the output voltage to obtain a second comparison result. When the second comparison result indicates that the output voltage is to be pulled down, the droop control circuit pulls up the first gating voltage and the second gating voltage during the second transient period.

An embodiment of the present invention provides a method for operating an output buffer. The operation method comprises the following steps: the input stage circuit correspondingly generates a first gating voltage and a second gating voltage according to the input voltage of the output buffer; the output stage circuit correspondingly generates the output voltage of the output buffer according to the first gate control voltage and the second gate control voltage; comparing the input voltage with the output voltage by the rise control circuit to obtain a first comparison result; when the first comparison result indicates that the output voltage is to be pulled up, the rising control circuit pulls down the first gating voltage and the second gating voltage in a first transient period; comparing the input voltage with the output voltage by the droop control circuit to obtain a second comparison result; and pulling up the first gating voltage and the second gating voltage by the droop control circuit during a second transient period when the second comparison result indicates that the output voltage is to be pulled down.

Based on the above, the output buffer and the operation method thereof according to the embodiments of the present invention can compare the input voltage with the output voltage. When the output voltage is to be pulled up, the first gate control voltage and the second gate control voltage of the output stage circuit of the output buffer are pulled down so as to improve the slew rate of the output voltage. When the output voltage is to be pulled down, the first gate control voltage and the second gate control voltage of the output stage circuit of the output buffer are pulled up so as to improve the slew rate of the output voltage.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram of a circuit block (circuit block) of an output buffer according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating an operation method of an output buffer according to an embodiment of the invention.

FIG. 3 is a block diagram illustrating the rise control circuit of FIG. 1 according to one embodiment of the present invention.

FIG. 4 is a block diagram of a rise control circuit shown in FIG. 1 according to another embodiment of the present invention.

Fig. 5 is a circuit block diagram illustrating the droop control circuit of fig. 1 according to an embodiment of the present invention.

Fig. 6 is a circuit block diagram illustrating the droop control circuit of fig. 1 according to another embodiment of the present invention.

[ description of reference ]

100: output buffer

110: input stage circuit

120: output stage circuit

130: rise control circuit

131: comparison circuit

140: droop control circuit

141: comparison circuit

310. 510: current mirror

EN, ENB: control signal

N1-N12, P1-P12: transistor with a metal gate electrode

NGATE, PGATE: gated voltage

S210 to S270: step (ii) of

VC1, VC 2: control voltage

VDDA: system voltage

VIN: input voltage

VOUT: output voltage

VSSA: reference voltage

Detailed Description

The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, elements/components/steps with the same reference numbers in the drawings and the description represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may be referred to one another in relation to the description.

Fig. 1 is a schematic diagram of a circuit block (circuit block) of an output buffer 100 according to an embodiment of the invention. The first input terminal of the output buffer 100 receives an input voltage VIN from a previous stage circuit (not shown), and the output terminal of the output buffer 100 outputs an output voltage VOUT to a next stage circuit (not shown). In the embodiment shown in fig. 1, the output voltage VOUT of the output buffer 100 is fed back to the second input terminal of the output buffer 100. According to design requirements, in other embodiments, the output terminal of the output buffer 100 may be coupled to the second input terminal of the output buffer 100 through other elements/circuits (not shown), or the output terminal of the output buffer 100 is not coupled to the second input terminal of the output buffer 100.

In the embodiment shown in fig. 1, the output buffer 100 includes an input stage circuit 110, an output stage circuit 120, a rise control circuit 130, and a fall control circuit 140. The input stage circuit 110 may include a differential input pair, a gain circuit, and/or other input stage circuits according to design requirements. For example, the input stage circuit 110 may be an input stage circuit of a conventional operational amplifier or an input stage circuit of another amplifier and/or a gain stage circuit. A first input terminal of the input stage circuit 110 is coupled to a first input terminal of the output buffer 100 so as to receive the input voltage VIN. A second input terminal of the input stage circuit 110 is coupled to a second input terminal of the output buffer 100 for receiving the output voltage VOUT. The input stage circuit 110 can generate a gate voltage PGATE and a gate voltage NGATE according to the input voltage VIN.

A first input terminal of the output stage circuit 120 is coupled to a first output terminal of the input stage circuit 110 for receiving the gate control voltage PGATE. A second input terminal of the output stage circuit 120 is coupled to a second output terminal of the input stage circuit 110 for receiving the gating voltage NGATE. An output terminal of the output stage circuit 120 is coupled to an output terminal of the output buffer 100. The output stage circuit 120 can correspondingly generate the output voltage VOUT of the output buffer 100 according to the gate control voltage PGATE and the gate control voltage NGATE.

In the embodiment shown in FIG. 1, the output stage 120 includes a transistor P1 and a transistor N1. The control terminal (e.g., gate) of the transistor P1 is coupled to the first output terminal of the input stage circuit 110 for receiving the gate control voltage PGATE. A first terminal (e.g., source) of the transistor P1 is coupled to the system voltage VDDA. The level of system voltage VDDA may be determined according to design requirements. A second terminal (e.g., a drain) of the transistor P1 is coupled to an output terminal of the output stage circuit 120, wherein the output terminal of the output stage circuit 120 outputs the output voltage VOUT. The control terminal (e.g., gate) of the transistor N1 is coupled to the second output terminal of the input stage circuit 110 for receiving the gate control voltage NGATE. A first terminal (e.g., source) of the transistor N1 is coupled to the reference voltage VSSA. The level of the reference voltage VSSA may be determined according to design requirements. A second terminal (e.g., a drain) of the transistor N1 is coupled to the output terminal of the output stage circuit 120 and a second terminal of the transistor P1.

The output stage 120 shown in fig. 1 is an example. In any event, the implementation of the output stage circuit 120 should not be limited to the embodiment shown in fig. 1. The output stage circuit 120 may include any type of output circuit according to design requirements. For example, in other embodiments, the output stage circuit 120 may be an output stage circuit of a known operational amplifier or an output stage circuit of another amplifier.

Fig. 2 is a flowchart illustrating an operation method of an output buffer according to an embodiment of the invention. Please refer to fig. 1 and fig. 2. In step S210, the input stage circuit 110 correspondingly generates a gate voltage PGATE and a gate voltage NGATE according to the input voltage VIN of the output buffer 100. In step S220, the output stage circuit 120 correspondingly generates the output voltage VOUT of the output buffer 100 according to the gate control voltage PGATE and the gate control voltage NGATE. In step S230, the up control circuit 130 compares the input voltage VIN with the output voltage VOUT to obtain a first comparison result, and the down control circuit 140 compares the input voltage VIN with the output voltage VOUT to obtain a second comparison result.

When the first comparison result indicates that the output voltage VOUT is to be pulled up (step S240, "to be pulled up"), the rise control circuit 130 may pull down the gate voltage PGATE and the gate voltage NGATE during the transient period (step S250). When the pull-up control circuit 130 pulls down the gate voltage NGATE, the off state of the transistor N1 can be ensured to avoid the occurrence of short circuit current. When the rising control circuit 130 pulls down the gate control voltage PGATE, the current flowing through the transistor P1 can be temporarily increased to speed up the pull-up of the output voltage VOUT. Therefore, the Slew Rate (Slew Rate) of the output voltage VOUT can be raised.

Depending on design requirements, step S250 may include the following operations in some embodiments. When the input voltage VIN is greater than the output voltage VOUT, the rise control circuit 130 may pull down the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is less than or equal to the output voltage VOUT, the rise control circuit 130 may not adjust the gate voltage PGATE and the gate voltage NGATE.

When the first comparison result and the second comparison result both indicate that the output voltage VOUT is not changed ("no change" in step S240), the rise control circuit 130 and the fall control circuit 140 may not adjust the gate voltage PGATE and the gate voltage NGATE (step S260). In the case where the rising control circuit 130 and the falling control circuit 140 do not interfere with the gate voltage PGATE and the gate voltage NGATE, the level of the gate voltage PGATE and the level of the gate voltage NGATE are determined by the input stage circuit 110.

When the second comparison result indicates that VOUT is to be pulled down ("to be pulled down" in step S240), the droop control circuit 140 may pull up the gate voltage PGATE and the gate voltage NGATE during the transient period (step S270). When the falling control circuit 140 pulls up the gate control voltage PGATE, the off state of the transistor P1 can be ensured to avoid the occurrence of short circuit current. When the droop control circuit 140 pulls the pull-up gate voltage NGATE, the current through the transistor N1 may be temporarily increased to speed up the pull-down output voltage VOUT. Therefore, the slew rate of the output voltage VOUT can be raised.

Depending on design requirements, step S270 may include the following operations in some embodiments. When the input voltage VIN is smaller than the output voltage VOUT, the droop control circuit 140 may pull up the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is greater than or equal to the output voltage VOUT, the droop control circuit 140 may not adjust the gate voltage PGATE and the gate voltage NGATE.

Depending on different design requirements, the above-mentioned blocks of the rising control circuit 130 and/or the falling control circuit 140 may be implemented in hardware (hardware), firmware (firmware), software (software, i.e. program), or a combination of multiple of the foregoing. In terms of hardware, the blocks of the rise control circuit 130 and/or the fall control circuit 140 may be implemented as logic circuits on an integrated circuit (integrated circuit). The related functions of the rising control circuit 130 and/or the falling control circuit 140 may be implemented as hardware by using a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the rise control circuit 130 and/or the fall control circuit 140 may be implemented in various logic blocks, modules and circuits of one or more controllers, microcontrollers, microprocessors, Application-specific integrated circuits (ASICs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and/or other processing units.

Fig. 3 is a block diagram illustrating the rise control circuit 130 shown in fig. 1 according to an embodiment of the invention. In the embodiment shown in FIG. 3, the rising control circuit 130 includes a comparison circuit 131, a transistor N2 and a transistor N3. The comparison circuit 131 may compare the input voltage VIN with the output voltage VOUT to generate the control voltage VC1 as the first comparison result. The control terminal (e.g., gate) of the transistor N2 is coupled to the output terminal of the comparison circuit 131 for receiving the control voltage VC 1. A first terminal (e.g., source) of the transistor N2 is coupled to the reference voltage VSSA. A second terminal (e.g., a drain) of the transistor N2 is coupled to the first input terminal of the output stage circuit 120 for receiving the gate control voltage PGATE. The control terminal (e.g., gate) of the transistor N3 is coupled to the output terminal of the comparison circuit 131 for receiving the control voltage VC 1. A first terminal (e.g., source) of the transistor N3 is coupled to the reference voltage VSSA. A second terminal (e.g., a drain) of the transistor N3 is coupled to a second input terminal of the output stage circuit 120 for receiving the gate control voltage NGATE.

When the input voltage VIN is greater than the output voltage VOUT, the comparison circuit 131 can turn on (turn on) the transistor N2 and the transistor N3 by the control voltage VC1 to pull down the gate control voltage PGATE and the gate control voltage NGATE. When the input voltage VIN is less than or equal to the output voltage VOUT, the comparing circuit 131 can turn off (turn off) the transistor N2 and the transistor N3 by the control voltage VC1, so that the rise control circuit 130 can not interfere (adjust) the gate voltage PGATE and the gate voltage NGATE.

In the embodiment shown in FIG. 3, the comparison circuit 131 includes a transistor N4, a transistor N5, and a current mirror 310. The control terminal (e.g., gate) of the transistor N4 is coupled to the input voltage VIN. A first terminal (e.g., source) of the transistor N4 is coupled to the output voltage VOUT. The main current terminal of the current mirror 310 is coupled to a second terminal (e.g., drain) of the transistor N4. The current mirror 310 is coupled from the current terminal to the output terminal of the comparison circuit 131, wherein the output terminal of the comparison circuit 131 can provide the control voltage VC1 to the transistor N2 and the transistor N3. The control terminal (e.g., gate) of the transistor N5 is coupled to the output terminal of the comparison circuit 131. A first terminal (e.g., source) of the transistor N5 is coupled to the reference voltage VSSA. A second terminal (e.g., a drain) of the transistor N5 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N5.

In the embodiment shown in FIG. 3, the current mirror 310 includes a transistor P2 and a transistor P3. A first terminal (e.g., source) of the transistor P2 is coupled to the system voltage VDDA. A second terminal (e.g., drain) and a control terminal (e.g., gate) of the transistor P2 are coupled to the main current terminal of the current mirror 310. A first terminal (e.g., source) of the transistor P3 is coupled to the system voltage VDDA. A second terminal (e.g., drain) of the transistor P3 is coupled to the slave current terminal of the current mirror 310. The control terminal (e.g., gate) of the transistor P3 is coupled to the control terminal of the transistor P2.

Fig. 4 is a circuit block diagram illustrating the rise control circuit 130 shown in fig. 1 according to another embodiment of the invention. In the embodiment shown in FIG. 4, the rise control circuit 130 includes a comparison circuit 132, a transistor N2 and a transistor N3. The comparison circuit 132, the transistor N2 and the transistor N3 shown in fig. 4 can be analogized from the related descriptions of the comparison circuit 131, the transistor N2 and the transistor N3 shown in fig. 3, and thus are not described again.

In the embodiment shown in FIG. 4, the comparison circuit 132 includes a transistor N6, a transistor N7, a transistor N8, a transistor N9, a transistor P4, and a current mirror 310. The control terminal (e.g., gate) of the transistor N6 is coupled to the input voltage VIN. A first terminal (e.g., source) of the transistor N6 is coupled to the output voltage VOUT. The control terminal (e.g., gate) of the transistor N7 is controlled by the control signal EN. A first terminal (e.g., source) of the transistor N7 is coupled to a second terminal (e.g., drain) of the transistor N6.

The main current terminal of the current mirror 310 is coupled to a second terminal (e.g., drain) of the transistor N7. The current mirror 310 is coupled from the current terminal to the output terminal of the comparison circuit 132, wherein the output terminal of the comparison circuit 132 can provide the control voltage VC1 to the transistor N2 and the transistor N3. The current mirror 310 shown in fig. 4 can be analogized with reference to the related description of the current mirror 310 shown in fig. 3, and therefore, the description thereof is omitted.

The control terminal (e.g., gate) of the transistor P4 is controlled by the control signal EN. A first terminal (e.g., source) of the transistor P4 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P4 is coupled to the enable terminal of the current mirror 310. That is, the second terminal of the transistor P4 is coupled to the control terminal of the transistor P2 and the control terminal of the transistor P3. A control terminal (e.g., gate) of the transistor N8 is coupled to the output terminal of the comparison circuit 132. A first terminal (e.g., source) of the transistor N8 is coupled to the reference voltage VSSA. A second terminal (e.g., a drain) of the transistor N8 is coupled to the slave current terminal of the current mirror 310 and the control terminal of the transistor N8. The control terminal (e.g., gate) of the transistor N9 is controlled by the control signal ENB. The control signal ENB is an inverted signal of the control signal EN. A first terminal (e.g., source) of the transistor N9 is coupled to the reference voltage VSSA. A second terminal (e.g., a drain) of the transistor N9 is coupled to a control terminal of the transistor N8.

When the control signal EN is at a high voltage level (e.g., the level of the system voltage VDDA or other levels), i.e., when the control signal ENB is at a low voltage level (e.g., the level of the reference voltage VSSA or other levels), the transistor N7 is turned on (turn on), and the transistors P4 and N9 are turned off (turn off), the operation of the comparison circuit 132 shown in fig. 4 is similar to that of the comparison circuit 131 shown in fig. 3. When the control signal EN is at a low voltage level (i.e., the control signal ENB is at a high voltage level), the transistor N7 is turned off, and the transistors P4 and N9 are turned on, so that the comparator 132 shown in FIG. 4 is disabled (disable), and the control voltage VC1 is pulled down to a low voltage level. When the control voltage VC1 is pulled down to the low voltage level, the transistors N2 and N3 are turned off (turn off). Therefore, when the control signal EN (control signal ENB) disables the rise control circuit 130, the rise control circuit 130 may not interfere (adjust) the gate voltage PGATE and the gate voltage NGATE.

In some applications, after the output voltage VOUT is pulled down, the output voltage VOUT may be lower (smaller) than the input voltage VIN for a certain period, and then the level of the output voltage VOUT is returned to be consistent with the input voltage VIN after the certain period is over. Generally, the specific period is short. The rise control circuit 130 may be disabled during the specific period and enabled outside the specific period by control of the control signal EN (control signal ENB). Therefore, malfunction of the rise control circuit 130 in the specific period can be avoided.

Fig. 5 is a block diagram illustrating the droop control circuit 140 of fig. 1 according to an embodiment of the present invention. In the embodiment shown in FIG. 5, the droop control circuit 140 includes a comparison circuit 141, a transistor P5 and a transistor P6. The comparison circuit 141 may compare the input voltage VIN with the output voltage VOUT to generate the control voltage VC2 as the second comparison result. The control terminal (e.g., gate) of the transistor P5 is coupled to the output terminal of the comparison circuit 141 for receiving the control voltage VC 2. A first terminal (e.g., source) of the transistor P5 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P5 is coupled to the first input terminal of the output stage circuit 120 for receiving the gate control voltage PGATE. The control terminal (e.g., gate) of the transistor P6 is coupled to the output terminal of the comparison circuit 141 for receiving the control voltage VC 2. A first terminal (e.g., source) of the transistor P6 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P6 is coupled to the second input terminal of the output stage circuit 120 for receiving the gate control voltage NGATE.

When the input voltage VIN is smaller than the output voltage VOUT, the comparing circuit 141 turns on (turn on) the transistor P5 and the transistor P6 by the control voltage VC2 to pull up the gate voltage PGATE and the gate voltage NGATE. When the input voltage VIN is greater than or equal to the output voltage VOUT, the comparing circuit 141 can turn off (turn off) the transistor P5 and the transistor P6 by the control voltage VC2, so that the droop control circuit 140 can not interfere (adjust) the gate voltage PGATE and the gate voltage NGATE.

In the embodiment shown in FIG. 5, the comparison circuit 141 includes a transistor P7, a transistor P8, and a current mirror 510. The control terminal (e.g., gate) of the transistor P7 is coupled to the input voltage VIN. A first terminal (e.g., source) of the transistor P7 is coupled to the output voltage VOUT. The main current terminal of the current mirror 510 is coupled to a second terminal (e.g., drain) of the transistor P7. The current mirror 510 is coupled from the current terminal to the output terminal of the comparison circuit 141, wherein the output terminal of the comparison circuit 141 can provide the control voltage VC2 to the transistor P5 and the transistor P6. The control terminal (e.g., gate) of the transistor P8 is coupled to the output terminal of the comparison circuit 141. A first terminal (e.g., source) of the transistor P8 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P8 is coupled to the slave terminal of the current mirror 510 and the control terminal of the transistor P8.

In the embodiment shown in FIG. 5, the current mirror 510 includes a transistor N10 and a transistor N11. A first terminal (e.g., source) of the transistor N10 is coupled to the reference voltage VSSA. A second terminal (e.g., drain) and a control terminal (e.g., gate) of the transistor N10 are coupled to the main current terminal of the current mirror 510. A first terminal (e.g., source) of the transistor N11 is coupled to the reference voltage VSSA. A second terminal (e.g., drain) of transistor N11 is coupled to the slave current terminal of current mirror 510. The control terminal (e.g., gate) of the transistor N11 is coupled to the control terminal of the transistor N10.

Fig. 6 is a circuit block diagram illustrating the droop control circuit 140 of fig. 1 according to another embodiment of the present invention. In the embodiment shown in FIG. 6, the droop control circuit 140 includes a comparison circuit 142, a transistor P5 and a transistor P6. The comparison circuit 142, the transistor P5 and the transistor P6 shown in FIG. 6 can be analogized from the related descriptions of the comparison circuit 141, the transistor P5 and the transistor P6 shown in FIG. 5, and therefore, the description thereof is omitted.

In the embodiment shown in FIG. 6, the comparison circuit 142 includes a transistor P9, a transistor P10, a transistor P11, a transistor P12, a transistor N12, and a current mirror 510. The control terminal (e.g., gate) of the transistor P9 is coupled to the input voltage VIN. A first terminal (e.g., source) of the transistor P9 is coupled to the output voltage VOUT. The control terminal (e.g., gate) of the transistor P10 is controlled by the control signal ENB. A first terminal (e.g., source) of the transistor P10 is coupled to a second terminal (e.g., drain) of the transistor P9.

The main current terminal of the current mirror 510 is coupled to a second terminal (e.g., drain) of the transistor P10. The current mirror 510 is coupled from the current terminal to the output terminal of the comparison circuit 142, wherein the output terminal of the comparison circuit 142 can provide the control voltage VC2 to the transistor P5 and the transistor P6. The current mirror 510 shown in fig. 6 can be analogized with reference to the related description of the current mirror 510 shown in fig. 5, and thus, the description thereof is omitted.

The control terminal (e.g., gate) of the transistor N12 is controlled by the control signal ENB. A first terminal (e.g., source) of the transistor N12 is coupled to the reference voltage VSSA. A second terminal (e.g., drain) of the transistor N12 is coupled to the enable terminal of the current mirror 510. That is, the second terminal of the transistor N12 is coupled to the control terminal of the transistor N10 and the control terminal of the transistor N11. A control terminal (e.g., gate) of the transistor P11 is coupled to the output terminal of the comparison circuit 142. A first terminal (e.g., source) of the transistor P11 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P11 is coupled to the slave terminal of the current mirror 510 and the control terminal of the transistor P11. The control terminal (e.g., gate) of the transistor P12 is controlled by the control signal EN. The control signal EN is an inverted signal of the control signal ENB. A first terminal (e.g., source) of the transistor P12 is coupled to the system voltage VDDA. A second terminal (e.g., a drain) of the transistor P12 is coupled to a control terminal of the transistor P11.

When the control signal EN is at a high voltage level (e.g., the level of the system voltage VDDA or other levels), i.e., when the control signal ENB is at a low voltage level (e.g., the level of the reference voltage VSSA or other levels), the transistor P10 is turned on (turn on), and the transistors N12 and P12 are turned off (turn off), the operation of the comparison circuit 142 shown in fig. 6 is similar to that of the comparison circuit 141 shown in fig. 5. When the control signal EN is at a low voltage level (i.e., the control signal ENB is at a high voltage level), the transistor P10 is turned off, the transistor N12 and the transistor P12 are turned on, the comparator circuit 142 shown in FIG. 6 is disabled, and the control voltage VC2 is pulled up to a high voltage level. When the control voltage VC2 is pulled up to the high voltage level, the transistors P5 and P6 are turned off (turn off). Therefore, when the control signal EN (control signal ENB) disables the droop control circuit 140, the droop control circuit 140 may not interfere (adjust) the gate voltage PGATE and the gate voltage NGATE.

In some applications, after the output voltage VOUT is pulled up, the output voltage VOUT may exceed (be greater than) the input voltage VIN for a certain period, and then the level of the output voltage VOUT returns to be consistent with the input voltage VIN after the certain period ends. Generally, the specific period is short. The fall control circuit 140 may be disabled during the specific period and enabled outside the specific period by control of the control signal EN (control signal ENB). Therefore, malfunction of the fall control circuit 140 in the specific period can be avoided.

In summary, the output buffer 100 and the operating method thereof according to the embodiments of the invention can compare the input voltage VIN with the output voltage VOUT. When the output voltage VOUT is to be pulled up, the gate voltage PGATE and the gate voltage NGATE of the output stage circuit 120 of the output buffer 100 are both pulled down to increase the slew rate of the output voltage VOUT. When the output voltage VOUT is to be pulled down, the gate voltage PGATE and the gate voltage NGATE of the output stage circuit 120 of the output buffer 100 are both pulled up to increase the slew rate of the output voltage VOUT.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, but rather, may be embodied in many different forms and varied within the spirit and scope of the invention.

Claims

1. An output buffer comprising:

an input stage circuit configured to receive an input voltage of the output buffer and generate a first gate voltage and a second gate voltage according to the input voltage;

an output stage circuit coupled to the input stage circuit to receive the first and second gating voltages, configured to generate an output voltage of the output buffer according to the first and second gating voltages;

a boost control circuit configured to compare the input voltage and the output voltage to obtain a first comparison result, wherein the boost control circuit pulls down the first gating voltage and the second gating voltage during a first transient when the first comparison result indicates that the output voltage is to be pulled up; and

a droop control circuit configured to compare the input voltage and the output voltage to obtain a second comparison result, wherein the droop control circuit pulls up the first and second gating voltages during a second transient when the second comparison result indicates that the output voltage is to be pulled down.

2. The output buffer of claim 1, wherein the output stage circuit comprises:

a first transistor having a control terminal coupled to the input stage circuit for receiving the first gate voltage, wherein a first terminal of the first transistor is coupled to a system voltage, a second terminal of the first transistor is coupled to an output terminal of the output stage circuit, and the output terminal of the output stage circuit outputs the output voltage of the output buffer; and

a second transistor having a control terminal coupled to the input stage circuit for receiving the second gate voltage, wherein a first terminal of the second transistor is coupled to a reference voltage, and a second terminal of the second transistor is coupled to the output terminal of the output stage circuit.

3. The output buffer of claim 1,

when the input voltage is greater than the output voltage, the rise control circuit pulls down the first and second gate voltages, an

When the input voltage is less than or equal to the output voltage, the rising control circuit does not adjust the first gating voltage and the second gating voltage.

4. The output buffer of claim 1, wherein the rise control circuit comprises:

a comparison circuit configured to compare the input voltage and the output voltage to generate a control voltage as the first comparison result;

a first transistor having a control terminal coupled to an output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the first transistor is coupled to a reference voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit for receiving the first gating voltage; and

a second transistor having a control terminal coupled to the output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the second transistor is coupled to the reference voltage, and a second terminal of the second transistor is coupled to a second input terminal of the output stage circuit for receiving the second gating voltage.

5. The output buffer of claim 4, wherein the comparison circuit comprises:

a third transistor having a control terminal coupled to the input voltage, wherein a first terminal of the third transistor is coupled to the output voltage;

a current mirror having a main current terminal coupled to a second terminal of the third transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit; and

a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the reference voltage, and a second terminal of the fourth transistor is coupled to the slave current terminal of the current mirror.

6. The output buffer of claim 4, wherein the comparison circuit comprises:

a fourth transistor having a control terminal controlled by a first control signal, wherein a first terminal of the fourth transistor is coupled to a second terminal of the third transistor;

a current mirror having a main current terminal coupled to a second terminal of the fourth transistor, wherein a slave current terminal of the current mirror is coupled to the output terminal of the comparison circuit;

a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to a system voltage, and a second terminal of the fifth transistor is coupled to an enable terminal of the current mirror; and

a sixth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the sixth transistor is coupled to the reference voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror.

7. The output buffer of claim 6, wherein the comparison circuit further comprises:

a seventh transistor having a control terminal controlled by a second control signal, wherein a first terminal of the seventh transistor is coupled to the reference voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor.

8. The output buffer of claim 1,

when the input voltage is less than the output voltage, the droop control circuit pulls up the first and second gate-control voltages, an

When the input voltage is greater than or equal to the output voltage, the droop control circuit does not adjust the first gating voltage and the second gating voltage.

9. The output buffer of claim 1, wherein the droop control circuit comprises:

a comparison circuit configured to compare the input voltage and the output voltage to generate a control voltage as the second comparison result;

a first transistor having a control terminal coupled to an output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the first transistor is coupled to a system voltage, and a second terminal of the first transistor is coupled to a first input terminal of the output stage circuit for receiving the first gating voltage; and

a second transistor having a control terminal coupled to the output terminal of the comparison circuit for receiving the control voltage, wherein a first terminal of the second transistor is coupled to the system voltage, and a second terminal of the second transistor is coupled to a second input terminal of the output stage circuit for receiving the second gating voltage.

10. The output buffer of claim 9, wherein the comparison circuit comprises:

a fourth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the fourth transistor is coupled to the system voltage, and a second terminal of the fourth transistor is coupled to the slave current terminal of the current mirror.

11. The output buffer of claim 9, wherein the comparison circuit comprises:

a fifth transistor having a control terminal controlled by the first control signal, wherein a first terminal of the fifth transistor is coupled to a reference voltage, and a second terminal of the fifth transistor is coupled to an enable terminal of the current mirror; and

a sixth transistor having a control terminal coupled to the output terminal of the comparison circuit, wherein a first terminal of the sixth transistor is coupled to the system voltage, and a second terminal of the sixth transistor is coupled to the slave current terminal of the current mirror.

12. The output buffer of claim 11, wherein the comparison circuit further comprises:

a seventh transistor having a control terminal controlled by a second control signal, wherein a first terminal of the seventh transistor is coupled to the system voltage, and a second terminal of the seventh transistor is coupled to the control terminal of the sixth transistor.

13. A method of operation of an output buffer, comprising:

an input stage circuit correspondingly generates a first gating voltage and a second gating voltage according to an input voltage of the output buffer;

generating an output voltage of the output buffer by an output stage circuit according to the first gate control voltage and the second gate control voltage;

comparing the input voltage with the output voltage by a rising control circuit to obtain a first comparison result;

pulling down, by the rise control circuit, the first and second gating voltages during a first transient when the first comparison result indicates that the output voltage is to be pulled up;

comparing the input voltage with the output voltage by a droop control circuit to obtain a second comparison result; and

when the second comparison result indicates that the output voltage is to be pulled down, the first gating voltage and the second gating voltage are pulled up by the fall control circuit during a second transient period.

14. The method of operation of claim 13, wherein the step of pulling down the first and second gating voltages comprises:

when the input voltage is greater than the output voltage, the first gating voltage and the second gating voltage are pulled down by the rising control circuit; and

when the input voltage is less than or equal to the output voltage, the first gating voltage and the second gating voltage are not adjusted by the rising control circuit.

15. The method of operation of claim 13, wherein the step of pulling up the first and second gating voltages comprises:

when the input voltage is less than the output voltage, the first and second gate-controlled voltages are pulled up by the droop control circuit, and

when the input voltage is greater than or equal to the output voltage, the first gating voltage and the second gating voltage are not adjusted by the droop control circuit.