CN111694541B - Base 32 operation circuit for number theory transformation multiplication - Google Patents

Abstract

The invention discloses a basic 32 operation circuit for number theory transformation multiplication, which comprises 32 operand generation modules, wherein each of 32 input data is divided into 11 words by taking 6 bits as one word after being subjected to high-order zero padding, 1 way of 32 96-bit operands, 16 ways of 11 192-bit operands, 3 ways of 16 192-bit operands and 12 ways of 12 192-bit operands are combined and output, each operand generation module is connected with an operand modular addition module, and the operands output by each operand generation module are subjected to modular addition; the modulo p module is used for modulo outputting the data output by each operand modulo adding module to prime number p, wherein the prime number p=2 ⁶⁴ ‑2 ³² +1. The invention combines 1024 operands from the prior art to 400 operands, greatly reduces the calculation cost and improves the calculation efficiency of the base 32 operation.

Description

A radix-32 operation circuit for number-theoretic transformation and multiplication

technical field

The invention relates to an operation circuit, in particular to a base-32 operation circuit for number theory transformation and multiplication.

Background technique

-Strassen算法。

-Strassen算法的核心思想是：对两个长度为n的大整数分别做一次环上的FFT，转换为频域分布；对两个整数的频域分布做点乘，得到乘积的频域分布；对乘积的频域分布做一次环上的IFFT，由此得到乘积。使用数论变换而不是离散傅立叶变换，可以通过使用模块化算术而不是浮点算术来避免舍入误差问题。数论变换乘法特指

-Strassen算法中使用数论变换的乘法。数论变换和逆数论变换作为数论变换乘法中的运算核心，占据了NTT乘法中90％以上的运算量和运算时间，优化数论变换的速度、面积和功耗，对于NTT乘法的整体性能，具有关键性的影响。In addition to traditional long multiplication, large integer multiplication also has

-Strassen algorithm.

-The core idea of the Strassen algorithm is: perform an FFT on the ring for two large integers with a length of n, and convert them into frequency domain distributions; perform dot multiplication on the frequency domain distributions of two integers to obtain the frequency domain distribution of the product; The product is obtained by performing an IFFT in the ring on the frequency domain distribution of the product. Using number-theoretic transforms instead of discrete Fourier transforms avoids round-off error problems by using modular arithmetic instead of floating-point arithmetic. Number Theoretic Transformation and Multiplication

- Multiplication using number-theoretic transformations in Strassen's algorithm. Number-theoretic transformation and inverse number-theoretic transformation, as the core of operation in number-theoretic transformation multiplication, occupy more than 90% of the calculation amount and operation time in NTT multiplication. Optimizing the speed, area and power consumption of number-theoretic transformation is critical to the overall performance of NTT multiplication sexual influence.

A 1048576-point number-theoretic transformation can be decomposed into operations of 4-level radix-32 arithmetic units and multiplication of twiddle factors. The calculation of the twiddle factor can be calculated in advance and stored in the ROM, and can be read directly when needed. The calculation amount of radix-32 operation accounts for more than 90% of the number-theoretic transformation, and its optimization is crucial to the efficiency of the number-theoretic transformation.

-Strassen算法的大整数乘法器硬件架构。论文将65536点的数论变换，分解成64点与1024点的形式，1024点数论变换使用2级基32运算串行构建的结构。其基32运算包括32个移位单元和树形大数求和处理单元。论文所采用的“0”填充的方式，使得每个树形大数求和处理单元，需要处理32个192位的数据，整个基32运算需要处理32*32＝1024个操作数。该基32运算电路效率不够高，导致电路实现后所需的功耗和资源比较大。FPGA Design and Implementation of Large Integer Multiplier, Xie Xing et al., Journal of Electronics and Information Technology, 2019. This paper describes a

- Large integer multiplier hardware architecture for Strassen algorithm. The paper decomposes the 65536-point number theory transformation into 64-point and 1024-point forms, and the 1024-point number theory transformation uses a structure constructed in series by two-level radix-32 operations. Its radix-32 operation includes 32 shift units and a tree-shaped large number sum processing unit. The "0" filling method used in the paper makes each tree-shaped large number sum processing unit need to process 32 pieces of 192-bit data, and the entire radix-32 operation needs to process 32*32=1024 operands. The efficiency of the radix-32 operation circuit is not high enough, resulting in relatively large power consumption and resources required after the circuit is implemented.

Contents of the invention

In view of the above-mentioned defects in the prior art, the present invention provides a radix-32 operation circuit for number-theoretic transformation and multiplication, which solves the problems of high power consumption and resource overhead of the radix-32 operation circuit.

The technical scheme of the present invention is as follows: a base 32 operation circuit for number theory transformation multiplication, comprising:

Operand generation module, be provided with 32, 32 operand generation module numbers are Xk, k=0,1,2,...,31, each described operand generation module comprises dividing circuit, combining circuit and filling A zero circuit, the segmentation circuit fills high bits with zeros for each of the 32 input data and divides it into 11 words with 6 bits as a word, and the input data after segmentation is x _{n, m} , 0≤n<32,0 ≤m<11, the merging circuit forms an operand output from the input data divided into 32×11 words, and one output of the merging circuits of the 32 operand generation modules is 32 96-bit operations Number, 16 outputs are 11 192-bit operands, 3 outputs are 16 192-bit operands, and 12 outputs are 12 192-bit operands, when the zero-filling circuit outputs the operands from the combining circuit Fill in the empty space with "0";

An operand modulo addition module modulo-adds the output operands of each of the operand generation modules;

as well as,

The modulo p module realizes outputting the data output by each operand modulo addition module modulo a prime number p, where the prime number p=2 ⁶⁴ -2 ³² +1.

Further, the number of the operand generating module whose output is 32 96-bit operands is X0, the last 11 words of each 96-bit operand are input data, and the first 5 words are allocated as zero.

Further, the number of the operand generation module whose output is 11 192-bit operands is Xk, k is an odd number, and each operand OP _m consists of 32 different input data x _{n, m} , 0≤n<32, Using the same word index m, 0 ≤ m < 11 combined, x _{n, the position of the lowest bit of m} in OP _m , is calculated by 6×(m+nk) (mod 192).

Further, the operand generation module whose output is 16 192-bit operands is numbered X8, X16 and X24, and the 16 operands are divided into 8 groups, each group has 2 operands, OP0 and OP1 are one group, and OP2 and OP3 are a group, and so on, the operands OP _2j and OP _2j+1 in each group are combined by 44 different input data x _{n, m} , 4j≤n≤4j+3, 0≤m<11 and Cheng, the position of the lowest bit of x _{n, m} in OP _2j and OP _2j+1 is calculated by 6×(m+nk) (mod 192), x _{n, m} is preferentially placed in OP _2j , such as OP If the position in _2j is already occupied, it is placed in the corresponding position in OP _2j+1 .

Further, the number of the operand generation module whose output is 12 192-bit operands is Xk except X0, X8, X16 and X24, k is an even number, and the 12 operands are divided into 2 groups, and OP0 to OP5 are one Groups, OP6 to OP11 are a group, and the operands OP _6j to OP _6j+5 in each group are formed by merging 176 different input data x _{n, m} , 16j≤n≤16j+15, 0≤m<11 , The position of the lowest bit of x _{n, m} in OP _6j to OP _6j+5 is calculated by 6×(m+nk) (mod 192), x _{n, m} combines operands with a cycle of 2 words, Placed preferentially in the OP with the lower index number among OP _6j to OP _6j+5 .

The advantage of the technical solution provided by the present invention is:

Utilize the "zero padding" vacancy after the operand is shifted, merge the operands of the radix 32 operation in the multiplication of the number theory transformation, and merge the operands from 1024 in the prior art to 400, which greatly reduces the calculation cost and improves the efficiency. Computational efficiency of radix-32 operations.

Description of drawings

FIG. 1 is a schematic diagram of the overall structure of the radix-32 operation circuit for number-theoretic transformation and multiplication of the present invention.

Fig. 2 is a schematic diagram of a segmentation circuit filling zeros for input data in the operand generation module.

Fig. 3 is a schematic diagram of the segmentation circuit in the operand generation module.

Fig. 4 is a schematic diagram of the output data obtained by the merging circuit of the X0 operand generation module.

Fig. 5 is a schematic diagram of the merging circuit of the X0 operand generation module.

Fig. 6 shows operands after merging by the merging circuit of the X1 operand generation module.

Fig. 7 is the merging circuit of operand 0 OP0 in the X1 operand generation module.

Fig. 8 shows operands after merging by the merging circuit of the X3 operand generation module.

Fig. 9 shows operands after merging by the merging circuit of the X16 operand generation module.

Fig. 10 shows the operands combined by the merging circuit of the X2 operand generation module.

Fig. 11 is a schematic circuit diagram of a 32-operation digital-to-analog module.

Fig. 12 is a schematic circuit diagram of an 11-operation digital analog addition module.

Fig. 13 is a schematic circuit diagram of a 16-operation digital analog addition module.

Fig. 14 is a schematic circuit diagram of a 12-operation digital analog addition module.

Detailed ways

The present invention will be further described below in conjunction with embodiment, should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art can modify various equivalent forms of the present invention All fall within the scope defined by the appended claims of this application.

The formula for the base 32 operation is as follows

Wherein, 0≤k<32, p is a prime number, and W ₃₂ is the 32nd unit root.

The prime number p is a Solinas prime number, p=2 ⁶⁴ -2 ³² +1. The prime numbers support efficient modulo operations: 2 ¹⁹² mod p = 1, 2 ⁹⁶ mod p = -1, 2 ⁶⁴ mod p = 2 ³² -1. Utilizing the property that the unit root W ₃₂ =2 ⁶ obtained by the prime number calculation is a power of 2, the above multiplication and addition operations can be conveniently converted into shift and modular addition operations, reducing the computational complexity of number theory transformation. Thus, the radix-32 operation can be written as

Divide each x _n into 11 words with 6 bits as a basic unit, called x _n,m , 0≤m<11. x _n can be expressed as

Where m represents the mth word, the data width of x _n is 64 bits, the data width of x _{n, m} is 6 bits, and the effective data bits of x _{n, 10} are 4 bits. After the input data is divided, the radix-32 operation can be written as the following formula, and the shifted operands can be combined by using "0 padding" to reduce the number of operation operations of modulo addition.

Please refer to Fig. 1, a kind of radix-32 operation circuit for number theory transformation multiplication involved in this embodiment, including 32 operand generation modules from X0 to X31, an operand modulo addition module and a modulo p module, wherein the operand The modular addition module is divided into a 32-operand analog addition module, an 11-operand analog addition module, a 16-operand analog addition module, and a 12-operand analog addition module according to the number of input operands. The 32 pieces of 64-bit bit data input on the circuit structure are used as the input of each operand generating module, and each operand generating module is connected to the operand modulo adding module, and each operand modulo adding module is connected to the modulo p module.

The operand generating module includes a dividing circuit, a combining circuit and a zero-filling circuit, which sequentially divide, combine and fill zero-input 32 pieces of 64-bit data to form operands. Please combine Figure 2 and Figure 3, the segmentation circuit fills the highest 2 bits of each 64-bit input data x _n with 0s to form 66-bit data, and then divides it into 11 words, each word contains 6 bits, the 11th Since the highest 2 bits of the word are filled with 0, the effective data bits are 4 bits. Data partitioning can be easily implemented with existing hardware with almost no hardware overhead.

The operand generation modules are numbered with Xk, k=0, 1, 2, .

Group 1: X0, a total of 1; Group 2: X1, X3, X5, etc. k is an odd number, a total of 16; Group 3: X8, X16 and X24, a total of 3; Group 4: except Group 1 and Group 3 The k is an even number, such as X2, X4, X6, etc., a total of 12.

The following groupings explain the data merge operations for each group:

Group 1 is the merging circuit of the X0 operand generation module.

The operands are actually aligned input data. In other words, each operand is derived from 11 consecutive words of output data from the split circuit. The output of the merging circuit is 32 96-bit operands, each new 96-bit operand is composed of 16 words, the last 11 words are input data, and the first 5 words are assigned as zero. As shown in Figure 4, the number i operand OP _j has 96 bits, which is obtained by placing x _n in the lower 66 bits and filling the upper 30 bits with zeros. The merging circuit is shown in Figure 5.

Group 2, the merging circuit of X1, X3, X5 and other odd operand generation modules.

For the merging circuit of the Xk operand generation module where k is an odd number, the input is 32 64-bit input data, and the output is 11 192-bit operands. Each operand OP _m is formed by merging 32 different data x _n,m , 0≤n<32, using the same word index m, 0≤m<11. x _{n, the position of the lowest bit of m} in OP _m , is calculated by 6×(m+nk)(mod 192). The following takes X1 and X3 as examples to illustrate the output operand composition:

The combined operands of the merging circuit of the X1 operand generating module are shown in FIG. 6 . After merging, there are 11 operands in total, and each operand is formed by merging 32 different data x _n,m , 0≤n<32, using the same word index m, 0≤m<11. x ₀ , the position of the lowest bit of 0 in OP0 is 6×(0+0×1)(mod 192)=0, x ₁ , the position of the lowest bit of 0 in OP0 is 6×(0+1×1 )(mod 192)=6, and x ₀ , the position of the lowest bit of 1 in OP1 is 6*(1+0×1)(mod 192)=6, x ₃₁ , the position of the lowest bit of 1 in OP1 It is 6×(1+31×1)(mod 192)=0. The merging circuit of operand OP0 in X1 operand generation module is shown in Fig. 7 .

The combined operands of the merging circuit of the X3 operand generation module are shown in FIG. 8 . x ₀ , the position of the lowest bit of 0 in OP0 is 6×(0+0×3)(mod 192)=0, x ₁ , the position of the lowest bit of 0 in OP0 is 6×(0+1×3 )(mod192)=18, and x _0, the position of the lowest bit of 1 in OP1 is 6×(1+0×3)(mod 192)=6, x ₃₁ , the position of the lowest bit of 1 in OP1 is 6*(1+31*3)(mod 192)=180.

The operands output by the merging circuits of the remaining operand generating modules are deduced in turn.

Group three, merging circuits of X8, X16 and X24 operand generation modules.

The input is 32 64-bit input data, and the output is 16 192-bit operands. The 16 operands are divided into 8 groups, each group has 2 operands, OP0 and OP1 are one group, OP2 and OP3 are one group, and so on. The operands OP _2j and OP _2j+1 in each group are formed by combining 44 different data x _n,m , 4j≤n≤4j+3, 0≤m<11. x _{n, the position of the lowest bit of m} in OP _2j and OP _2j+1 is calculated by 6×(m+nk) (mod 192). x _{n, m} is placed in OP _2j first, if the position in OP _2j is already occupied, it is placed in the corresponding position in OP _2j+1 . Fill the rest of the blanks with "0". Taking the output data of the merging circuit of the X16 operand generating module as an example, as shown in FIG. 9 , there are 8 groups of operands, and each group includes 2 operands after merging. Each new 192-bit operand consists of 32 words from 2 different input data, each providing 11 consecutive words. The upper 30 bits of 192 and the 30 bits between two consecutive 11 words are filled with 0.

Group four, merging circuits of even operand generation modules except for groups one and three.

For the merging circuit of the Xk operand generation module where k is an even number other than 0, 8, 16 or 24, the input is 32 64-bit input data, and the output is 12 192-bit operands. The 12 operands are divided into 2 groups, each group has 6 operands, OP0 to OP5 is a group, OP6 to OP11 is a group. The operands OP _6j to OP _6j+5 in each group are formed by combining 176 different data x _n,m , 16j≤n≤16j+15, 0≤m<11. x _{n, the position of the lowest bit of m} in OP _6j to OP _6j+5 is calculated by 6×(m+nk) (mod192). x _{n, m} combine operands at a period of 2 words, and place them in the OP with a smaller index number among OP _6j to OP _6j+5 first. Fill the rest of the blanks with "0". Taking the output data of the merging circuit of the X2 operand generating module as an example, as shown in FIG. 9 , there are 2 groups of operands, and each group includes 6 operands after merging. The first group includes OP0 to OP5; the second group includes OP6 to OP11. Each new 192-bit operand consists of 32 words from 16 different input data, each providing 2 consecutive words.

According to the number of operands obtained by the above different groups of operand generation modules, the operand modulus addition module includes a 32-operand modulo addition module, an 11-operand modulus addition module, a 16-operand modulus addition module, and a 12-operand modulus addition module.

The 32-operand analog addition module is shown in Figure 11, where CSA means carry-save adder, CPA means ripple carry adder, "<<1" means shift the carry end (Carry end) of the carry-save adder to the left 1 bit. Among the 32 operands, 4i, i=1, 2, ..., 8 operands are reserved, and the rest of the operands are input into the first layer of CSA every three; the carry end of the first layer of CSA is shifted to the left by 1 bit With its sum end and 4i, i=1, 2,..., the operand at 8 positions is input to the second layer CSA; the sum end of every two second layer CSAs and the carry end of one of the second layer CSAs Shift 1 bit to the left to enter the third-level CSA; the carry end of the third-level CSA is shifted to the left by 1 bit, the sum end of the third-level CSA and the other second-level CSA of every two second-level CSAs Shift the carry end to the left by 1 bit and input the fourth layer CSA; shift the sum end of every two fourth layer CSAs and the carry end of one of the fourth layer CSAs to the left by 1 bit and input the fifth layer CSA; The carry end of the layer CSA is shifted to the left by 1 bit, the sum end of the fifth layer CSA and the carry end of the other fourth layer CSA in every two fourth layer CSAs are shifted to the left by 1 bit and input to the sixth layer CSA; There are two CSAs in the sixth layer, shift the carry end of the second CSA to the left by 1 bit, and input the sum end of the second CSA and the sum end of the first CSA into the seventh layer CSA (1 in total) ;The carry end of the CSA of the seventh layer is shifted to the left by 1 bit, the sum end and the carry end of the first CSA of the sixth layer are shifted to the left by 1 and input to the CSA of the eighth layer; the CSA carry end of the eighth layer is shifted to the left Bit 1 and the sum terminal are input to CPA, and the result is then input to the modulo addition module. The modular addition module implements the input 193-bit width data, realizes the addition operation of the lower 192-bit data and the 193-bit data, and the output result is congruent to the prime number p of the input data.

The 11-operand modulo addition module is shown in Figure 12, where CSA stands for carry-save adder, CPA stands for ripple-carry adder, and "ROL 1-bit" means the carry end (Carry end) of the carry-save adder is rotated to the left Shift by 1 bit. Among the 11 operands, 1, 2, 3; 5, 6, 7; 9, 10, and 11 are respectively input into three first-level CSAs, and the sum terminal of the first CSA in the first-level CSA, operand 4 and the second The carry end of the second CSA in the first layer of CSA is rotated to the left by 1 bit and input to the first CSA of the second layer, and the operand 8 and the carry end of the third CSA in the first layer of CSA are shifted to the left by 1 bit And its sum end is input to the second CSA of the second layer, the carry end of the first CSA in the first layer CSA is cyclically shifted to the left by 1 bit, and the carry end of the first CSA of the second layer is cyclically shifted to the left by 1 The bit and its sum terminal are input to the first CSA of the third layer, the sum terminal of the second CSA in the first layer CSA, and the carry terminal of the second CSA of the second layer are cyclically shifted to the left by 1 bit and its sum The terminal is input to the second CSA of the third layer; the sum terminal of the first CSA in the third layer CSA, the carry terminal of the second CSA of the third layer is cyclically shifted to the left by 1 bit and its sum terminal is input to the fourth layer CSA; the carry end of the first CSA in the third layer CSA is cyclically shifted to the left by 1 bit, the carry end of the fourth layer CSA is cyclically shifted to the left by 1 bit and the sum end is input to the fifth layer CSA; the fifth layer The carry end of CSA is shifted 1 bit to the left and the sum end is input to CPA, and the result is input to the modulo addition module. The modular addition module realizes the addition operation of the input 193-bit width data, the lower 192-bit data and the 193-bit data, and the output result is congruent to the prime number p of the input data.

The 16-operand analog addition module is shown in Figure 13, where CSA means carry-save adder, CPA means ripple carry adder, "<<1" means shift the carry end (Carry end) of the carry-save adder to the left 1 bit. Among the 16 operands, 4i, i=1, 2, 3, and 4 operands are reserved, and the remaining operands are input into the first layer of CSA every three; the carry end of the first layer of CSA is shifted to the left by 1 bit and its sum Number terminal and 4i, i=1, 2, 3, 4 operands are input to the second-level CSA; the sum terminal of every two second-level CSAs and the carry terminal of one of the second-level CSAs are shifted to the left 1 bit is input to the third-level CSA; the carry end of the third-level CSA is shifted to the left by 1 bit, the sum end of the third-level CSA and the carry end of the other second-level CSA in every two second-level CSAs are left Shift 1 bit to input the fourth layer CSA; the fourth layer CSA has two CSAs, shift the carry end of the second CSA to the left by 1 bit, the sum end of the second CSA and the sum of the first CSA input to the fifth layer CSA (total 1); the CSA carry end of the fifth layer is shifted to the left by 1 bit, the sum end and the carry end of the first CSA of the fourth layer are shifted to the left by 1 bit and input to the sixth layer CSA: The CSA carry end of the sixth layer is shifted to the left by 1 and the sum end is input to CPA, and the result is then input to the modulo addition module. The modular addition module realizes the addition operation of the input 193-bit width data, the lower 192-bit data and the 193-bit data, and the output result is congruent to the prime number p of the input data.

The 12-operand modulo addition module is shown in Figure 14, where CSA stands for carry-save adder, CPA stands for ripple carry adder, and "ROL 1-bit" means that the carry end (Carry end) of the carry-save adder is rotated to the left Shift by 1 bit. Every three of the 12 operands are input to the first-layer CSA, and the sum ends of every two first-layer CSAs and the carry end of one of the second-layer CSAs are cyclically shifted to the left by 1 bit and input to the second-layer CSA; The carry end of the layer CSA is cyclically shifted to the left by 1 bit, and the sum end of the second layer CSA and the carry end of the other first layer CSA in every two first layer CSAs are cyclically shifted to the left by 1 and input to the third layer CSA There are two CSAs in the third layer of CSA, the carry end of the second CSA is cyclically shifted to the left by 1 bit, the sum end of the second CSA and the sum end of the first CSA are input into the fourth layer CSA (total 1); the CSA carry end of the fourth layer is cyclically shifted to the left by 1 bit, the sum end and the carry end of the first CSA of the third layer are cyclically shifted to the left by 1 bit and input to the fifth layer CSA; The carry terminal of CSA is rotated to the left by 1 bit and the sum terminal is input to CPA, and the result is then input to the modulo addition module. The modular addition module realizes the addition operation of the input 193-bit width data, the lower 192-bit data and the 193-bit data, and the output result is congruent to the prime number p of the input data.

The modulo p module implements the modulo of the prime number p on the input data.

Claims (5)

1. A radix-32 arithmetic circuit for number-theoretic transformation multiplication, characterized in that the operand generating modules are provided with 32, and the 32 operand generating modules are numbered Xk, k=0, 1, 2,... , 31, each of the operand generation modules includes a segmentation circuit, a merge circuit and a zero-filling circuit, and the segmentation circuit performs high-order zero-filling on each of the 32 input data and divides it into 11 words with 6 bits as a word , the divided input data is x _{n, m} , 0≤n<32, 0≤m<11, the merging circuit forms the input data divided into 32×11 words to form an operand output, and the 32 In the said merging circuit of the operand generating module, 1 output is 32 96-bit operands, 16 outputs are 11 192-bit operands, 3 outputs are 16 192-bit operands, and 12 outputs are 12 192-bit operands. A bit operand, the zero-filling circuit fills the vacancy when the combining circuit outputs the operand with "0"; An operand modulo addition module modulo-adds the output operands of each of the operand generation modules; as well as, The modulo p module realizes outputting the data output by each operand modulo addition module modulo a prime number p, where the prime number p=2 ⁶⁴ -2 ³² +1. 2. the base 32 arithmetic circuit for number theory transformation multiplication according to claim 1, is characterized in that, described output is the operand generation module numbering of 32 96-bit operands is X0, and the number of each 96-bit operand The last 11 words are input data, and the first 5 words are assigned zeros. 3. the base 32 arithmetic circuit for number theory transformation multiplication according to claim 1, is characterized in that, described output is the operand generation module numbering of 11 192-bit operands Xk, and k is an odd number, and each operation The number OP _m is formed by merging 32 different input data x _{n, m} , 0≤n<32, using the same word index m, 0≤m<11, and the lowest bit of x _{n, m} is in the position of OP _m , is calculated by 6×(m+nk)(mod 192). 4. The base 32 arithmetic circuit for number theory transformation multiplication according to claim 1, characterized in that, the operand generation module numbering of 16 192-bit operands for the output is X8, X16 and X24, and 16 operations The number is divided into 8 groups, each group has 2 operands, OP0 and OP1 are a group, OP2 and OP3 are a group, and so on, the operands OP _2j and OP _2j+1 in each group are composed of 44 different inputs Data x _{n, m} , 4j≤n≤4j+3, 0≤m<11 are combined, and the position of the lowest bit of x _{n, m} in OP _2j and OP _2j+1 is determined by 6×(m+nk ) (mod 192), x _{n, m} is preferentially placed in OP _2j , if the position in OP _2j is already occupied, it is placed in the corresponding position in OP _2j+1 . 5. the base 32 operation circuit for number theory transformation multiplication according to claim 1, is characterized in that, described output is the operand generation module numbering of 12 192 bit operands except X0, X8, X16 and X24 Xk, k is an even number, 12 operands are divided into 2 groups, OP0 to OP5 is a group, OP6 to OP11 is a group, and the operands OP _6j to OP _6j+5 in each group are composed of 176 different input data x _{n, m} , 16j≤n≤16j+15, 0≤m<11 are combined, the position of the lowest bit of x _{n, m} in OP _6j to OP _6j+5 is 6×(m+nk) Calculated by (mod 192), x _{n, m} combine operands at a period of 2 words, and place them in OP _6j to OP _6j+5 with a smaller index number first.

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