CN111694293A - Low-power consumption control circuit and low-power consumption electronic product - Google Patents
Low-power consumption control circuit and low-power consumption electronic product Download PDFInfo
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- CN111694293A CN111694293A CN202010704847.3A CN202010704847A CN111694293A CN 111694293 A CN111694293 A CN 111694293A CN 202010704847 A CN202010704847 A CN 202010704847A CN 111694293 A CN111694293 A CN 111694293A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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Abstract
The application discloses low-power consumption control circuit includes: a circuit function module; the power supply module is connected with the circuit function module; the input control pin is respectively connected with the circuit functional module and the power supply module and used for receiving an input control signal sent by an external circuit and controlling the circuit functional module and the power supply module; and the timing module is respectively connected with the power supply module and the input control pin and is used for sending a corresponding feedback signal to the input control pin when detecting that the input control pin receives a low level signal exceeding the preset time length so as to turn off the power supply module by using the input control pin and enable the circuit functional module to enter a low-power-consumption standby mode. Obviously, compared with the prior art that a peripheral circuit is required to trigger the low-power-consumption control circuit to enter the low-power-consumption standby mode, the pin resource occupation amount and the design cost required by the low-power-consumption control circuit when the low-power-consumption control circuit enters the low-power-consumption standby mode can be obviously reduced through the setting mode.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a low-power-consumption control circuit and a low-power-consumption electronic product.
Background
With the continuous development of power electronic technology, higher design requirements are also put forward on the energy consumption of electronic products. In the prior art, in order to enable an electronic product to consume a low energy consumption, a low power consumption control circuit is generally built in the electronic product to enable the electronic product to enter a low power consumption standby mode when the electronic product is in the standby mode. Wherein, the low-power consumption control circuit is usually provided with a circuit function module for realizing various functions and a power module for supplying power to the circuit function module, and the realization principle that the low-power consumption control circuit enters a low-power consumption standby mode is as follows: the power supply module for supplying power to the circuit functional module is turned off through the additionally arranged peripheral circuit, and then the circuit functional module in the low-power-consumption control circuit enters a low-power-consumption standby mode through the power-off of the power supply module. However, this arrangement not only needs to occupy more pin resources in the low power consumption control circuit, but also needs higher design cost for setting the peripheral circuit. At present, no effective solution exists for the technical problem.
Therefore, how to reduce the occupied amount of pin resources and the design cost required by the low-power consumption control circuit when entering the low-power consumption standby mode is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a low power consumption control circuit and a low power consumption electronic product, so as to reduce the pin resource occupation amount and the design cost required by the low power consumption control circuit when entering the low power consumption standby mode. The specific scheme is as follows:
a low power consumption control circuit comprising:
a circuit function module;
the power supply module is connected with the circuit function module and used for providing an energy source;
the input control pin is respectively connected with the circuit functional module and the power supply module and used for receiving an input control signal sent by an external circuit and controlling the circuit functional module and the power supply module;
and the timing module is respectively connected with the power supply module and the input control pin and is used for sending a corresponding feedback signal to the input control pin when detecting that the input control pin receives a low level signal exceeding the preset time length so as to turn off the power supply module by using the input control pin and enable the circuit function module to enter a low-power-consumption standby mode.
Preferably, the timing module is specifically a timer.
Preferably, the timing module is a logic gate circuit with a timing function.
Preferably, the input control pin is an input control pin in a double full bridge driving circuit chip.
Preferably, the input control pin is an input control pin in a three-phase brushless motor driving chip.
Preferably, the power module is specifically an LDO.
Preferably, the LDO comprises a first resistor, a second resistor, a third resistor, a first NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
the first end of the first resistor is connected with a high-voltage power supply, the second end of the first resistor is connected with the source electrode of the first NMOS tube, the grid electrode of the first NMOS tube is used for receiving the bias current generated by the LDO, the drain electrode of the first NMOS tube is connected with the first end of the second resistor, the second end of the second resistor is respectively connected with the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the timing module, the source electrode of the first PMOS tube is grounded, the drain electrode of the second PMOS tube is connected with the first end of the third resistor, the source electrode of the second PMOS tube is grounded, the second end of the third resistor is connected with a low-voltage power supply, and the first end of the third resistor is the control end of the LDO.
Preferably, the method further comprises the following steps: a Zener diode;
and the anode of the Zener diode is grounded, and the cathode of the Zener diode is connected with the grid electrode of the second PMOS tube.
Correspondingly, the invention also discloses a low-power consumption electronic product which comprises the low-power consumption control circuit disclosed in the foregoing.
Obviously, compared with the prior art that a peripheral circuit is required to trigger the low-power-consumption control circuit to enter the low-power-consumption standby mode, in the low-power-consumption control circuit provided by the invention, the circuit function module in the low-power-consumption control circuit can enter the low-power-consumption standby mode only by multiplexing the input control pin in the low-power-consumption control circuit and timing the timing module. Because the input control pin is a pin of the low-power consumption control circuit, and the manufacturing cost of the timing module is far lower than that of a peripheral circuit, the pin resource occupation amount and the design cost required by the low-power consumption control circuit when the low-power consumption control circuit enters a low-power consumption standby mode can be obviously reduced through the setting mode. Correspondingly, the low-power-consumption electronic product provided by the invention also has the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural diagram of a low power consumption control circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an input control pin in a dual full bridge driver circuit chip according to an embodiment of the present invention;
fig. 3 is a structural diagram of another low power consumption control circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a structural diagram of a low power consumption control circuit according to an embodiment of the present invention; the low power consumption control circuit includes:
a circuit function block 11;
a power module 12 connected to the circuit function module 11 for providing an energy source;
an input control pin 13, which is respectively connected to the circuit function module 11 and the power module 12, and is used for receiving an input control signal sent by an external circuit and controlling the circuit function module 11 and the power module 12;
and the timing module 14 is respectively connected with the power module 12 and the input control pin 13, and is configured to send a corresponding feedback signal to the input control pin 13 when detecting that the input control pin 13 receives a low level signal exceeding a preset time duration, so as to turn off the power module 12 by using the input control pin 13, and enable the circuit function module 11 to enter a low power consumption standby mode.
In this embodiment, a novel low power consumption control circuit is provided, and through the low power consumption control circuit, the occupied amount of pin resources and the design cost required by the low power consumption control circuit when entering the low power consumption standby mode can be significantly reduced.
Specifically, the low power consumption control circuit is provided with a circuit function module 11, a power supply module 12, an input control pin 13, and a timing module 14, where the circuit function module 11 and the power supply module 12 are common function modules in the low power consumption control circuit in the prior art, and therefore, in this embodiment, details of the circuit function module 11 and the power supply module 12 are not repeated.
It can be understood that the input control pin 13 is disposed in one low power consumption control circuit, and the input control pin 13 is used to receive an input control signal sent by an external circuit to control the low power consumption control circuit, and the input control pin 13 itself can also control the circuit function module 11 and the power supply module 12 in the low power consumption control circuit. In this embodiment, when the timing module 14 detects that the input control pin 13 receives a low level signal exceeding a preset time period, it indicates that the low power consumption control circuit needs to enter a low power consumption standby mode, in this case, the timing module 14 sends a corresponding feedback signal to the input control pin 13, and when the input control pin 13 receives the feedback signal sent by the timing module 14, the power module 12 for supplying power to the circuit function module 11 is turned off, so that the power module 12 cannot supply power to the circuit function module 11 in the low power consumption control circuit, and thus the low power consumption control circuit can enter the low power consumption standby mode, and energy consumed by the control circuit is reduced.
It should be noted that, in this embodiment, the preset time duration may be flexibly set according to the needs of the actual situation, and the timing module 14 is any logic circuit module or logic device with a timing function, and is not specifically limited herein as long as the actual application requirements can be met.
In the low power consumption control circuit provided in this embodiment, the circuit function module 11 in the low power consumption control circuit can enter the low power consumption standby mode by multiplexing the input control pin 13 and timing the timing module 14. Because the input control pin 13 is a pin of the low power consumption control circuit itself, and the manufacturing cost of the timing module 14 is much lower than the design cost required by the peripheral circuit, the pin resource occupation amount and the design cost required by the low power consumption control circuit when entering the low power consumption standby mode can be significantly reduced by such an arrangement mode.
Obviously, compared with the prior art that a peripheral circuit is required to trigger the low-power-consumption control circuit to enter the low-power-consumption standby mode, in the low-power-consumption control circuit provided by the invention, the circuit function module in the low-power-consumption control circuit can enter the low-power-consumption standby mode only by multiplexing the input control pin in the low-power-consumption control circuit and timing the timing module. Because the input control pin is a pin of the low-power consumption control circuit, and the manufacturing cost of the timing module is far lower than that of a peripheral circuit, the pin resource occupation amount and the design cost required by the low-power consumption control circuit when the low-power consumption control circuit enters a low-power consumption standby mode can be obviously reduced through the setting mode.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the timing module 14 is specifically a timer.
Specifically, in this embodiment, the timing module 14 is set as a timer, because the timer is a functional module which is relatively common in engineering, and the timer has a small volume and a precise and reliable timing function, when the timing module 14 is set as the timer, the occupied space of the low power consumption control circuit can be relatively reduced.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the timing module 14 is specifically a logic gate circuit with a timing function.
In practical applications, the timing module 14 may be further configured as a logic gate circuit with timing function, because the design cost of the logic gate circuit is relatively low, and the logic gate circuit with timing function is relatively easy to implement in the design process, when the timing module 14 is configured as a logic gate circuit with timing function, the design cost required by the low power consumption control circuit may be further reduced.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the input control pin 13 is specifically an input control pin in a dual full bridge driving circuit chip.
In the present embodiment, a specific arrangement manner of the input control pin 13 is provided, that is, the input control pin 13 is arranged as an input control pin in a dual full bridge driving circuit chip. Referring to fig. 2, fig. 2 is a schematic diagram of an input control pin in a dual full bridge driver circuit chip according to an embodiment of the present invention.
In the dual full bridge driving circuit chip, the input control pin of the dual full bridge driving circuit chip is controlled by 4 control signals, that is, AIN1, AIN2, BIN1 and BIN2, when the 4 control signals are all low level, the input control pin of the dual full bridge driving circuit chip generates an input low level signal, in this case, if the timing module 14 detects that the input control pin in the dual full bridge driving circuit chip receives a low level signal exceeding a preset time duration, the input control pin is triggered to turn off the power module, and the low power consumption control circuit enters a low power consumption standby mode. When one high-level signal is selected from 4 control signals AIN1, AIN2, BIN1 and BIN2, the low-power consumption control circuit is directly awakened, so that the low-power consumption control circuit enters a normal working mode.
Obviously, the technical scheme provided by the embodiment can further ensure the overall reliability of the low-power-consumption control circuit provided by the application in the actual use process.
Based on the above embodiments, this embodiment further describes and optimizes the technical solution, and as a preferred implementation, the input control pin 13 is specifically an input control pin in a three-phase brushless motor driving chip.
In the actual use process, the input control pin 13 may also be set as an input control pin in a driving chip of the three-phase brushless motor, because the input control pin of the driving chip of the three-phase brushless motor is a pin controlled by a PWM (Pulse width modulation) signal, when the PWM signal is lower than a certain threshold, the driving chip of the three-phase brushless motor cannot normally drive the motor to operate, in this case, a low level signal is input, at this time, if the timing module 14 detects that the input control pin in the driving chip of the three-phase brushless motor receives a low level signal exceeding a preset time, the input control pin is triggered to turn off the power module, and the low power consumption control circuit enters a low power consumption standby mode, and when the PWM signal becomes high, the low power consumption control circuit is directly wakened up to enter a normal working mode.
It should be noted that, in this application, only the specific application scenarios of two input control pins are listed, that is, the dual full-bridge driving circuit chip and the three-phase brushless motor driving chip. Of course, in practical applications, the low power consumption control circuit provided in the present application may also be embedded in other low power consumption application scenarios, which are not described herein in detail.
Obviously, the technical scheme provided by the embodiment can make the low-power-consumption control circuit provided by the application more flexible and diversified.
Based on the above embodiments, the present embodiment further describes and optimizes the technical solution, and as a preferred implementation, the power module 12 is specifically an LDO.
In practical applications, the power module 12 can be configured as a Low Dropout Regulator (LDO), because the LDO not only has lower power consumption but also has lower noise compared with the conventional power module 12, when the power module 12 is configured as the LDO, the power consumption and noise of the Low power consumption control circuit can be reduced, so that the user experience when using the Low power consumption control circuit can be further improved.
Referring to fig. 3, fig. 3 is a structural diagram of another low power consumption control circuit according to an embodiment of the invention. As a preferred embodiment, the LDO includes a first resistor R1, a second resistor R2, a third resistor R3, a first NMOS transistor N1, a first PMOS transistor P1, and a second PMOS transistor P2;
the first end of the first resistor R1 is connected to the high-voltage power supply VM, the second end of the first resistor R1 is connected to the source of the first NMOS transistor N1, the gate of the first NMOS transistor N1 is used for receiving a bias current generated by the LDO, the drain of the first NMOS transistor N1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the drain of the first PMOS transistor P1 and the gate of the second PMOS transistor P2, the gate of the first PMOS transistor P1 is connected to the timing module, the source of the first PMOS transistor P1 is grounded, the drain of the second PMOS transistor P2 is connected to the first end of the third resistor R3, the source of the second PMOS transistor P2 is grounded, the second end of the third resistor R3 is connected to the low-voltage power supply AVDD, and the first end of the third resistor R3 is the control end of the LDO.
In order to make the inventive principle of the present application more clearly known to those skilled in the art, in the present embodiment, the invention is specifically described by a low power consumption control circuit shown in fig. 3. In fig. 3, VM is a high voltage power supply, and AVDD is a low voltage power supply generated by the LDO.
When the low-power consumption control circuit is in a normal working mode, the LDO can generate a normal AVDD signal and provide an energy source for each circuit component in the control circuit. In the process, current bias generated by the LDO works normally, a pull-up current of about 10uA is provided for a branch where the VM is located, VG1 is output of the timing module, VG1 is high level in normal work, the first PMOS tube P1 is conducted to directly pull VG2 to a low level state, the second PMOS tube P2 is turned off, and an LDO turn-off signal is pulled up by AVDD to output a high level.
When the timing module detects that the input control pin receives a low level signal exceeding a preset time, the output VG1 of the timing module becomes a low level, the first PMOS tube P1 is turned off, thereby causing VG2 to be pulled up to a high level, thereby the second PMOS tube P2 is turned on, the LDO turn-off signal is pulled down, the signal can directly control the LDO, and the AVDD is turned off, meanwhile, the current bias generated by the LDO is also turned off, thereby the first NMOS tube N1 is also in a turn-off state, a branch where the VM is located does not have current, so the VG2 is always in a suspended state, and therefore, a circuit function module in the low-power consumption control circuit can enter a low-power consumption standby mode.
As a preferred embodiment, the low power consumption control circuit further includes: a Zener diode D;
the anode of the zener diode D is grounded, and the cathode of the zener diode D is connected to the gate of the second PMOS transistor P2.
In order to prevent the gate voltage of M3 from being too high due to charge accumulation, in this embodiment, a zener diode D is used to protect the gate voltage of the second PMOS transistor P2, so that even if the second PMOS transistor P2 is in a conducting state, no current is generated due to the turn-off of AVDD, which further ensures the safety and reliability of the low power consumption control circuit during use.
Correspondingly, the embodiment of the invention also discloses a low-power consumption electronic product which comprises the low-power consumption control circuit disclosed in the foregoing.
The low-power-consumption electronic product provided by the embodiment of the invention has the beneficial effects of the low-power-consumption control circuit disclosed above.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The present invention provides a low power consumption control circuit and a low power consumption electronic product, and the principle and implementation of the present invention are explained in detail by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A low power consumption control circuit, comprising:
a circuit function module;
the power supply module is connected with the circuit function module and used for providing an energy source;
the input control pin is respectively connected with the circuit functional module and the power supply module and used for receiving an input control signal sent by an external circuit and controlling the circuit functional module and the power supply module;
and the timing module is respectively connected with the power supply module and the input control pin and is used for sending a corresponding feedback signal to the input control pin when detecting that the input control pin receives a low level signal exceeding the preset time length so as to turn off the power supply module by using the input control pin and enable the circuit function module to enter a low-power-consumption standby mode.
2. The low power consumption control circuit according to claim 1, wherein the timing module is specifically a timer.
3. The low power consumption control circuit according to claim 1, wherein the timing module is a logic gate circuit with timing function.
4. The low power consumption control circuit according to claim 1, wherein the input control pin is an input control pin in a dual full bridge driver circuit chip.
5. The low power consumption control circuit according to claim 1, wherein the input control pin is an input control pin in a three-phase brushless motor driving chip.
6. The low power consumption control circuit according to any one of claims 1 to 5, wherein the power supply module is specifically an LDO.
7. The low power consumption control circuit of claim 6, wherein the LDO comprises a first resistor, a second resistor, a third resistor, a first NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
the first end of the first resistor is connected with a high-voltage power supply, the second end of the first resistor is connected with the source electrode of the first NMOS tube, the grid electrode of the first NMOS tube is used for receiving the bias current generated by the LDO, the drain electrode of the first NMOS tube is connected with the first end of the second resistor, the second end of the second resistor is respectively connected with the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the timing module, the source electrode of the first PMOS tube is grounded, the drain electrode of the second PMOS tube is connected with the first end of the third resistor, the source electrode of the second PMOS tube is grounded, the second end of the third resistor is connected with a low-voltage power supply, and the first end of the third resistor is the control end of the LDO.
8. The low power consumption control circuit of claim 7, further comprising: a Zener diode;
and the anode of the Zener diode is grounded, and the cathode of the Zener diode is connected with the grid electrode of the second PMOS tube.
9. A low power consumption electronic product comprising a low power consumption control circuit as claimed in any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010704847.3A CN111694293A (en) | 2020-07-21 | 2020-07-21 | Low-power consumption control circuit and low-power consumption electronic product |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010704847.3A CN111694293A (en) | 2020-07-21 | 2020-07-21 | Low-power consumption control circuit and low-power consumption electronic product |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113795045A (en) * | 2021-08-30 | 2021-12-14 | 云南电网有限责任公司 | Power transmission line communication equipment with low power consumption |
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2020
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113795045A (en) * | 2021-08-30 | 2021-12-14 | 云南电网有限责任公司 | Power transmission line communication equipment with low power consumption |
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