CN111686829A

CN111686829A - Micro-fluidic array circuit and chip

Info

Publication number: CN111686829A
Application number: CN202010440723.9A
Authority: CN
Inventors: 冯林润; 刘哲; 杜江文; 李骏
Original assignee: Hangzhou Lingzhi Technology Co ltd
Current assignee: Hangzhou Lingzhi Technology Co ltd
Priority date: 2020-05-22
Filing date: 2020-05-22
Publication date: 2020-09-22
Anticipated expiration: 2040-05-22
Also published as: CN111686829B

Abstract

The embodiment of the application discloses a current control array circuit and a chip, wherein the circuit comprises: the microfluidic array comprises m rows and n columns of microfluidic pixel units; the system also comprises an input signal shunting circuit connected with the control signal input end of the microfluidic array and x clock signal sources CK for providing clock signals for the input signal shunting circuit; the input signal shunting circuit comprises a column input signal shunting circuit and/or a row input signal shunting circuit; each input signal shunting circuit is used for shunting an input signal of one control signal source into x sub-signals and then respectively providing control signals for the x rows or x columns of microfluidic pixel units; the input signal shunting circuit comprises x sub-shunting circuits; the x clock signal sources CK respectively provide clock signals for the x sub-shunting circuits. By the scheme of the embodiment, the number of input signals can be amplified under the condition that the cost is basically kept unchanged and the FPC binding difficulty is kept unchanged, and the resolution of the microfluidic array in a unit effective area is increased.

Description

Micro-fluidic array circuit and chip

Technical Field

The present disclosure relates to microfluidic technology, and more particularly, to microfluidic array circuits and chips.

Background

In the processes of immunodetection, molecular detection and nucleic acid protein including gene sequencing sample pretreatment, a microfluidic chip is required. The micro-fluidic chip has the working principle that the surface tension between the liquid drop and the hydrophobic dielectric medium is changed by adjusting the potential applied between the liquid drop and the solid electrode, so that the contact angle between the liquid drop and the hydrophobic dielectric medium is changed, the liquid drop is asymmetrically deformed, the internal pressure difference is generated, and the operation and the control of the liquid drop are realized. The micro-fluidic chip can be divided into a passive type and an active type according to different back plate designs. The passive micro-fluidic chip is composed of a metal electrode, a dielectric layer and a hydrophobic layer, and the pixel electrode is directly connected with an operation signal through a metal wiring. The active micro-fluidic chip is composed of a metal electrode, a semiconductor active layer, a dielectric layer and a hydrophobic layer, and the pixel electrode is connected with an operation signal through a switch device composed of the semiconductor active layer.

At present, a common micro-fluidic chip on the market is a passive chip, a processing technology is usually a PCB (printed circuit board) technology or other similar micro-nano processing technologies, and a pixel electrode is large. The passive chip has the advantages of simple design and manufacturing process and low cost, and has the defects of incapability of simultaneously controlling a plurality of liquid drops, large movable minimum liquid drop volume and consumption of a plurality of biological samples. In addition, the moving path of the liquid drop of the passive microfluidic chip is relatively fixed, and if the moving scheme of the liquid drop needs to be modified, the microfluidic chip needs to be redesigned. The number of the array units of the active microfluidic chip can be greatly increased, and the moving path of the liquid drop can be modified, so that the control number of the liquid drop is obviously improved compared with that of a passive chip, the minimum controllable liquid drop volume is smaller, and the liquid drop control method can be suitable for more liquid drop moving schemes.

The pixel circuit of a common active microfluidic chip is generally composed of a Thin Film Transistor (TFT) and a capacitor (fig. 1), and the voltage writing and holding of the pixel electrode are completed by turning on and off the TFT (fig. 2), so as to drive the droplet above the pixel electrode to move. Typically, for an active microfluidic array with a resolution of m rows x n columns (as shown in fig. 3), m rows of scanning signals and n columns of data signals need to be provided. In practical biological, chemical or material experiments, it is of practical scientific and economic significance to reduce the single minimum processing sample size, i.e. to reduce the droplet volume for pixel manipulation.

In order to be able to handle smaller droplet movements, the pixel area of the microfluidic chip should be as small as possible. To achieve this, it is necessary to increase the resolution of the microfluidic array per unit active area, but this results in an increase in the scanning and data signals. The increase in scan/data signals can lead to two disadvantages: the number of channels of the IC driving chip increases, resulting in an increase in the cost of the IC driving chip; 2. the number of binding channels is increased, so that the binding difficulty of the FPC (flexible printed circuit) is increased, and the production difficulty of the microfluidic chip is increased.

Disclosure of Invention

The embodiment of the application provides a microfluidic array circuit and a chip, which can increase the resolution of a microfluidic array in a unit effective area under the condition of basically keeping the cost unchanged and the FPC binding difficulty unchanged.

The embodiment of the application provides a microfluidic array circuit, which can comprise: the microfluidic array comprises m rows and n columns of microfluidic pixel units; m and n are natural numbers; further comprising: one or more input signal shunt circuits connected with the control signal input end of the microfluidic array and x clock signal sources CK for providing clock signals for the one or more input signal shunt circuits;

the one or more input signal splitting circuits may include: the column input signal shunting circuit is used for providing a control signal for each connected column of microfluidic pixel units, and/or the row input signal shunting circuit is used for providing a control signal for each connected row of microfluidic pixel units;

each input signal shunting circuit is used for shunting an input signal of one control signal source into x sub-signals and then respectively providing control signals for the x rows or x columns of micro-fluidic pixel units; x is a natural number greater than 1 and less than or equal to m; or x is a natural number which is more than 1 and less than or equal to n; the input signal shunting circuit includes: x sub-shunting circuits; the x clock signal sources CK respectively provide clock signals for the x sub-shunting circuits.

In an exemplary embodiment of the present application, after the signal input terminal of each sub-shunting circuit is connected, the signal input terminal of the input signal shunting circuit is formed and connected to the control signal source;

and the signal output end of each sub-shunt circuit is used as a sub-signal output end of the input signal shunt circuit and is connected with the control signal input end of one row or one column of microfluidic pixel units.

In an exemplary embodiment of the present application, each of the sub-shunt circuits may include: a first thin film transistor TFT;

the grid electrode of the first TFT is respectively connected with a clock signal source CK, one of the source electrode and the drain electrode of the first TFT is used as a signal input end of the sub-shunt circuit, and the other is used as a signal output end of the sub-shunt circuit and is connected between the control signal source and the ith row or jth column microfluidic pixel unit; i is a natural number greater than or equal to 1 and less than or equal to m; j is a natural number greater than or equal to 1 and less than or equal to n;

the clock signal sources CK connected with different sub-shunt circuits belonging to the same input signal shunt circuit have driving time differences.

In an exemplary embodiment of the present application, the sub-shunt circuit may further include: x-1 second TFTs;

the gates of the x-1 second TFTs are all connected to the clock signal source CK,

the source electrode and the drain electrode of the x-1 second TFTs are connected with a preset high level, and one of the source electrode and the drain electrode is connected with a sub-shunt circuit except the ith sub-shunt circuit in the x sub-shunt circuits;

the x-1 second TFTs are respectively connected with the signal input ends of x-1 sub-shunt circuits except the ith sub-shunt circuit in the x sub-shunt circuits; the high level is a level greater than a preset voltage threshold.

In an exemplary embodiment of the present application, any one of the TFTs in the input signal shunting circuit may be a P-type TFT or an N-type TFT.

In an exemplary embodiment of the present application, the input signal splitting circuit may include: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; a first TFT in the first sub-shunt circuit is a first P-type TFT; a first TFT in the second sub-shunt circuit is a second P-type TFT;

the input signal shunting circuit is a row input signal shunting circuit of the microfluidic array;

the grid electrode of the first P-type TFT is connected with a first clock signal source CK1, the source electrode of the first P-type TFT is a signal input end of the first sub-shunt circuit, and the drain electrode of the first P-type TFT is a signal output end of the first sub-shunt circuit and is connected with a first control signal input end of the ith row of microfluidic pixel units; the grid electrode of the second P-type TFT is connected with a second clock signal source CK2, the source electrode of the second P-type TFT is a signal input end of the second sub-shunt circuit, and the drain electrode of the second P-type TFT is a signal output end of the second sub-shunt circuit and is connected with a first control signal input end of the (i + 1) th row of microfluidic pixel units; the source electrode of the first P-type TFT is connected with the source electrode of the second P-type TFT and then serves as a signal input end of the input signal shunting circuit, and the source electrode of the first P-type TFT is connected with the control signal source; i is any odd number less than or equal to m;

or,

the input signal shunting circuit is a column input signal shunting circuit of the microfluidic array;

the grid electrode of the first P-type TFT is connected with a first clock signal source CK1, the source electrode of the first P-type TFT is a signal input end of the first sub-shunt circuit, and the drain electrode of the first P-type TFT is a signal output end of the first sub-shunt circuit and is connected with a second control signal input end of the jth row of microfluidic pixel units; the grid electrode of the second P-type TFT is connected with a second clock signal source CK2, the source electrode of the second P-type TFT is a signal input end of the second sub-shunt circuit, and the drain electrode of the second P-type TFT is a signal output end of the second sub-shunt circuit and is connected with a second control signal input end of the (j + 1) th row of microfluidic pixel units; the source electrode of the first P-type TFT is connected with the source electrode of the second P-type TFT and then serves as a signal input end of the input signal shunting circuit, and the source electrode of the first P-type TFT is connected with the control signal source; j is any odd number less than or equal to n.

In an exemplary embodiment of the present application, the input signal splitting circuit includes: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; the second TFT of the first sub-shunt circuit is a third P-type TFT; the second TFT of the second sub-shunting circuit is a fourth P-type TFT;

wherein the gates of the third P-type TFTs are all connected with the first clock signal source CK1,

the source electrode of the third P-type TFT is connected with a preset high level, and the drain electrode of the third P-type TFT is connected with the signal input end of the second sub-shunt circuit;

the gates of the fourth P-type TFTs are all connected to the second clock signal source CK2,

and the source electrode of the fourth P-type TFT is connected with a preset high level, and the drain electrode of the fourth P-type TFT is connected with the signal output end of the first sub-shunt circuit.

In an exemplary embodiment of the present application, when m is an even number, the microfluidic array circuit may include: 2+ m/2 line input signal shunt circuits; when m is an odd number, the microfluidic array circuit may include: 3+ (m-1)/2 line input signal shunt circuits;

and/or the presence of a gas in the gas,

when n is an even number, the microfluidic array circuit comprises: 2+ n/2 column input signal shunt circuits; when n is an odd number, the microfluidic array circuit comprises: 3+ (n-1)/2 column input signal shunt circuits.

In an exemplary embodiment of the present application, each of the row input signal splitting circuits may be configured to split an input signal of one first control signal source into x split signals and then respectively provide the x row microfluidic pixel units with the first control signals;

each column input signal shunting circuit can be used for shunting an input signal of a second control signal source into x sub-signals and then respectively providing second control signals for the x columns of microfluidic pixel units;

the microfluidic pixel cell may include: a pixel TFT and a capacitor;

the grid electrode of the pixel TFT is used as a second control signal input end of the pixel TFT and is connected with one sub-signal output end of the column input signal shunting circuit;

a source or a gate of the pixel TFT, one of which is used as a first control signal input terminal of the pixel TFT, is connected to one of the sub-signal output terminals of the row input signal shunting circuit; the other is connected with the capacitor in series and then grounded.

The embodiment of the application provides a microfluidic chip, which can comprise the microfluidic array circuit.

Compared with the related art, the microfluidic array circuit of the embodiment of the present application may include: the microfluidic array comprises m rows and n columns of microfluidic pixel units; m and n are natural numbers; further comprising: one or more input signal shunt circuits connected with the control signal input end of the microfluidic array and x clock signal sources CK for providing clock signals for the one or more input signal shunt circuits; the one or more input signal splitting circuits may include: the column input signal shunting circuit is used for providing a control signal for each connected column of microfluidic pixel units, and/or the row input signal shunting circuit is used for providing a control signal for each connected row of microfluidic pixel units; each input signal shunting circuit is used for shunting an input signal of one control signal source into x sub-signals and then respectively providing control signals for the x rows or x columns of micro-fluidic pixel units; x is a natural number greater than 1 and less than or equal to m; or x is a natural number which is more than 1 and less than or equal to n; the input signal shunting circuit includes: x sub-shunting circuits; the x clock signal sources CK respectively provide clock signals for the x sub-shunting circuits. Through the scheme of the embodiment, the number of input signals can be increased under the condition that the cost is basically kept unchanged and the FPC binding difficulty is basically kept unchanged, and the resolution of the microfluidic array in a unit effective area is increased.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. Other advantages of the present application may be realized and attained by the instrumentalities and combinations particularly pointed out in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the examples serve to explain the principles of the disclosure and not to limit the disclosure.

Fig. 1 is a schematic diagram of a pixel circuit of an active microfluidic chip in the related art;

FIG. 2 is a timing diagram of the driving of the circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of a microfluidic array of m rows and n columns in the related art;

FIG. 4 is a schematic diagram of a microfluidic array circuit including an input signal shunting circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an input signal splitting circuit according to an embodiment of the present application;

FIG. 6 is a specific circuit diagram of an input signal splitting circuit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an input signal shunting circuit according to an embodiment of the present application when the input signal shunting circuit includes two sub-shunting circuits;

FIG. 8 is a schematic circuit diagram of a microfluidic array including the input signal splitting circuit shown in FIG. 7 according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a driving timing sequence of the input signal splitting circuit shown in FIG. 7 according to an embodiment of the present application;

FIG. 10 is a schematic diagram of an input signal splitting circuit including a second TFT according to an embodiment of the present application;

FIG. 11 is a schematic circuit diagram of each of the shunting circuits in FIG. 7 including a second TFT according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a driving timing diagram of the circuit shown in FIG. 11 according to an embodiment of the present application;

fig. 13 is a block diagram of a microfluidic chip according to an embodiment of the present disclosure.

Detailed Description

The present application describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive concept as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.

The embodiment of the present application provides a microfluidic array circuit a, as shown in fig. 4, which may include: the micro-fluidic array 1 comprises m rows and n columns of micro-fluidic pixel units 11; m and n are natural numbers; the method can also comprise the following steps: one or more input signal shunt circuits 2 connected to the control signal input end of the microfluidic array 1 and x clock signal sources CK providing clock signals for the one or more input signal shunt circuits;

the one or more input signal splitting circuits 2 may include: a column input signal shunting circuit 2-2 for providing a control signal for each connected column of microfluidic pixel units 11, and/or a row input signal shunting circuit 2-1 for providing a control signal for each connected row of microfluidic pixel units 11;

each of the input signal shunting circuits 2 is configured to shunt an input signal of a control signal source (e.g., a GATE signal) into x sub-signals and then provide a control signal for the x-row or x-column microfluidic pixel units 11; x is a natural number greater than 1 and less than or equal to m; or x is a natural number which is more than 1 and less than or equal to n; the input signal splitting circuit may include: x sub-shunting circuits; the x clock signal sources CK respectively provide clock signals for the x sub-shunting circuits.

In an exemplary embodiment of the present application, in order to solve the problem caused by the resolution increase of the microfluidic chip, the embodiment of the present application provides a solution: a plurality of circuit cells (i.e., the one or more input signal shunting circuits 2) are connected between a signal (i.e., a control signal of the microfluidic array 1, or an input signal, which may be a scan/data signal) output by an integrated circuit IC (which may be regarded as a control signal source) and the microfluidic array 1. The small circuit unit can amplify signals output by a control signal source (such as a GATE signal), so that the micro-fluidic chip with higher resolution can be driven under the condition that the control signal source is unchanged and the same number of signals are output.

In an exemplary embodiment of the present application, as shown in fig. 5, the input signal splitting circuit 2 may include: x sub-shunting circuits (shown as 21, 22, … …, 2x in fig. 5);

after the signal input end of each sub-shunt circuit is connected, the signal input end of the input signal shunt circuit is formed and is connected with the control signal source (such as a GATE signal);

the signal output terminal of each sub-shunting circuit serves as a sub-signal output terminal (shown as out1, out2, … … and outx in fig. 5) of the input signal shunting circuit, and is connected to the control signal input terminal of one row or one column of the microfluidic pixel units 11.

In the exemplary embodiment of the present application, through the input signal shunting circuit 2, an output signal of one control signal source (i.e., an input signal of the microfluidic array 1, or a control signal) can be divided into x sub-control signals through the x sub-shunting circuits, and the x sub-control signals are respectively transmitted to the x rows or x columns of the microfluidic pixel units 11. Thereby being equivalent to the fact that the number of the control signal sources can be expanded to x times the original number.

In the exemplary embodiment of the present application, the intensity of the output signal of the control signal source may be increased by x times without changing the magnitude of the control signal of each row or each column of the microfluidic pixel units 11. For example, the current is x times larger than the original current.

In an exemplary embodiment of the present application, as shown in fig. 3 (fig. 3 is a microfluidic array 1 with m rows and n columns without using the input signal splitting circuit 2), the microfluidic pixel unit 11 may include: a pixel TFT 111 and a capacitor (storage capacitor) 112;

the gate of the pixel TFT 111 is used as a second control signal input terminal of the pixel TFT 111 and is connected to one sub-signal output terminal of the column input signal shunting circuit 2;

a source or a gate of the pixel TFT 111, one of which is used as a first control signal input terminal of the pixel TFT 111, is connected to a sub-signal output terminal of the row input signal shunting circuit 2; the other is connected in series with the capacitor 112 and then grounded.

In an exemplary embodiment of the present application, 002 is a pad (gold finger) where the data signal is bound to an FPC (flexible circuit board); 001 is the pad (gold finger) where the scan signal is tied to the FPC, and each of 001 and 002 may represent a control signal source.

In an exemplary embodiment of the present application, the microfluidic array 1 with m rows and n columns may include m × n microfluidic pixel units 11, where each microfluidic pixel unit 11 may be configured to need to provide two control signals (for example, a first control signal, that is, the foregoing scan signal, may be provided to the foregoing first control signal input terminal, and a second control signal, that is, the foregoing data signal, may be provided to the foregoing second control signal input terminal), where the microfluidic pixel units 11 in each row may provide the first control signal through the same control signal source or the same shunt circuit, for example, when the pixel TFT is a P-type TFT, the first control signal may be provided to the source of the pixel TFT through the same control signal source or the same shunt circuit; the microfluidic pixel cells 11 of each column may provide the second control signal by the same control signal source, for example, the gate of the pixel TFT may be provided by the same control signal source or the same shunt circuit.

In an exemplary embodiment of the present application, each of the row input signal splitting circuits 2-1 may be configured to split an input signal of one first control signal source into x split signals and then respectively provide the x row microfluidic pixel units with the first control signals;

each column input signal shunting circuit 2-2 may be configured to shunt an input signal of one second control signal source into x shunt signals and then provide second control signals for the x columns of microfluidic pixel units, respectively.

In an exemplary embodiment of the present application, as shown in fig. 6, each of the sub-shunt circuits may include: a first TFT (thin film transistor) T1 (shown, for example, as T1-1, T1-2, T1-3, …, T1-x in FIG. 6);

the grid electrode of the first TFT is respectively connected with a clock signal source CK, one of the source electrode and the drain electrode of the first TFT is used as a signal input end of the sub-shunt circuit, and the other is used as a signal output end of the sub-shunt circuit and is connected between the control signal source and the ith row or jth column microfluidic pixel unit 11; i is a natural number greater than or equal to 1 and less than or equal to m; j is a natural number greater than or equal to 1 and less than or equal to n;

the clock signal sources CK connected to different sub-shunting circuits belonging to the same input signal shunting circuit may all have driving time differences.

In the exemplary embodiment of the present application, the shunting of the output signal of the control signal source may be implemented by at least one TFT in each of the sub-shunting circuits, and as shown by a plurality of first TFTs in fig. 6, when x sub-shunting circuits are included, the entire input signal shunting circuit 2 includes x first TFTs (T1-1, T1-2, T1-3, …, T1-x).

In the exemplary embodiment of the present application, each of the first TFTs is connected to one clock signal (shown as CK1, CK2, …, CKx in fig. 6), respectively.

In the exemplary embodiment of the present application, for one microfluidic array 1, the m rows of microfluidic pixel units 11 may provide a control signal from one control signal source, divide the control signal of 1 control signal source into m sub-control signals through the input signal dividing circuit 2, and input the m sub-control signals to the m rows of microfluidic pixel units 11 respectively, or divide the control signals of a plurality of control signal sources (the number is less than m) into m sub-control signals through the plurality of input signal dividing circuits 2, and input the m sub-control signals to the m rows of microfluidic pixel units 11 respectively.

In the exemplary embodiment of the present application, only a part of the m rows of the microfluidic pixel units 11 may obtain the control signal after shunting the output signal of the control signal source by one or more input signal shunting circuits 2.

In the exemplary embodiment of the present application, for one microfluidic array 1, n columns of microfluidic pixel units 11 may provide a control signal from one control signal source, divide the control signal of 1 control signal source into n sub-control signals through the input signal dividing circuit 2, and input the n sub-control signals to the n columns of microfluidic pixel units 11 respectively, or divide the control signals of a plurality of control signal sources (the number of which is less than n) into n sub-control signals through the plurality of input signal dividing circuits 2, and input the n sub-control signals to the n columns of microfluidic pixel units 11 respectively.

In the exemplary embodiment of the present application, only a part of the rows of the microfluidic pixel units 11 in the n columns of the microfluidic pixel units 11 may obtain the control signal after shunting the output signal of the control signal source through one or more input signal shunting circuits 2.

In the exemplary embodiments of the present application, one microfluidic array 1 may include only one or more row input signal splitting circuits 2-1, only one or more column input signal splitting circuits 2-2, or both at least one row input signal splitting circuit 2-1 and at least one column input signal splitting circuit 2-2.

In the exemplary embodiment of the present application, any one of the TFTs in the input signal shunting circuit 2 may be a P-type TFT or an N-type TFT. That is, the input signal shunting circuit 2 may be arranged using an N-type TFT, a P-type TFT, or an N, P-type TFT mixture.

In the exemplary embodiment of the present application, an embodiment is given below in which any one TFT in the input signal shunting circuit 2 is a P-type TFT, and two sub-shunting circuits are included in the input signal shunting circuit 2.

In an exemplary embodiment of the present application, as shown in fig. 7 and 8, the input signal splitting circuit 2 may include: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; a first TFT in the first sub-shunt circuit is a first P-type TFT T1-P1; the first TFT in the second sub-shunt circuit is a second P-type TFTT 1-P2; (ii) a

The input signal shunting circuit 2 is a row input signal shunting circuit 2-1 of the microfluidic array 1;

the grid electrode of the first P-type TFT T1-1 is connected with a first clock signal source CK1, the source electrode of the first P-type TFT T1-1 is a signal input end of the first sub-shunting circuit, and the drain electrode of the first P-type TFT T1-1 is a signal output end (OUT1) of the first sub-shunting circuit and is connected with a first control signal input end of the ith row of microfluidic pixel units 11; the grid electrode of the second P-type TFT T1-2 is connected with a second clock signal source CK2, the source electrode of the second P-type TFT T1-2 is a signal input end of the second sub-shunting circuit, and the drain electrode of the second P-type TFT is a signal output end (OUT2) of the second sub-shunting circuit and is connected with a first control signal input end of the (i + 1) th row of microfluidic pixel units 11; the source electrode of the first P-type TFTT1-1 is connected with the source electrode of the second P-type TFT T1-2 to serve as a signal input end of the input signal shunting circuit, and the input signal shunting circuit is connected with a control signal source (GATE);

or,

the input signal shunting circuit 2 is a column input signal shunting circuit 2-2 of the microfluidic array 1;

the grid electrode of the first P-type TFT T1-1 is connected with a first clock signal source CK1, the source electrode of the first P-type TFT T1-1 is a signal input end of the first sub-shunting circuit, and the drain electrode of the first P-type TFT T1-1 is a signal output end of the first sub-shunting circuit and is connected with a second control signal input end of the jth column of microfluidic pixel unit 11; the grid electrode of the second P-type TFT T1-2 is connected with a second clock signal source CK2, the source electrode of the second P-type TFT T1-2 is a signal input end of the second sub-shunting circuit, and the drain electrode of the second P-type TFT T1-2 is a signal output end of the second sub-shunting circuit and is connected with a second control signal input end of the (j + 1) th column of microfluidic pixel units 11; and the source electrode of the first P-type TFT T1-1 is connected with the source electrode of the second P-type TFT T1-2 to serve as a signal input end of the input signal shunting circuit and is connected with the control signal source.

In an exemplary embodiment of the present application, the driving timing of this input signal splitting circuit embodiment may be as shown in fig. 9.

In the exemplary embodiment of the present application, when the input signal splitting circuit 2 shown in fig. 8 is used in one microfluidic array 1, the number of the input signal splitting circuits 2 that can be set at most is as follows:

when m is an even number, the microfluidic array circuit may include: 2+ m/2 line input signal shunt circuits; when m is an odd number, the microfluidic array circuit may include: 3+ (m-1)/2 line input signal shunt circuits;

and/or the presence of a gas in the gas,

In the exemplary embodiment of the present application, for the microfluidic array 1 with m rows and n columns, if the input signal shunting circuit 2 is not used, m rows of scanning signals (first control signals) and n columns of data signals (second control signals) are required to drive the microfluidic array to operate normally. If the input signal splitting circuit 2 is used (taking 1 GATE to generate two OUT signals as an example), the required scan signal (first control signal) and data signal (second control signal) will be reduced to 2+ m/2, 2+ n/2, respectively (as shown in fig. 8).

In the exemplary embodiment of the present application, for the row/column amplification circuit (i.e., the row input signal shunting circuit 2-1 and the column input signal shunting circuit 2-2), during operation, when the first TFT is turned off, the output terminals of the sub-shunting circuits (e.g., OUT1 and OUT2) may be in a floating state, which may cause the row/column control signals (the first control signal and the second control signal) input into the microfluidic array 1to be easily interfered by external signals and become unstable. In order to reduce the instability of the control signal caused by turning off the first TFT, a circuit including a plurality of (e.g., 4) TFTs (e.g., second TFTs described below) may be used in each input signal shunting circuit 2 to enhance the circuit stability (see fig. 10 and 11).

In the exemplary embodiment of the present application, as shown in fig. 5 of the input signal shunting circuit 2, x-1 voltage stabilizing circuits may be further provided in each sub-shunting circuit, and the voltage stabilizing circuits are configured to stabilize x-1 sub-shunting circuits except the current sub-shunting circuit when the current sub-shunting circuit is turned on and x-1 sub-shunting circuits except the current sub-shunting circuit are turned off.

In an exemplary embodiment of the present application, x-1 stabilizing circuits in each of the sub-shunt circuits may be constituted by x-1 TFTs.

In an exemplary embodiment of the present application, as shown in fig. 10, the sub-shunting circuit may further include: x-1 second TFTs (i.e., voltage regulator circuits, as shown in fig. 10, T2-1_1, …, T2-1_ x-1, T2-2_1, …, T2-2_ x-2, …, T2-x-1_1, and T2-x-1_2, where 1tox means a shunt circuit);

the gates of the x-1 second TFTs are all connected with the clock signal source CK (shown as CK1, CK2, … and CKx in each self-shunt circuit in fig. 10);

the source and drain electrodes of the x-1 second TFTs are connected with a preset high level H, and one is connected with the sub-shunt circuits except the ith sub-shunt circuit in the x sub-shunt circuits;

the x-1 second TFTs are respectively connected with the signal input ends of x-1 sub-shunt circuits except the ith sub-shunt circuit in the x sub-shunt circuits; the high level H is a level greater than a preset voltage threshold.

In the exemplary embodiment of the present application, the second TFT may be in an on state during the off period of the first TFT, and therefore, the output terminal of the sub-shunting circuit in which the first TFT is in the off state may not be in a floating state, and thus instability caused by signal floating may be avoided.

In the exemplary embodiment of the present application, any one of the TFTs in the input signal shunting circuit 2 including the first TFT and the second TFT may be a P-type TFT or an N-type TFT. That is, the input signal shunting circuit 2 may be arranged using an N-type TFT, a P-type TFT, or an N, P-type TFT mixture.

In the exemplary embodiment of the present application, an embodiment is given below in which any one of the first TFT and the second TFT in the input signal shunting circuit 2 is a P-type TFT, and the input signal shunting circuit 2 includes two sub-shunting circuits, each of which includes one first TFT and one second TFT.

In an exemplary embodiment of the present application, as shown in fig. 11, the input signal splitting circuit may include: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; the second TFT of the first sub-shunting circuit may be a third P-type TFT T3; the TFT of the second sub-shunting circuit may be a fourth P-type TFT T4;

the grid electrodes of the third P-type TFTs T3 are connected with the first clock signal source CK 1;

the source of the third P-type TFT T3 is connected to a preset high level, and the drain of the third P-type TFT T3 may be connected to the signal input terminal of the second sub-shunting circuit;

the gates of the fourth P-type TFTs T4 are all connected to the second clock signal source CK2,

the source of the fourth P-type TFT T4 is connected to a preset high level, and the drain of the fourth P-type TFT T4 may be connected to the signal output terminal of the first sub-shunting circuit.

In an exemplary embodiment of the present application, as shown in fig. 12, a driving timing chart of the circuit shown in fig. 11 is shown.

The embodiment of the present application provides a microfluidic chip B, as shown in fig. 13, which may include the microfluidic array circuit a described in any one of the above.

In the exemplary embodiments of the present application, any of the above-mentioned embodiments of the microfluidic array circuit a is applicable to the microfluidic chip B, and details thereof are not repeated here.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

Claims

1. A microfluidic array circuit comprising: the microfluidic array comprises m rows and n columns of microfluidic pixel units; m and n are natural numbers; it is characterized by also comprising: one or more input signal shunt circuits connected with the control signal input end of the microfluidic array and x clock signal sources CK for providing clock signals for the one or more input signal shunt circuits;

the one or more input signal splitting circuits include: the column input signal shunting circuit is used for providing a control signal for each connected column of microfluidic pixel units, and/or the row input signal shunting circuit is used for providing a control signal for each connected row of microfluidic pixel units;

each input signal shunting circuit is used for shunting an input signal of one control signal source into x sub-signals and then respectively providing control signals for the x rows or x columns of micro-fluidic pixel units; x is a natural number greater than 1 and less than or equal to m; or x is a natural number which is more than 1 and less than or equal to n;

the input signal shunting circuit includes: x sub-shunting circuits; the x clock signal sources CK respectively provide clock signals for the x sub-shunting circuits.

2. The microfluidic array circuit of claim 1,

after the signal input end of each sub-shunt circuit is connected, the signal input end of the input signal shunt circuit is formed and is connected with the control signal source;

3. The microfluidic array circuit of claim 2, wherein each sub-shunting circuit comprises: a first thin film transistor TFT;

4. The microfluidic array circuit of claim 3, wherein the sub-shunting circuit further comprises: x-1 second TFTs;

5. The microfluidic array circuit according to claim 2 or 4, wherein any one of the TFTs in the input signal shunting circuit is a P-type TFT or an N-type TFT.

6. The microfluidic array circuit of claim 3, wherein the input signal shunting circuit comprises: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; a first TFT in the first sub-shunt circuit is a first P-type TFT; a first TFT in the second sub-shunt circuit is a second P-type TFT;

or,

7. The microfluidic array circuit of claim 4, wherein the input signal shunting circuit comprises: 2 sub-shunting circuits; the 2 sub-shunt circuits are respectively a first sub-shunt circuit and a second sub-shunt circuit; the second TFT of the first sub-shunt circuit is a third P-type TFT; the second TFT of the second sub-shunting circuit is a fourth P-type TFT;

wherein the gates of the third P-type TFTs are all connected with a first clock signal source CK1,

the gates of the fourth P-type TFTs are both connected to a second clock signal source CK2,

8. Microfluidic array circuit according to claim 6 or 7,

when m is an even number, the microfluidic array circuit comprises: 2+ m/2 line input signal shunt circuits; when m is an odd number, the microfluidic array circuit comprises: 3+ (m-1)/2 line input signal shunt circuits;

and/or the presence of a gas in the gas,

9. Microfluidic array circuit according to any of claims 1-4,

each row input signal shunting circuit is used for shunting an input signal of a first control signal source into x sub-signals and then respectively providing first control signals for the x row microfluidic pixel units;

each column input signal shunting circuit is used for shunting an input signal of a second control signal source into x sub-signals and then respectively providing second control signals for the x columns of microfluidic pixel units;

the microfluidic pixel cell includes: a pixel TFT and a capacitor;

10. A microfluidic chip comprising the microfluidic array circuit of any one of claims 1-9.