CN111684427B - 高速缓存控制感知的存储器控制器 - Google Patents

高速缓存控制感知的存储器控制器 Download PDF

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Publication number
CN111684427B
CN111684427B CN201880088583.4A CN201880088583A CN111684427B CN 111684427 B CN111684427 B CN 111684427B CN 201880088583 A CN201880088583 A CN 201880088583A CN 111684427 B CN111684427 B CN 111684427B
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China
Prior art keywords
access request
memory
tag
cache
request
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CN201880088583.4A
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Chinese (zh)
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CN111684427A (zh
Inventor
拉温德拉·N·巴尔加瓦
加内什·巴拉里斯南
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201880088583.4A 2017-12-12 2018-09-19 高速缓存控制感知的存储器控制器 Active CN111684427B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/839,700 US10572389B2 (en) 2017-12-12 2017-12-12 Cache control aware memory controller
US15/839,700 2017-12-12
PCT/US2018/051624 WO2019118035A1 (en) 2017-12-12 2018-09-19 Cache control aware memory controller

Publications (2)

Publication Number Publication Date
CN111684427A CN111684427A (zh) 2020-09-18
CN111684427B true CN111684427B (zh) 2025-02-11

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US (1) US10572389B2 (https=)
EP (1) EP3724775B1 (https=)
JP (1) JP7036925B2 (https=)
KR (1) KR102402630B1 (https=)
CN (1) CN111684427B (https=)
WO (1) WO2019118035A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11416395B2 (en) 2018-02-05 2022-08-16 Micron Technology, Inc. Memory virtualization for accessing heterogeneous memory components
US12135876B2 (en) 2018-02-05 2024-11-05 Micron Technology, Inc. Memory systems having controllers embedded in packages of integrated circuit memory
US10782908B2 (en) 2018-02-05 2020-09-22 Micron Technology, Inc. Predictive data orchestration in multi-tier memory systems
US11099789B2 (en) 2018-02-05 2021-08-24 Micron Technology, Inc. Remote direct memory access in multi-tier memory systems
US10880401B2 (en) * 2018-02-12 2020-12-29 Micron Technology, Inc. Optimization of data access and communication in memory systems
US10732897B2 (en) * 2018-07-03 2020-08-04 Western Digital Technologies, Inc. Quality of service based arbitrations optimized for enterprise solid state drives
US11392320B2 (en) 2018-07-03 2022-07-19 Western Digital Technologies, Inc. Quality of service based arbitrations optimized for enterprise solid state drives
US10877892B2 (en) 2018-07-11 2020-12-29 Micron Technology, Inc. Predictive paging to accelerate memory access
US10852949B2 (en) 2019-04-15 2020-12-01 Micron Technology, Inc. Predictive data pre-fetching in a data storage device
US12189535B2 (en) * 2022-12-29 2025-01-07 Advanced Micro Devices, Inc. Tiered memory caching
KR102579319B1 (ko) * 2023-04-19 2023-09-18 메티스엑스 주식회사 캐시 메모리 장치 및 이를 이용하는 캐시 스케줄링 구현 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US6427188B1 (en) * 2000-02-09 2002-07-30 Hewlett-Packard Company Method and system for early tag accesses for lower-level caches in parallel with first-level cache
JP4520788B2 (ja) * 2004-07-29 2010-08-11 富士通株式会社 マルチスレッドプロセッサ
US20090006777A1 (en) * 2007-06-28 2009-01-01 Donley Greggory D Apparatus for reducing cache latency while preserving cache bandwidth in a cache subsystem of a processor
US7680985B2 (en) * 2007-06-28 2010-03-16 International Business Machines Corporation Method and apparatus for accessing a split cache directory
US8341358B1 (en) * 2009-09-18 2012-12-25 Nvidia Corporation System and method for cleaning dirty data in a cache via frame buffer logic
JP2012103826A (ja) * 2010-11-09 2012-05-31 Fujitsu Ltd キャッシュメモリシステム
US20120136857A1 (en) * 2010-11-30 2012-05-31 Advanced Micro Devices, Inc. Method and apparatus for selectively performing explicit and implicit data line reads
US20120144118A1 (en) * 2010-12-07 2012-06-07 Advanced Micro Devices, Inc. Method and apparatus for selectively performing explicit and implicit data line reads on an individual sub-cache basis
US8645762B2 (en) 2010-12-08 2014-02-04 Advanced Micro Devices, Inc. Queue freeze on protocol error
US20120297256A1 (en) 2011-05-20 2012-11-22 Qualcomm Incorporated Large Ram Cache
US8825955B2 (en) * 2011-11-22 2014-09-02 The Regents Of The University Of Michigan Data processing apparatus having a cache configured to perform tag lookup and data access in parallel, and a method of operating the data processing apparatus
US8868843B2 (en) * 2011-11-30 2014-10-21 Advanced Micro Devices, Inc. Hardware filter for tracking block presence in large caches
US9753858B2 (en) * 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
US9535832B2 (en) * 2013-04-30 2017-01-03 Mediatek Singapore Pte. Ltd. Multi-hierarchy interconnect system and method for cache system
US9652397B2 (en) * 2014-04-23 2017-05-16 Texas Instruments Incorporated Dynamic power reduction and performance improvement in caches using fast access
US9779025B2 (en) 2014-06-02 2017-10-03 Micron Technology, Inc. Cache architecture for comparing data

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Publication number Publication date
JP2021506033A (ja) 2021-02-18
US10572389B2 (en) 2020-02-25
US20190179760A1 (en) 2019-06-13
EP3724775A1 (en) 2020-10-21
KR20200096971A (ko) 2020-08-14
KR102402630B1 (ko) 2022-05-26
EP3724775B1 (en) 2022-11-16
CN111684427A (zh) 2020-09-18
WO2019118035A1 (en) 2019-06-20
JP7036925B2 (ja) 2022-03-15

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