CN111681693A - NVDIMM-P controller fused with DDR5LRDIMM chip set and control method - Google Patents
NVDIMM-P controller fused with DDR5LRDIMM chip set and control method Download PDFInfo
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- CN111681693A CN111681693A CN202010453210.1A CN202010453210A CN111681693A CN 111681693 A CN111681693 A CN 111681693A CN 202010453210 A CN202010453210 A CN 202010453210A CN 111681693 A CN111681693 A CN 111681693A
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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Abstract
The invention discloses an NVDIMM-P controller fusing a DDR5LRDIMM chip set and a control method, the controller comprises a chip set and a memory, the memory comprises a DRAM and a high-capacity nonvolatile memory, the chip set comprises a clock command driving module, an address line cross transposition module and a data cache module, after the cross transposition is carried out on the address lines in the data transmission process according to two groups of clock command address signals sent by the clock command driving module, 10 data cache modules carry out corresponding position numbering, simultaneously, a DDR bandwidth conversion method is used for carrying out data caching, data in the clock command driving module are written into the corresponding data cache modules in a data broadcasting mode according to the position numbering of each data cache module, and simultaneously, the state acquisition is carried out, the NVM bus interface has higher transmission bandwidth, and the number of elements is reduced, the transmission quality is improved.
Description
Technical Field
The invention relates to the technical field of memory controllers of computer systems, in particular to an NVDIMM-P controller fusing a DDR5LRDIMM chipset and a control method thereof.
Background
The area of DDR5LRDIMM memory is the same as the area of past LRDIMMs, and NVDIMM-P requires additional controllers and solid state storage media. The controller for centralized control needs to support data width of 80 bits, and the number of pins is large, so that the transmission quality is reduced.
Disclosure of Invention
The invention aims to provide an NVDIMM-P controller fusing a DDR5LRDIMM chip set and a control method, and transmission quality is improved.
In order to achieve the above object, in a first aspect, the present invention provides an NVDIMM-P controller fused with a DDR5LRDIMM chipset, where the NVDIMM-P controller fused with the DDR5LRDIMM chipset includes a chipset and a memory, the chipset includes a clock command driving module, an address line interleaving bit module and a data cache module, the address line interleaving bit module is connected with the clock command driving module and the data cache module, the clock command driving module is bidirectionally connected with the data cache module, and the data cache module is connected with the memory;
the clock command driving module is used for sending two groups of clock command address signals, wherein each group of clock command address signals drives 5 data cache modules;
the address line cross transposition module is used for carrying out address line cross transposition according to the clock command address signal and transmitting the address line cross transposition to the data cache module;
and the data cache module is used for carrying out position numbering according to the signals transmitted by the address line cross transposition module.
The data cache module comprises a first storage channel and a plurality of second storage channels, and the first storage channel and the plurality of second storage channels are connected with the memory;
the first storage channel is used for performing data transmission with the storage host interface by adopting a DDR bandwidth conversion method;
and the second memory channel is used for performing data transmission with the second interface of the memory by adopting a DDR bandwidth conversion method.
The chipset also comprises a programmable code module which is connected with the clock command driving module;
the programmable code module is used for coding the chip set.
The chipset further comprises a data acquisition module, and the data acquisition module is connected with the clock command driving module and the data cache module;
and the data acquisition module is used for carrying out data broadcasting and state reading after the position number of the data cache module is determined.
In a second aspect, the present invention provides a method for controlling an NVDIMM-P controller fused with a DDR5LRDIMM chipset, comprising:
data transmission and positioning are carried out by adopting an address line cross transposition method;
after the position is determined, data broadcasting and status reading are carried out.
The method for performing data transmission and positioning by adopting address line cross transposition comprises the following steps:
after the address lines in the data transmission process are subjected to cross transposition according to two groups of clock command address signals sent by the clock command driving module, the corresponding position numbering is carried out by 10 data cache modules, and simultaneously, the data cache is carried out by using a DDR bandwidth conversion method.
After the position is determined, data broadcasting and state reading are performed, and the method comprises the following steps:
and writing the data in the clock command driving module into the corresponding data cache module in a data broadcasting mode according to the position number of each data cache module, and simultaneously acquiring the state.
The invention relates to an NVDIMM-P controller fusing a DDR5LRDIMM chip set and a control method thereof, wherein the NVDIMM-P controller comprises a chip set and a memory, the chip set comprises a clock command driving module, an address line cross transposition module and a data cache module, after the address line of a data transmission process is subjected to cross transposition according to two groups of clock command address signals sent by the clock command driving module, corresponding position numbering is carried out by 10 data cache modules, simultaneously, data caching is carried out by using a DDR bandwidth conversion method, data in the clock command driving module is written into the corresponding data cache modules in a data broadcasting mode according to the position numbering of each data cache module, and meanwhile, state acquisition is carried out, so that the transmission quality is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an NVDIMM-P controller fused with a DDR5LRDIMM chipset according to the present invention.
FIG. 2 is a schematic diagram illustrating steps of a method for controlling an NVDIMM-P controller integrated with a DDR5LRDIMM chipset according to the present invention.
Fig. 3 is a schematic diagram of address line transposition provided by the present invention.
FIG. 4 is a block diagram of the NVDIMM-P controller fused to the DDR5LRDIMM chipset provided by the present invention.
The device comprises a 1-chip set, a 2-memory, a 3-clock command driving module, a 4-address line cross transposition module, a 5-data cache module, a 51-first storage channel, a 52-second storage channel, a 6-programmable code module and a 7-data acquisition module.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1, the NVDIMM-P controller fused with DDR5LRDIMM chipset 1 according to the present invention includes a chipset 1 and a memory 2, where the chipset 1 includes a clock command driver module 3, an address line interleaving bit module 4 and a data cache module 5, the address line interleaving bit module 4 is connected to the clock command driver module 3 and the data cache module 5, the clock command driver module 3 is bidirectionally connected to the data cache module 5, and the data cache module 5 is connected to the memory 2;
the clock command driving module 3 is configured to send two sets of clock command address signals, where each set of clock command address signals drives 5 data caching modules 5;
the address line cross transposition module 4 is used for carrying out address line cross transposition according to the clock command address signal and transmitting the address line cross transposition to the data cache module 5;
and the data cache module 5 is used for carrying out position numbering according to the signals transmitted by the address line cross transposition module 4.
In the present embodiment, as shown in fig. 4, the chipset 1 and the memory 2 are integrated in a distributed processing manner, thereby reducing the signal transmission length and the load. The memory 2 (ROM) may be a DRAM and a large capacity nonvolatile memory. The chip set 1 only buffers address command signals, the memory 2 also buffers data lines at the same time, and has more effective capacity increasing capability in parallel connection, the memory capacity can only increase to about 4 times of the original capacity, after the address lines of the data transmission process are subjected to cross transposition initialization by two groups of clock command address signals sent by the clock command driving module 3 (RCD), corresponding position numbering is carried out by 10 data cache modules 5 (NVMn DDR PCTRL DB), wherein each group of clock command address signals drives 5 data cache modules 5, meanwhile, the clock command driving module 3 can also write 5 address lines into the 5 data cache modules 5 in a broadcasting mode, the position identification of the 5 data cache modules 5 is realized by adopting a cross transposition mode without increasing pins and without increasing the number of signals of the chip set 1, further ensuring the transmission quality.
Further, the data cache module 5 includes a first storage channel 51 and a plurality of second storage channels 52, and both the first storage channel 51 and the plurality of second storage channels 52 are connected to the memory 2;
the first storage channel 51 is configured to perform data transmission with the host interface of the memory 2 by using a DDR bandwidth conversion method;
the second memory channel 52 is configured to perform data transmission with the second interface of the memory 2 by using a DDR bandwidth conversion method.
In this embodiment, the first memory channel 51 of the data cache module 5 is connected to a host interface of the memory 2 by using a DDR bandwidth conversion circuit, and the memory 2 may further select the second memory channel 52 to be connected to a second interface of the memory 2, where the first memory channel 51 is a first pin (DDR 5), the second memory channel 52 is a second pin (DDR 4/3), the second interface of the memory 2 is all interfaces except the host interface, 4 dies are packaged in the first memory channel 51, two second memory channels 52 may guarantee a DDR5-6400 bandwidth of 6400MB/s, one NAND flash memory and one controller control die, and the second memory channel 52 needs to meet the selection of a data transmission speed. Therefore, in order to ensure the bandwidth of the host interface, the bandwidth of the first storage channel 51 and the bandwidth of the second storage channel 52, which are used for data caching, need to be greater than the bandwidth of the host interface, so as to ensure the transmission speed of data, and further ensure the transmission quality.
Further, the chipset 1 further comprises a programmable code module 6, and the programmable code module 6 is connected with the clock command driving module 3;
the programmable code module 6 is used for encoding the chipset 1.
In this embodiment, the programmable code module 6 is stored in an externally connected SPI flash memory. The flash memory is connected to the clock command driver module 3, and is transmitted to 10 data buffer modules 5 by the clock command driver module 3 during initialization, and the programmable code module 6 can be used for programming and changing the program code of the controller when necessary.
Further, the chipset 1 further includes a data obtaining module 7, and the data obtaining module 7 is connected to the clock command driving module 3 and the data caching module 5;
and the data acquisition module 7 is configured to perform data broadcasting and status reading after the position number of the data cache module 5 is determined.
In this embodiment, after the position numbers of 10 data buffer modules 5 are determined, the data obtaining module 7 transmits the data in the clock command driving module 3 to the data obtaining module 7 in a broadcast manner, and reads the state of the corresponding data obtaining module 7.
Referring to fig. 2, the present invention provides a method for controlling an NVDIMM-P controller fused with a DDR5LRDIMM chipset 1, comprising:
s101, data transmission and positioning are carried out by adopting an address line cross transposition method.
Specifically, after the address lines in the data transmission process are subjected to cross transposition according to two groups of clock command address signals sent by the clock command driving module 3, 10 data cache modules 5 perform corresponding position numbering, and simultaneously, a DDR bandwidth conversion method is used for data caching, wherein in order to not increase the number of interface signals, positions are designated by adopting a mode of exchanging a plurality of address lines, and a specific method of address line cross transposition is shown in fig. 3:
CA13 of No. 0 is connected to a11, CA11 is connected to a13 (CA13 is exchanged with CA 11), CA12 of No. 1 is connected to a11, CA11 is connected to a12 (CA12 is exchanged with CA 11), CA11 of No. 2 is connected to a11 (CA11 is not exchanged), CA9 of No. 3 is connected to a11, CA11 is connected to a9 (CA9 is exchanged with CA 11), CA8 is connected to a11 of No. 4, CA11 is connected to A8 (CA8 is exchanged with CA 11), at initialization, the RCD issues CA0-13=10100_1111_1101_1, and as above, a0-a 0 received by device 0 is 10100_1111_ 0 (a 0 is exchanged with a 0), so device 0 defines its own position as 0 and internally regards a0 as CA0, a0 as CA 0; and the rest is analogized. Therefore, under the condition of not increasing signals, 5 data cache devices can be arranged and identified by using the command address lines CA0-CA13 of the DDR5, and the method is also suitable for transmitting CA0-CA13 of a double-rate data mode
And S102, after the position is determined, data broadcasting and state reading are carried out.
Specifically, according to the position number of each data cache module 5, the data in the clock command driving module 3 is written into the corresponding data cache module 5 in a data broadcasting manner by using the data acquisition module 7, and state acquisition is performed at the same time, so that the NVM driver has a higher NVM transmission bandwidth, the number of components is reduced, and the signal transmission quality is improved
The invention relates to an NVDIMM-P controller fusing a DDR5LRDIMM chip set 1 and a control method thereof, wherein the NVDIMM-P controller comprises a chip set 1 and a memory 2, the chip set 1 comprises a clock command driving module 3, an address line cross transposition module 4 and a data cache module 5, after cross transposition is carried out on address lines in a data transmission process according to two groups of clock command address signals sent by the clock command driving module 3, corresponding position numbering is carried out by 10 data cache modules 5, data caching is carried out by using a DDR bandwidth conversion method, data in the clock command driving module 3 are written into the corresponding data cache modules 5 in a data broadcasting mode according to the position numbering of each data cache module 5, and state acquisition is carried out at the same time, so that the transmission quality is improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. An NVDIMM-P controller fused with a DDR5LRDIMM chipset, the NVDIMM-P controller fused with the DDR5LRDIMM chipset comprises a chipset and a memory, the chipset comprises a clock command driving module, an address line cross over transposition module and a data caching module, the address line cross over transposition module is connected with the clock command driving module and the data caching module, the clock command driving module is bidirectionally connected with the data caching module, and the data caching module is connected with the memory;
the clock command driving module is used for sending two groups of clock command address signals, wherein each group of clock command address signals drives 5 data cache modules;
the address line cross transposition module is used for carrying out address line cross transposition according to the clock command address signal and transmitting the address line cross transposition to the data cache module;
and the data cache module is used for carrying out position numbering according to the signals transmitted by the address line cross transposition module.
2. The NVDIMM-P controller fused with DDR5LRDIMM chipset of claim 1, wherein the data caching module comprises a first memory channel and a plurality of second memory channels, the first memory channel and the plurality of second memory channels each connected with the memory;
the first storage channel is used for performing data transmission with the storage host interface by adopting a DDR bandwidth conversion method;
and the second memory channel is used for performing data transmission with the second interface of the memory by adopting a DDR bandwidth conversion method.
3. The NVDIMM-P controller fused with DDR5LRDIMM chipset of claim 1, wherein the chipset further comprises a programmable code module, the programmable code module connected with the clock command driver module;
the programmable code module is used for coding the chip set.
4. The NVDIMM-P controller fused with DDR5LRDIMM chipset of claim 1, wherein the chipset further comprises a data fetch module, the data fetch module connected with the clock command driver module and the data cache module;
and the data acquisition module is used for carrying out data broadcasting and state reading after the position number of the data cache module is determined.
5. A control method of an NVDIMM-P controller fused with a DDR5LRDIMM chipset is characterized by comprising the following steps:
data transmission and positioning are carried out by adopting an address line cross transposition method;
after the position is determined, data broadcasting and status reading are carried out.
6. The method for controlling the NVDIMM-P controller fused with the DDR5LRDIMM chipset as recited in claim 5, wherein the data transmission and positioning are performed by adopting an address line cross-over method, comprising the following steps:
after the address lines in the data transmission process are subjected to cross transposition according to two groups of clock command address signals sent by the clock command driving module, the corresponding position numbering is carried out by 10 data cache modules, and simultaneously, the data cache is carried out by using a DDR bandwidth conversion method.
7. The method for controlling the NVDIMM-P controller fused with the DDR5LRDIMM chipset of claim 6, wherein the performing data broadcasting and status reading after the position determination comprises:
and writing the data in the clock command driving module into the corresponding data cache module in a data broadcasting mode according to the position number of each data cache module, and simultaneously acquiring the state.
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