CN111681623A

CN111681623A - Time schedule controller, method for generating inter-frame mark of time schedule controller and display device

Info

Publication number: CN111681623A
Application number: CN202010515593.0A
Authority: CN
Inventors: 肖光星
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL China Star Optoelectronics Technology Co Ltd; TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2020-06-09
Filing date: 2020-06-09
Publication date: 2020-09-18
Anticipated expiration: 2040-06-09
Also published as: CN111681623B

Abstract

The application discloses a time schedule controller and a method for generating interframe marks of the time schedule controller. The method comprises the following steps: generating a second DE signal according to the first DE signal under the system clock; acquiring the number of clocks when the second DE signal is at a low level under a system clock; when the number of the clocks is judged to be equal to a preset number threshold value, resetting the number of the clocks and controlling a blanking count value to increase automatically; and setting the interframe mark when the blanking count value is judged to be equal to a preset blanking threshold value. The application provides an inter-frame mark generation mechanism with compatibility and expandability, and can prevent abnormity under the condition of different clock efficiencies.

Description

Time schedule controller, method for generating inter-frame mark of time schedule controller and display device

Technical Field

The application relates to the technical field of display, in particular to a time schedule controller, a method for generating interframe marks of the time schedule controller and a display device.

Background

Most of the current High Definition televisions (UD) and 8k Timing Controllers (TCON) use a video transmission digital interface standard (VBO, V-By-One) interface. The VBO signals decompressed by the current TCON are mostly 74.25Mhz in clock, UD is 8lane VBO, and they will usually constitute a channel from 4lane or 2 lane. If the system uses a 74.25Mhz clock as the system clock, there is a problem of wasting resources, i.e., processing 8 pixels (pixels) per 74.25Mhz clock. FIG. 1 is a diagram illustrating a comparison between a normal frame and an abnormal frame in the prior art, and the left side of the diagram is a normal frame. In general, when switching clock domains, a flag signal is generated in vertical blanking (V-blank) of a current IP (in this application, IP refers to an IP core), and is used for some processing on the IP, such as clearing some registers, etc. However, when the clock signal of the front end signal changes, if the inter-frame flag generation mechanism is not good, the inter-frame flag bit is abnormal, and the de-Blank frame with horizontal blanking (H-Blank, also called line blanking) is mistakenly detected as VS-Blank. Thereby causing the IP not to operate normally when the reception clock changes and the screen to be abnormal as shown in the right of fig. 1.

FIG. 2 is a timing diagram of the decompressed VBO signal. Among them, the DE (data enable) signal is a valid data strobe signal, also called data enable signal, valid data signal, and its representation symbols are various in the liquid crystal display circuit, such as DSP, dspmg, DEN, DE, etc. The DE signal is an active high signal and the corresponding video data signal is considered to be an active data signal during the high level of the DE signal. As can be seen from fig. 2, the lower the RX clock (RX _ CLK) of the front end is, the higher the count of the system clock (SYS _ CLK) of the clock domain of the system, the corresponding DE signal, is constant, and the corresponding low count is increased. Because the VS-blank detection mechanism is realized by counting the number of low levels, if the parameter setting is too small, misoperation is easily caused; on the other hand, if the parameter setting is too large, the data bit width of the DE signal low level counter is increased accordingly, which may cause hardware resources to increase, and thus, the area of an IC (Integrated Circuit) increases, and the cost increases.

Therefore, it is desirable to provide a method for generating TCON inter-frame flags to overcome the above-mentioned drawbacks.

Disclosure of Invention

The application aims to provide a time schedule controller, a method for generating an inter-frame mark of the time schedule controller and a display device, and reduce abnormal conditions generated by the inter-frame mark.

According to a first aspect of the present application, there is provided a method for generating an inter-frame flag of a timing controller, including: s1, generating a second DE signal according to the first DE signal under the system clock; s2, acquiring the number of clocks when the second DE signal is at a low level under a system clock; s3, judging whether the number of the clocks is equal to a preset number threshold, if so, executing a step S4, otherwise, returning to execute the step S2; s4, resetting the number of the clocks and controlling a blanking count value to increase automatically; s5, judging whether the blanking count value is equal to a preset blanking threshold value, if yes, executing a step S6; otherwise, returning to execute the step S4; and S6, setting the interframe flag.

According to a second aspect of the present application, there is provided a timing controller. The method comprises the following steps: the signal generating unit is used for generating a second DE signal according to the first DE signal under the system clock; the clock counting unit is used for acquiring the number of clocks when the second DE signal is at a low level under a system clock; the clock number judging unit is used for judging whether the clock number is equal to a preset number threshold value or not, if so, the blanking count value self-increasing unit is called, and otherwise, the clock counting unit is called; the blanking count value self-increasing unit is used for resetting the number of the clocks and controlling the self-increasing of a blanking count value; the blanking count value judging unit is used for judging whether the blanking count value is equal to a preset blanking threshold value or not, and if so, the flag setting unit is called; otherwise, calling the blanking counting unit; and the mark setting unit is used for setting the interframe marks.

According to a third aspect of the present application, there is provided a display device comprising: at least one processor; and at least one memory for storing one or more computer-executable instructions; wherein the executable instructions, when executed by the processor, cause any of the signal calibration methods in the embodiments of the present application to be performed.

Compared with the prior art, the positive effect of this application lies in: by providing a mechanism for generating interframe marks with better compatibility and expandability, the abnormal conditions generated by the interframe marks are reduced, and the performance of a timing controller is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a comparison between a normal frame and an abnormal frame in the prior art.

FIG. 2 is a timing diagram of the decompressed VBO signal.

Fig. 3 is a flowchart of a method for generating an inter-frame flag of a timing controller according to the present application.

Fig. 4 is a detailed flowchart of an embodiment of a method for generating an inter-frame flag of a timing controller according to the present application.

Fig. 5 is a block diagram of a timing controller according to the present application.

Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present application

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. Unless otherwise specifically limited.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Referring to fig. 3 and 4, fig. 3 is a flowchart illustrating a method for generating an inter-frame flag of a timing controller according to the present invention. Fig. 4 is a detailed flowchart of an embodiment of a method for generating an inter-frame flag of a timing controller according to the present application.

As shown in fig. 3, the present application provides a method for generating an inter-frame flag of a timing controller, the method including:

s1, generating a second DE signal according to the first DE signal under the system clock;

s2, acquiring the number of clocks when the second DE signal is at a low level under a system clock;

s3, judging whether the number of the clocks is equal to a preset number threshold, if so, executing a step S4, otherwise, returning to execute the step S2;

s4, resetting the number of the clocks and controlling a blanking count value to increase automatically;

s5, judging whether the blanking count value is equal to a preset blanking threshold value, if yes, executing a step S6; otherwise, returning to the step S4 to continuously update the blanking count value;

and S6, setting the interframe flag.

Among them, the DE (data enable) signal is a valid data strobe signal, also called data enable signal, valid data signal, and its representation symbols are various in the liquid crystal display circuit, such as DSP, dspmg, DEN, DE, etc. The DE signal is an active high signal and the corresponding video data signal is considered to be an active data signal during the high level of the DE signal.

A detailed explanation is given below of the above methods from S1 to S5 with reference to FIG. 4. The flow representation in fig. 4 using some codes or pseudo codes can be fully understood by those skilled in the art, and therefore, should not be construed as limiting the present application.

With respect to step S1, a second DE signal is generated from the first DE signal at the system clock.

Specifically, the step S1 further includes: in the system clock, if the first DE signal is determined to be at a falling edge, the second DE signal DE _ GEN is generated, i.e., a high level of M clocks is generated. Where M represents the number of horizontal display pixels of video resolution. Taking UD (3840 × 2160) as an example, M produced is 3840. Furthermore, for better observation, the second DE signal DE _ GEN may be correspondingly pulled down.

The number of clocks at the time when the second DE signal is at the low level in the system clock is obtained in step S2.

Specifically, the step S2 further includes: s21, judging whether the second DE signal DE _ GEN is in a low level or not, if so, executing a step S22, otherwise, executing a step S23; s22, when the second DE signal DE _ GEN is at a low level, controlling the clock number DE _ LCNT to increase automatically; and S23, when the second DE signal DE _ GEN is not at low level, resetting the clock number DE _ LCNT and returning to execute the judgment process of the step S21.

In step S22, the self-increment operation refers to incrementing the value of the corresponding operand (i.e., the clock number DE _ LCNT) by 1; the reset operation in step S23 refers to assigning the corresponding operand (i.e., the clock number DE _ LCNT) to zero.

Regarding step S3, it is determined whether the number of clocks is equal to a predetermined number threshold, if yes, step S4 is executed, otherwise, the step S2 is returned to:

specifically, it is determined whether the clock number DE _ LCNT obtained in step S22 is equal to the number threshold DE _ SET, if the clock number DE _ LCNT is equal to the number threshold DE _ SET, step S4 is executed, otherwise, the step S21 is executed again to obtain the clock number. The number threshold DE _ SET is generally SET to a value M, where M represents the number of clocks when the second DE signal is at a high level, i.e., the number of display pixels in the horizontal direction of the video resolution.

The number of clocks is reset with respect to step S4, and a blanking count value is controlled to be incremented.

Specifically, the step S4 further includes: s41, resetting the clock number DE _ LCNT when the clock number DE _ LCNT is equal to the number threshold DE _ SET; s42, controlling the blanking count value V _ BLANK _ LINE _ CNT to increase automatically; s43, determining whether the second DE signal DE _ GEN is at a high level, and if the second DE signal DE _ GEN is at a high level, executing step S44; otherwise, go to the step S5; s44, resets the blanking count value V _ BLANK _ LINE _ CNT, and ends.

The number of times that the number of clocks is equal to the number threshold value is represented by the blanking count value V _ BLANK _ LINE _ CNT, i.e., how many (DE _ LCNT ═ DE _ SET) the number of clocks is represented, and the maximum value is 15 since the number of clocks is generally counted by 4 BIT.

In addition, the reset operation in step S41 refers to assigning the corresponding operand (i.e., the clock number DE _ LCNT) to zero; the self-increment operation in step S42 is to increment the value of the corresponding operand (i.e., the blanking count value V _ BLANK _ LINE _ CNT) by 1; the reset operation in step S44 refers to assigning the corresponding operand (i.e., the blanking count value V _ BLANK _ LINE _ CNT) to zero.

Regarding step S5, determining whether the blanking count value is equal to a preset blanking threshold, if yes, setting an inter-frame flag; otherwise, returning to the step S4 to continue updating the blanking count value:

the step S5 further includes: s51, judging whether the blanking count value V _ BLANK _ LINE _ CNT is equal to the blanking threshold value V _ BLANK _ SET, if so, judging whether the blanking count value V _ BLANK _ LINE _ CNT is equal to the blanking threshold value V _ BLANK _ SET

V _ BLANK _ LINE _ CNT is equal to the blanking threshold V _ BLANK _ SET, then step S6 is executed; otherwise, executing step S52; s52, setting the interframe FLAG VS _ FLAG to 0, and returning to execute the step S42. The blanking threshold V _ BLANK _ SET ranges from 10 to 15.

Regarding step S6, the inter flag is set:

if the blanking count value V _ BLANK _ LINE _ CNT is equal to the blanking threshold V _ BLANK _ SET, the interframe FLAG VS _ FLAG is SET to 1.

The specific principle is as follows.

The corresponding de _ blank _ cnt (number of clocks not shown in the newly generated horizontal direction) is taken according to the formula:

de_blank_cnt＝((M+N)*(1÷Frx))*Fold-(M+N)

where M represents the number of horizontal display pixels of video resolution and N represents the number of horizontal non-display clocks. Frx represents the frequency corresponding to the input clock and Fold corresponds to the resolution corresponding to the system clock. For UD120HZ, if V _ BLANK _ SET is SET to 11 and DE _ GEN is 4400, Frx is 10HZ, i.e. 10 HZ-120 HZ can ensure that the VS _ FLAG mechanism works normally. When the panel is applied, the panel can generate serious flicker, and no application can be realized from Frx to 20 Hz.

The application provides an efficient interframe mark generation method of a time sequence controller (TCON), so that the generation of interframe marks VS _ FLAG has compatibility, and the VS _ FLAG can be normally generated when the frequency is reduced due to the change of compatible RX _ CLK. The interframe mark generating mechanism of the time schedule controller provided by the application has certain expandability, and can prevent abnormity and misoperation under the condition of different clock efficiencies, so that the work of the time schedule controller is more stable.

Referring to fig. 5, fig. 5 is a block diagram of a timing controller according to the present disclosure. As shown in fig. 5, the present application discloses a timing controller 5, including: a signal generating unit 51, configured to generate a second DE signal according to the first DE signal in the system clock; a clock counting unit 52, configured to obtain the number of clocks when the second DE signal is at a low level in the system clock; a clock number determining unit 53, configured to determine whether the number of clocks is equal to a preset number threshold, if so, invoke a blanking count value self-increasing unit 54, otherwise, invoke the clock counting unit 52, and continue to obtain the number of clocks; the blanking count value self-increasing unit 54 is configured to reset the number of clocks and control a blanking count value to self-increase; a blanking count value determining unit 55, configured to determine whether the blanking count value is equal to a preset blanking threshold, and if so, invoke a flag setting unit 56; otherwise, the blanking count unit 54 is invoked; the flag setting unit 56 is configured to set an inter-frame flag.

The timing controller proposed in this embodiment and the method for generating inter-frame flags of the timing controller proposed in the above embodiment belong to the same inventive concept, the specific work flows of the above modules have been described in the foregoing, and technical details that are not described in detail in this embodiment can be referred to the above embodiment, and are not described herein again. And the embodiment has the same beneficial effects as the generation method of the interframe mark of the execution time controller.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 6, the display device 6 includes: at least one processor 61; and at least one memory 62 for storing one or more computer-executable instructions; wherein the executable instructions, when executed by the processor, cause the method for generating the inter-frame flag of the timing controller to be performed. The memory 62 stores a plurality of instructions adapted to be loaded by the processor 61 and to perform the steps of:

s1, generating a second DE signal according to the first DE signal under the system clock; s2, acquiring the number of clocks when the second DE signal is at a low level under a system clock; s3, judging whether the number of the clocks is equal to a preset number threshold, if so, executing a step S4, otherwise, returning to execute the step S2; s4, resetting the number of the clocks and controlling a blanking count value to increase automatically; s5, judging whether the blanking count value is equal to a preset blanking threshold value, if yes, executing a step S6; otherwise, returning to execute the step S4; and S6, setting the interframe flag.

In fig. 6, a processor 61 is taken as an example; the processor 61 and the memory 62 in the display device may be connected by a bus or other means, and the bus connection is exemplified in fig. 6.

The memory 62 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules (for example, the respective modules shown in fig. 5) corresponding to the signal calibration method of the timing controller in the embodiment of the present application. The processor 61 executes various functional applications and data processing of the server by running software programs, instructions and modules stored in the memory 62, that is, implements the above-described method for generating the inter-frame flag of the timing controller.

The memory 62 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system and an application program required by at least one function; the storage data area may store data created according to the use of the display device, and the like.

Further, the memory 62 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 62 may further include memory remotely located from the processor 61, which may be connected to the display device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The display device provided by the embodiment can be used for implementing an efficient method for generating the inter-frame FLAG of the Timing Controller (TCON), so that the generation of the inter-frame FLAG VS _ FLAG has compatibility, and the VS _ FLAG can be normally generated when the frequency is reduced due to the compatible RX _ CLK change. Meanwhile, the inter-frame mark of the time schedule controller has certain expandability, so that the abnormal operation and the misoperation can be prevented under the condition of different clock efficiencies, and the work of the display device is more stable.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The timing controller, the method for generating inter-frame marks thereof, and the display device provided in the embodiments of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A method for generating an inter-frame flag of a timing controller, the method comprising:

s5, judging whether the blanking count value is equal to a preset blanking threshold value, if yes, executing a step S6; otherwise, returning to execute the step S4;

and S6, setting the interframe flag.

2. The method of claim 1, wherein the step S1 further comprises: generating the second DE signal if the first DE signal is determined to be on a falling edge at a system clock.

3. The method of claim 1, wherein the step S2 further comprises:

s21, judging whether the second DE signal is in a low level, if so, executing a step S22, otherwise, executing a step S23;

s22, when the second DE signal is at low level, controlling the number of the clocks to increase automatically;

and S23, when the second DE signal is not at low level, resetting the clock number and returning to execute the step S21.

4. The method of claim 3, wherein the step S3 further comprises: judging whether the number of clocks acquired in the step S22 is equal to the number threshold, if so, executing the step S4, otherwise, returning to execute the step S21.

5. The method of claim 4, wherein the step S4 further comprises:

s41, resetting the number of the clocks when the number of the clocks is equal to the number threshold;

s42, controlling the blanking count value to increase automatically; wherein the blanking count value represents a number of times the number of clocks equals the number threshold;

s43, judging whether the second DE signal is in a high level or not, if so, executing a step S44, otherwise, entering the step S5;

s44, resetting the blank count value, and ending.

6. The method of claim 5, wherein the step S5 further comprises: s51, judging whether the blanking count value is equal to the blanking threshold value, if so, executing the step S6; otherwise, executing step S52; s52, setting the inter-frame flag to 0, and returning to execute the step S42.

7. The method according to claim 1, wherein the blanking threshold in the step S5 is in a range of 10 to 15.

8. The method of claim 1 wherein said quantity threshold of said step S2 is the number of clocks at which said second DE signal is high.

9. A timing controller, comprising:

the signal generating unit is used for generating a second DE signal according to the first DE signal under the system clock;

the clock counting unit is used for acquiring the number of clocks when the second DE signal is at a low level under a system clock;

the clock number judging unit is used for judging whether the clock number is equal to a preset number threshold value or not, if so, the blanking count value self-increasing unit is called, and otherwise, the clock counting unit is called;

the blanking count value self-increasing unit is used for resetting the number of the clocks and controlling the self-increasing of a blanking count value;

the blanking count value judging unit is used for judging whether the blanking count value is equal to a preset blanking threshold value or not, and if so, the flag setting unit is called; otherwise, calling the blanking counting unit;

and the mark setting unit is used for setting the interframe marks.

10. A display device, characterized in that the display device comprises:

at least one processor; and

at least one memory for storing one or more computer-executable instructions;

wherein the executable instructions, when executed by the processor, cause the method of any of claims 1 to 8 to be performed.