CN111681191A

CN111681191A - Color image demosaicing method and system based on FPGA and storage medium

Info

Publication number: CN111681191A
Application number: CN202010391687.1A
Authority: CN
Inventors: 汪俊锋; 朱文佳; 张晓慧
Original assignee: Anhui Bai Cheng Hui Tong Technology Co ltd
Current assignee: Anhui Bai Cheng Hui Tong Technology Co ltd
Priority date: 2020-05-11
Filing date: 2020-05-11
Publication date: 2020-09-18
Anticipated expiration: 2040-05-11
Also published as: CN111681191B

Abstract

The color image demosaicing method, the color image demosaicing system and the storage medium based on the FPGA can solve the technical problem that the reconstructed image quality is poor due to the fact that the correlation among different color channels cannot be effectively utilized for traditional algorithms such as bilinear interpolation. Comprising the following steps implemented by a computer device: s100, determining the arrangement mode of the CFA array; s200, determining whether a color channel of a pixel point in a bayer image is an R channel, a G channel or a B channel; s300, acquiring pixel point information in a neighborhood around a pixel point to be reconstructed; s400, reconstructing a GB color component of the R channel; s500, reconstructing an RB color component of the G channel; and S600, reconstructing the RG color component of the B channel. The invention fully utilizes the correlation and gradient information among different color channels and can reconstruct and obtain a high-quality full-color image. Meanwhile, two pixel points can be processed in one clock period, and the processing speed of the algorithm is obviously improved.

Description

Color image demosaicing method and system based on FPGA and storage medium

Technical Field

The invention relates to the technical field of digital images, in particular to a color image demosaicing method and system based on an FPGA.

Background

For a color image, each pixel point needs to acquire data of three channels of RGB. And image sensors such as CCD and CMOS are used in cooperation with a color filter array CFA, and each pixel point can only obtain color data of one channel in RGB channels, namely an original image in raw format. And reconstructing a full color image aiming at incomplete sampling output by the CFA color channel, namely reconstructing a complete RGB three-color channel of each pixel, namely a demosaicing processing process of the color image. For the traditional algorithms such as bilinear interpolation, the quality of the reconstructed image is not ideal because the correlation between different color channels cannot be effectively utilized.

Disclosure of Invention

The color image demosaicing method and system based on the FPGA can solve the technical problem that reconstructed images are poor in quality due to the fact that correlation among different color channels cannot be effectively utilized for traditional algorithms such as bilinear interpolation.

In order to achieve the purpose, the invention adopts the following technical scheme:

a color image demosaicing method based on an FPGA comprises the following steps:

implementing, by a computer device, the steps of:

s100, determining the arrangement mode of the CFA array;

s200, determining whether a color channel of a pixel point in a bayer image is an R channel, a G channel or a B channel;

s300, acquiring pixel point information in a neighborhood around a pixel point to be reconstructed;

s400, reconstructing a GB color component of the R channel;

s500, reconstructing an RB color component of the G channel;

and S600, reconstructing the RG color component of the B channel.

Further, the S100 determines an arrangement of the CFA array;

the method specifically comprises the following steps:

it is first determined which CFA array the CCD or CMOS image sensor employs: RGGB, GRBG, GBRG, BGGR.

Further, the S200 determines whether a color channel of a pixel point in the bayer image is an R channel, a G channel, or a B channel;

the method specifically comprises the following steps:

and determining whether the color channel corresponding to each pixel point in the input bayer image is an R channel, a G channel or a B channel by counting rows and columns of the input image and combining the corresponding CFA array.

Further, the S300 obtains pixel information in a neighborhood around the pixel to be reconstructed;

the method specifically comprises the following steps:

for an R channel in a bayer image, data of a G channel and data of a B channel of the bayer image need to be reconstructed;

for a G channel in a bayer image, data of an R channel and data of a B channel of the bayer image need to be reconstructed;

for a B channel in a bayer image, data of an R channel and data of a G channel need to be reconstructed;

the method comprises the following steps of processing the pixel points to be reconstructed by utilizing the information of 24 pixel points in total, namely 5 rows and 5 columns around the pixel points to be reconstructed, wherein the method comprises the following steps:

simultaneously acquiring data of a pixel point to be reconstructed and 24 pixel points in the neighborhood of the pixel point in a clock period;

a RAM or FIFO buffer with the size of 5 lines of pixels is arranged in the FPGA, and after the set time delay, the data of 25 pixels are obtained in a pipeline mode in each clock period.

Further, the S400 reconstructs a GB color component of the R channel;

the method specifically comprises the following steps:

reconstructing data of a G component and a B component of an R channel in an original bayer image;

after 24 pixel data of a pixel point to be reconstructed and the neighborhood thereof are obtained, selecting an interpolation parameter, and then carrying out interpolation calculation;

the interpolation parameters and the cached pixel points are in one-to-one correspondence;

setting Xij as an interpolation parameter corresponding to the pixel point Pij, wherein i and j represent the ith row and the jth column in the neighborhood;

for the parameters for reconstructing the G component, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

for the calculation of the B component, the following parameters are chosen:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0。

further, S500, reconstructing an RB color component of the G channel;

the method specifically comprises the following steps:

for the calculation of the R component, if the G channel is in R row and B column, the following parameters are selected:

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

if the G channel is in B row and R column, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

for the calculation of the B component, if the G channel is in R row and B column, the following parameters are selected:

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0。

further, the S600 reconstructs an RG color component of the B channel;

the method specifically comprises the following steps:

for the calculation of the R component, the following parameters were chosen:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0；

for the calculation of the G component, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0。

on the other hand, the invention also discloses a color image demosaicing system based on the FPGA,

the method comprises the following units:

a CFA array arrangement determining unit for determining the arrangement of the CFA array;

the RGB determining unit is used for determining whether the color channel of the pixel point in the bayer image is an R channel, a G channel or a B channel;

the neighborhood pixel information acquisition unit is used for acquiring pixel point information in a neighborhood around a pixel point to be reconstructed;

and the color component reconstruction unit is used for reconstructing a GB color component of the R channel, reconstructing an RB color component of the G channel and reconstructing an RG color component of the B channel.

Meanwhile, the invention also discloses a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and when the computer program is executed by a processor, the color image demosaicing method based on the FPGA is realized.

According to the technical scheme, the color image demosaicing method based on the FPGA fully utilizes correlation and gradient information among different color channels, and can reconstruct and obtain a high-quality full-color image. Meanwhile, two pixel points can be processed in one clock period, and the processing speed of the algorithm is obviously improved.

Drawings

FIG. 1 is a flow chart of a method of the present invention;

FIG. 2 is a schematic diagram of a pixel buffer according to the present invention;

FIG. 3 is a schematic diagram of the structure of interpolation parameters according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

As shown in fig. 1, the color image demosaicing method based on FPGA according to this embodiment includes the following steps implemented by a computer device:

s100, determining the arrangement mode of the CFA array;

s400, reconstructing a GB color component of the R channel;

s500, reconstructing an RB color component of the G channel;

and S600, reconstructing the RG color component of the B channel.

The following detailed description is made with reference to the accompanying drawings:

1. determining the arrangement mode of CFA array

The CFA array has four arrangement modes of RGGB, GRBG, GBRG and BGGR, and firstly, which CFA array is adopted by the CCD or CMOS image sensor is determined.

2. Determining color channels of pixel points in bayer image

By counting rows and columns of the input image and combining the corresponding CFA array, whether the color channel corresponding to each pixel point in the input bayer image is an R channel, a G channel or a B channel can be determined.

3. Obtaining neighborhood pixel information

For an R channel in a bayer image, data of a G channel and data of a B channel of the bayer image need to be reconstructed; for a G channel in a bayer image, data of an R channel and data of a B channel of the bayer image need to be reconstructed; for the B channel in the bayer image, data of its R channel and G channel needs to be reconstructed. In order to obtain a better reconstruction effect, the information of the pixel points in the neighborhood around the pixel point to be reconstructed needs to be fully utilized. The invention utilizes the information of 24 pixels in total in 5 rows and 5 columns around the pixel to be reconstructed to process the pixel to be reconstructed. In order to exert the advantage of parallel processing of the FPGA, the data of the pixel to be reconstructed and the 24 pixels in the neighborhood thereof need to be acquired simultaneously in one clock cycle. Since the image data input to the FPGA is input line by line, it is impossible to acquire 5 lines of pixel data at the same time. Even though buffering is performed by DDR, if DDR is read randomly, efficiency of DDR reading is extremely low, and it is difficult to meet a real-time processing requirement in a video. Therefore, a RAM or FIFO buffer with a pixel size of 5 lines needs to be arranged inside the FPGA, and after a certain time delay, data of 25 pixels can be obtained in a pipeline manner in each clock cycle, as shown in fig. 2, where p33 is a pixel to be reconstructed.

4. Reconstructing GB color component of R channel

For the R channel in the original bayer image, data of its G component and B component needs to be reconstructed. After 24 pixel data of the pixel point to be reconstructed and the neighborhood thereof are obtained, a proper interpolation parameter needs to be selected, and then interpolation calculation is carried out. The structure of the interpolation parameter is shown in fig. 3, and the interpolation parameter corresponds to the pixel points cached in fig. 2 one by one.

For parameters for reconstructing the G component, through simulation and experiment, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

for the calculation of the B component, the following parameters were selected through simulation and experiment:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0；

5. reconstructing RB color components of G channel

Because the G component has two positions in the original image: the R row, B column and B row, R column, because the pixel arrangement of the surrounding neighborhood is different, when reconstructing RB component in G channel, the selected parameters are also different.

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

6. reconstructing RG components of B channels

As described above, for the calculation of the R component, the following parameters are selected:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0；

for the calculation of the G component, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0。

in summary, in the color image demosaicing method based on the FPGA of the embodiment of the present invention, the arrangement manner of the CFA array is determined first, and then interpolation parameters adopted by each channel are reconstructed for different pixel point positions, and the parameters can fully utilize correlation and gradient information between each color channel. And reconstructing a pixel point, wherein pixel information of 5 rows and 5 columns in the surrounding neighborhood is needed, so that a 5-row buffer needs to be designed in the FPGA, so that data of 25 pixel points in total of 5 rows and 5 columns in the surrounding neighborhood of the pixel point to be processed can be simultaneously acquired in one clock cycle. And finally, setting a counter, determining the position of each pixel point in the whole frame of image, and calculating by using a corresponding interpolation parameter.

The color image demosaicing method based on the FPGA fully utilizes the correlation and gradient information among different color channels, and can reconstruct and obtain a high-quality full-color image. Meanwhile, two pixel points can be processed in one clock period, and the processing speed of the algorithm is obviously improved.

On the other hand, the embodiment of the invention discloses a color image demosaicing system based on FPGA,

the method comprises the following units:

It is understood that the system provided by the embodiment of the present invention corresponds to the method provided by the embodiment of the present invention, and the explanation, the example and the beneficial effects of the related contents can refer to the corresponding parts in the method.

The embodiment of the application also provides an electronic device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,

a memory for storing a computer program;

the processor is used for realizing the color image demosaicing method based on the FPGA when executing the program stored in the memory, and the method comprises the following steps:

s100, determining the arrangement mode of the CFA array;

s400, reconstructing a GB color component of the R channel;

s500, reconstructing an RB color component of the G channel;

and S600, reconstructing the RG color component of the B channel.

The communication bus mentioned in the electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the electronic equipment and other equipment.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other Programmable logic devices, discrete Gate or transistor logic devices, or discrete hardware components.

In yet another embodiment provided by the present application, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of any of the above-mentioned FPGA-based color image demosaicing methods.

In yet another embodiment provided by the present application, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform any of the above embodiments of the FPGA-based color image demosaicing method.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A color image demosaicing method based on FPGA is characterized in that: implementing, by a computer device, the steps of:

s100, determining the arrangement mode of the CFA array;

s400, reconstructing a GB color component of the R channel;

s500, reconstructing an RB color component of the G channel;

and S600, reconstructing the RG color component of the B channel.

2. The FPGA-based color image demosaicing method of claim 1, wherein: the S100 determines the arrangement mode of the CFA array;

the method specifically comprises the following steps:

3. The FPGA-based color image demosaicing method of claim 2, wherein: the S200 determines whether the color channel of the pixel point in the bayer image is an R channel, a G channel or a B channel;

the method specifically comprises the following steps:

4. The FPGA-based color image demosaicing method of claim 3, wherein: the S300 acquires pixel point information in the neighborhood around the pixel point to be reconstructed;

the method specifically comprises the following steps:

5. The FPGA-based color image demosaicing method of claim 4, wherein: the S400 reconstructs GB color components of the R channel;

the method specifically comprises the following steps:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

for the calculation of the B component, the following parameters are chosen:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0。

6. the FPGA-based color image demosaicing method of claim 5, wherein: s500, reconstructing an RB color component of the G channel;

the method specifically comprises the following steps:

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝1/2，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝0，x24＝-1，x25＝0；

X31＝-1，x32＝4，x33＝5，x34＝4，x35＝-1；

X41＝0，x42＝-1，x43＝0，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝1/2，x54＝0，x55＝0；

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝-1，x23＝4，x24＝-1，x25＝0；

X31＝1/2，x32＝0，x33＝5，x34＝0，x35＝1/2；

X41＝0，x42＝-1，x43＝4，x44＝-1，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0。

7. the FPGA-based color image demosaicing method of claim 6, wherein: s600, reconstructing an RG color component of a B channel;

the method specifically comprises the following steps:

for the calculation of the R component, the following parameters were chosen:

x11＝0，x12＝0，x13＝-3/2，x14＝0，x15＝0；

X21＝0，x22＝2，x23＝0，x24＝2，x25＝0；

X31＝-3/2，x32＝0，x33＝6，x34＝0，x35＝-3/2；

X41＝0，x42＝2，x43＝0，x44＝2，x45＝0；

X51＝0，x52＝0，x53＝-3/2，x54＝0，x55＝0；

for the calculation of the G component, the following parameters are selected:

x11＝0，x12＝0，x13＝-1，x14＝0，x15＝0；

X21＝0，x22＝0，x23＝2，x24＝0，x25＝0；

X31＝-1，x32＝2，x33＝4，x34＝2，x35＝-1；

X41＝0，x42＝0，x43＝2，x44＝0，x45＝0；

X51＝0，x52＝0，x53＝-1，x54＝0，x55＝0。

8. the color image demosaicing system based on the FPGA is characterized in that:

the method comprises the following units:

9. A computer-readable storage medium characterized by: the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the FPGA-based color image demosaicing method of any of claims 1-7.