CN111679945A - Processor detection method and device and computer readable storage medium - Google Patents
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- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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Abstract
A method and an apparatus for detecting a processor and a computer-readable storage medium are disclosed. The method comprises the following steps: determining parameters stored in a first type register in a detected processor, wherein the parameters stored in the first type register are related to data needing to be processed currently by the detected processor; the operating state of the detected processor is determined based on the parameters stored in the first type of register. The embodiment of the disclosure can conveniently and reliably realize the detection of the interrupt loss, thereby effectively monitoring the interrupt loss condition.
Description
Technical Field
The present disclosure relates to the field of communications technologies, and in particular, to a method and an apparatus for detecting a processor, and a computer-readable storage medium.
Background
The chip can comprise a general processor and a special processor, and the special processor can inform the general processor by means of an interrupt after completing a specific task. In some cases, an interrupt loss (i.e. a special purpose processor completes a specific task but a general purpose processor does not receive a notification) may occur, which may cause an exception of the whole chip, so that it is necessary to perform an interrupt loss detection, and how to implement the interrupt loss detection is a problem to be solved for those skilled in the art.
Disclosure of Invention
The present disclosure is proposed to solve the above technical problems. The embodiment of the disclosure provides a detection method and device of a processor and a computer readable storage medium.
According to an aspect of an embodiment of the present disclosure, there is provided a detection method of a processor, including:
determining parameters stored in a first type register in a detected processor, wherein the parameters stored in the first type register are related to data needing to be processed currently by the detected processor;
and determining the working state of the detected processor based on the parameters stored in the first type register.
According to another aspect of the embodiments of the present disclosure, there is provided a detection apparatus of a processor, including:
the system comprises a first determining module, a second determining module and a control module, wherein the first determining module is used for determining parameters stored in a first type register in a detected processor, and the parameters stored in the first type register are related to data which needs to be processed currently by the detected processor;
and the second determining module is used for determining the working state of the detected processor based on the parameters stored in the first type register determined by the first determining module.
According to still another aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium storing a computer program for executing the detection method of the processor described above.
According to still another aspect of an embodiment of the present disclosure, there is provided an electronic apparatus including:
a processor;
a memory for storing the processor-executable instructions;
the processor is used for reading the executable instruction from the memory and executing the instruction to realize the detection method of the processor.
Based on the detection method and device for the processor, the computer-readable storage medium and the electronic device provided by the above embodiments of the present disclosure, the operating state of the detected processor can be determined based on the parameters, stored in the first type register of the detected processor, related to the data that needs to be processed currently by the detected processor. Generally, before a special purpose processor executes a specific task, data to be processed by the special purpose processor is rapidly changed, and based on this, in the embodiment of the present disclosure, the special purpose processor may be used as a detected processor to detect a change of the data processed by the special purpose processor based on a parameter stored in a first type register in the special purpose processor, so as to obtain an operating state of the special purpose processor, which may characterize whether the special purpose processor has an interrupt loss. Therefore, the embodiment of the disclosure can conveniently and reliably realize the detection of the interrupt loss, so as to effectively monitor the condition of the interrupt loss.
The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.
FIG. 1 is a block diagram of a heterogeneous design of a general purpose processor plus a special purpose processor in an exemplary embodiment of the disclosure.
Fig. 2 is a flowchart illustrating a detection method of a processor according to an exemplary embodiment of the disclosure.
Fig. 3 is a flowchart illustrating a detection method of a processor according to another exemplary embodiment of the present disclosure.
Fig. 4 is a flowchart illustrating a detection method of a processor according to still another exemplary embodiment of the present disclosure.
Fig. 5 is a flowchart illustrating a detection method of a processor according to still another exemplary embodiment of the present disclosure.
Fig. 6 is a flowchart illustrating a detection method of a processor according to still another exemplary embodiment of the present disclosure.
Fig. 7 is a block diagram of a detection device of a processor according to an exemplary embodiment of the present disclosure.
Fig. 8 is a block diagram of a detection apparatus of a processor according to another exemplary embodiment of the present disclosure.
Fig. 9 is a block diagram of a detection device of a processor according to still another exemplary embodiment of the present disclosure.
Fig. 10 is a block diagram of a detection apparatus of a processor according to still another exemplary embodiment of the present disclosure.
Fig. 11 is a block diagram of an electronic device provided in an exemplary embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.
It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.
It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.
In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and the same or similar parts may be referred to each other, so that the descriptions thereof are omitted for brevity.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
The disclosed embodiments may be applied to electronic devices such as terminal devices, computer systems, servers, etc., which are operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well known terminal devices, computing systems, environments, and/or configurations that may be suitable for use with electronic devices, such as terminal devices, computer systems, servers, and the like, include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, microprocessor-based systems, set top boxes, programmable consumer electronics, network pcs, minicomputer systems, mainframe computer systems, distributed cloud computing environments that include any of the above systems, and the like.
Electronic devices such as terminal devices, computer systems, servers, etc. may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. The computer system/server may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.
Summary of the application
Thanks to the recent development of moore's law, the computing power of hardware is becoming more and more powerful, and the tasks that a general-purpose processor can support are also becoming more and more complex, and a general-purpose processor can face hundreds of tasks. However, a general-purpose processor has strong limitations for some specific tasks (such as tasks related to a neural network algorithm), and in order to ensure the flexibility of the general-purpose processor, the general-purpose processor is not optimized for the specific tasks, but a heterogeneous design scheme of the general-purpose processor plus a special-purpose processor is adopted, that is, the general-purpose processor and the special-purpose processor are arranged in a chip at the same time, and the special-purpose processor is specially used for processing the specific tasks, such as the tasks related to the neural network algorithm.
In the heterogeneous design scheme of the general-purpose processor and the special-purpose processor, the general-purpose processor and the special-purpose processor communicate in an interrupt mode, and the special-purpose processor informs the general-purpose processor in the interrupt mode after completing a specific task. In implementing the present disclosure, the inventors found that, in some cases, an interrupt loss occurs, that is, a special purpose processor completes a specific task but a general purpose processor does not receive a notification, and if the interrupt loss of the special purpose processor cannot be effectively detected, an exception may be caused to the entire chip.
Brief description of the drawings
As shown in fig. 1, a chip 10 may include a general-purpose processor 11 and a special-purpose processor 12; the dedicated processor 12 may have a driver, the dedicated processor 12 may exist as a peripheral to the general-purpose processor 11, and the general-purpose processor 11 and the dedicated processor 12 may communicate by way of an interrupt.
When the special purpose processor 12 is responsible for processing neural network algorithm-related tasks, the special purpose processor 12 may also be referred to as an Artificial Intelligence (AI) processor.
The dedicated processor 12 may be the detected processor in embodiments of the present disclosure. In specific implementation, the general-purpose processor 11 may execute the processor detection method in the embodiments of the present disclosure, so as to conveniently and reliably determine whether the special-purpose processor 12 is interrupted or lost; alternatively, a processor may be additionally provided, and the detection method of the processor in the embodiment of the present disclosure is executed by the additionally provided processor, so as to easily and reliably determine whether the dedicated processor 12 has an interrupt loss.
Exemplary method
Fig. 2 is a flowchart illustrating a detection method of a processor according to an exemplary embodiment of the disclosure. The method shown in fig. 2 comprises step 201 and step 202, which are described below.
Here, the detected processor may be a dedicated processor, such as dedicated processor 12 in FIG. 1.
It should be noted that there may be multiple registers in the detected processor, and different registers may be used to store different types of parameters. In step 201, first, a first type register in the detected processor may be screened out according to the type of the parameter used for storage by each register in the detected processor, and then the parameter stored in the screened out first type register may be determined.
Optionally, the parameters stored in the first type register are related to the data currently required to be processed by the detected processor, including but not limited to the following cases: the parameters stored in the first type register are related to the content of data currently required to be processed by the detected processor, the parameters stored in the first type register are related to the data size of the data currently required to be processed by the detected processor, and the parameters stored in the first type register are related to the processing mode (which can be characterized by the information of instructions or functions called in the processing process) of the data currently required to be processed by the detected processor.
At step 202, the operating state of the detected processor is determined based on the parameters stored in the first type register.
Here, there may be two possible cases of the determined operating state of the detected processor based on the parameters stored in the first type register, which are the first type operating state and the second type operating state, respectively; the first type of operating state may be an interrupt loss state (which indicates that the detected processor has an interrupt loss), and the second type of operating state may be a non-interrupt loss state (which indicates that the detected processor has no interrupt loss).
In the embodiment of the disclosure, the working state of the detected processor can be determined based on the parameters which are stored in the first type register in the detected processor and are related to the data which needs to be processed currently by the detected processor. Generally, before a special purpose processor executes a specific task, data to be processed by the special purpose processor is rapidly changed, and based on this, in the embodiment of the present disclosure, the special purpose processor may be used as a detected processor to detect a change of the data processed by the special purpose processor based on a parameter stored in a first type register in the special purpose processor, so as to obtain an operating state of the special purpose processor, which may characterize whether the special purpose processor has an interrupt loss. Therefore, the embodiment of the disclosure can conveniently and reliably realize the detection of the interrupt loss, so as to effectively monitor the condition of the interrupt loss.
As shown in fig. 3, based on the embodiment shown in fig. 2, step 202 may include:
Here, the current processing data of the detected processor may be specifically identified by a label, and at this time, the parameter stored in the first preset register may be a label of the current processing data of the detected processor, and in this case, the first preset register may be referred to as an fc _ head register, and the parameter stored in the first preset register may be referred to as an fc _ head value in this case.
Here, the first preset time period may be 1 second, 2 seconds or other values, which are not listed here.
In step 2022, the change status of the currently processed data within the first preset duration may be determined according to the change status of the parameter stored in the first preset register within the first preset duration; the change state can be used to indicate whether a change occurs, what kind of change occurs, and the like. Specifically, if the parameter stored in the first preset register does not change within the first preset time period, it may be determined that the current processing data does not change within the first preset time period; if the parameter stored in the first preset register changes within the first preset time, it can be determined that the current processing data also changes within the first preset time; if the parameter stored in the first preset register changes 3 times within the first preset duration, it can be determined that the current processing data also changes 3 times within the first preset duration.
In one embodiment, step 2023, comprises:
if the current preprocessing data is not changed within a first preset time length, determining the working state of the detected processor as a first type of working state; otherwise, the working state of the detected processor is determined to be the second type working state.
Generally speaking, before the special processor executes a specific task, the data which needs to be processed by the special processor is changed rapidly, if the current processing data of the special processor as the detected processor is not changed within a first preset time length, which is inconsistent with the situation that the special processor normally processes the specific task, at this time, it can be considered that the special processor is interrupted and lost, then the working state of the special processor can be determined to be a first type working state; otherwise, the operating state of the special purpose processor may be determined to be a second type of operating state.
In the embodiment, the working state of the detected processor can be conveniently and reliably determined based on whether the current processing data changes within the first preset time length.
Of course, the specific implementation of step 2023 is not limited thereto, and for example, the operating state of the processor to be detected may be determined by combining whether the current processing data changes within the first preset time period and the change of the parameter stored in the other register (for example, the second preset register hereinafter).
Therefore, in the embodiment of the disclosure, since the parameters stored in the first preset register can accurately identify the current processing data of the detected processor, the working state of the detected processor can be determined conveniently and reliably through the parameters stored in the first preset register.
As shown in fig. 4, based on the embodiment shown in fig. 2, step 202 may include:
Here, the second preset register may be an instruction length register (which may also be referred to as an inst _ num register), and the parameter stored in the second preset register may be an inst _ num value, which represents the number of instructions (which may also be referred to as an instruction length) for processing the current processing data of the detected processor.
At step 2025, the variation status of the instruction amount in the second preset time period is determined.
Here, the second preset time period may be 1 second, 2 seconds or other values, which are not listed here. Optionally, the first preset duration and the second preset duration may be the same or different, and further, when the first preset duration and the second preset duration are the same, the same timer may be used for timing, or different timers may be used for synchronous timing, and when the first preset duration and the second preset duration are different, the different timers may be used for timing.
In step 2025, the variation state of the instruction number within the second preset time period may be determined according to the variation state of the parameter stored in the second preset register within the second preset time period; the change state can be used to indicate whether a change occurs, what kind of change occurs, and the like. Specifically, if the parameter stored in the second preset register does not change within the second preset time period, it may be determined that the number of instructions does not change within the second preset time period; if the parameter stored in the second preset register changes within the second preset time, it can be determined that the instruction number also changes within the second preset time; if the parameter stored in the second preset register changes 5 times within the second preset duration, it may be determined that the number of instructions also changes 5 times within the second preset duration.
At step 2026, the operating state of the detected processor is determined based on the variation status of the number of instructions within the second preset time period.
In one embodiment, step 2026, comprises:
if the instruction number does not change within a second preset time length, determining the working state of the detected processor as a first type working state; otherwise, the working state of the detected processor is determined to be the second type working state.
Generally speaking, before the special purpose processor finishes executing a specific task, the data which needs to be processed by the special purpose processor is changed rapidly, and the number of instructions for processing different data is often different, so that before the special purpose processor finishes executing the specific task, the number of instructions is also changed rapidly, if the number of instructions is not changed within a second preset time period, which is inconsistent with the situation that the special purpose processor normally processes the specific task, at this time, it can be considered that the special purpose processor is lost due to interruption, and then the working state of the special purpose processor can be determined to be a first kind of working state; otherwise, the operating state of the special purpose processor may be determined to be a second type of operating state.
In this embodiment, since the instruction number can accurately represent the processing mode of the currently processed data of the detected processor, and the processing modes of different data are generally different, the operating state of the detected processor can be determined conveniently and reliably by the change state of the instruction number within the second preset time period.
Of course, the specific implementation of step 2026 is not limited thereto, and for example, the operating state of the detected processor may be determined according to the changing state of the current processing data within the first preset time period and the changing state of the instruction number within the second preset time period, so as to further ensure the reliability of the determination result. Specifically, if the current processing data does not change within a first preset time period and the instruction number does not change within a second preset time period, the working state of the detected processor can be determined to be a first type of working state; otherwise, the operating state of the detected processor can be determined to be the second type of operating state.
Therefore, in the embodiment of the disclosure, the parameter stored in the second preset register can accurately represent the instruction number for processing the current processing data of the detected processor, and the working state of the detected processor can be determined conveniently and reliably through the parameter stored in the second preset register.
As shown in fig. 5, on the basis of the embodiment shown in fig. 1, after step 202, the method may further include:
in step 203, if the detected processor is in the first type of operating state, the interrupt and loss handling operation is executed.
In one embodiment, step 203 comprises:
outputting an interrupt loss alarm signal;
and/or the presence of a gas in the gas,
a signal simulating an interrupt trigger signal sent by a processor to be detected is generated, and the generated signal is sent to a specified receiving element of the interrupt trigger signal.
Here, the interruption loss warning signal may be output in a voice form, a mail form, a short message form, or the like.
Here, the designated receiving element of the interrupt trigger signal may be a general-purpose processor, such as general-purpose processor 11 in fig. 1.
If the working state of the special processor as the detected processor is determined to be the first type working state, which indicates that the special processor is interrupted and lost, in this case, an interruption loss alarm signal can be output to inform relevant personnel of the interruption loss, so that the relevant personnel can check and maintain the special processor in time, in addition, a signal for simulating an interruption trigger signal normally sent to the general processor by the special processor can be generated and provided for the special processor, and thus, even if the interruption loss occurs, the general processor can successfully receive the notification to avoid the abnormality caused by the interruption loss as much as possible.
Therefore, in the embodiment of the disclosure, by executing the processing operation of the interruption loss, the corresponding processing can be performed in time aiming at the interruption loss condition, so as to avoid the adverse effect caused by the interruption loss as much as possible.
In an alternative example, a timer may be maintained in the driver of the general purpose processor. In order to enable detection of an interrupt loss for a special purpose processor (e.g., an AI processor) that is a peripheral to a general purpose processor, the following steps may be performed, as shown in fig. 6:
in step 601, the AI processor is turned on by the general purpose processor.
In step 603, at the starting time of the timer (assuming that the time is 08:00:00), an fc _ head value in an fc _ head register (corresponding to the first preset register in the above) and an inst _ num value in an inst _ num register (corresponding to the second preset register in the above) may be obtained, and the obtained fc _ head value and inst _ num value are recorded.
In step 607, it is determined that the AI processor has an interrupt loss, and an interrupt loss handling operation is performed.
At step 608, it is determined that no interrupt loss has occurred to the AI processor.
It can be seen that, the embodiment of the present disclosure provides a mechanism for detecting an interrupt loss of an AI processor, and whether an interrupt loss occurs in the AI processor can be determined conveniently and reliably by checking whether parameters in an fc _ head register and an inst _ num register in the AI processor change, and corresponding processing is performed, so as to ensure normal communication between the AI processor and a general processor. When the AI processor is turned off, the timer may be turned off accordingly.
In addition, it should be noted that, since the maximum value of the fc _ head value (e.g., 2048) is limited, in the case where the fc _ head value in the fc _ head register is updated faster (for example, the update period is less than 1 millisecond), there is a certain possibility that the timer start time and the timer end time are occurred, and the fc _ head value in the fc _ head register is consistent but a normal interrupt actually occurs (for example, between the timer start time and the timer end time, the fc _ head value in the fc _ head register may experience a change from 100 to 300, 300 to 500, 500 to 700, … …, 80 to 100), and, inst _ num in the inst _ num register is a relatively random value, therefore, there is a certain possibility that the inst _ num value in the inst _ num register is consistent but a normal interrupt occurs at the timing start time and the timing end time of the timer. In view of this, in the embodiment of the present disclosure, between the timing start time and the timing end time of the timer, the recorded fc _ head value and inst _ num value may be cleared when a normal interrupt is detected, so that the fc _ head value and inst _ num value obtained at the timing end time of the timer are subsequently compared with zero, and a comparison result is obviously inconsistent, and therefore, the embodiment of the present disclosure can better avoid that an interrupt loss occurs in the AI processor in a case that the timing start time and the timing end time of the timer, the fc _ head value in the fc _ head register are consistent, and the inst _ num value in the inst _ num register are consistent, so that the accuracy of detecting the interrupt loss can be improved.
Any of the processor detection methods provided by embodiments of the present disclosure may be performed by any suitable device having data processing capabilities, including but not limited to: terminal equipment, a server and the like. Alternatively, the detection method of any one of the processors provided by the embodiments of the present disclosure may be executed by the processor, for example, the processor executes the detection method of any one of the processors mentioned by the embodiments of the present disclosure by calling a corresponding instruction stored in the memory. And will not be described in detail below.
Exemplary devices
Fig. 7 is a schematic structural diagram of a detection device of a processor according to an exemplary embodiment of the present disclosure. The apparatus shown in fig. 7 comprises a first determining module 71 and a second determining module 72.
A first determining module 71, configured to determine a parameter stored in a first type register in the detected processor, where the parameter stored in the first type register is related to data that needs to be processed currently by the detected processor;
a second determining module 72, configured to determine an operating state of the detected processor based on the parameter stored in the register of the first type determined by the first determining module 71.
In an alternative example, based on the embodiment shown in fig. 7, as shown in fig. 8, the second determining module 72 includes:
the first reading submodule 721 is configured to read a parameter stored in a first preset register, where the first preset register is a register in a first class of registers, and the parameter stored in the first preset register is used to identify current processing data of the detected processor;
a first determining submodule 722, configured to determine a change state of the currently processed data identified by the parameter read by the first reading submodule 721 within a first preset time period;
the second determining submodule 723 is configured to determine the operating state of the detected processor based on the change state of the current processing data determined by the first determining submodule 722 within the first preset time period.
In an optional example, the second determining sub-module 723 is specifically configured to determine that the working state of the detected processor is the first type of working state if the current processing data does not change within a first preset time period; otherwise, the working state of the detected processor is determined to be the second type working state.
In an alternative example, based on the embodiment shown in fig. 7, as shown in fig. 9, the second determining module 72 includes:
a second reading submodule 724, configured to read a parameter stored in a second preset register, where the second preset register is a register in the first type of register, the parameter stored in the second preset register is used to represent the number of target instructions, and the number of the target instructions is the number of instructions used for processing currently processed data of the detected processor;
the third determining submodule 725 is configured to determine a change state of the number of instructions represented by the parameter read by the second reading submodule 724 in a second preset time period;
the fourth determining submodule 726 is configured to determine the operating state of the detected processor based on the variation state of the instruction number determined by the third determining submodule 725 within the second preset time period.
In an optional example, the fourth determining submodule 726 is specifically configured to determine that the working state of the detected processor is the first type working state if the instruction number does not change within the second preset time period; otherwise, the working state of the detected processor is determined to be the second type working state.
In an alternative example, based on the embodiment shown in fig. 7, as shown in fig. 10, the apparatus further includes:
an executing module 73, configured to execute the interruption loss processing operation if the operating state of the detected processor determined by the second determining module 72 is the first type operating state.
In an alternative example, the execution module 73 is specifically configured to output an interruption loss warning signal; and/or generating a signal simulating an interrupt trigger signal sent by the detected processor and sending the generated signal to a designated receiving element of the interrupt trigger signal.
Exemplary electronic device
Next, an electronic apparatus according to an embodiment of the present disclosure is described with reference to fig. 11. The electronic device may be either or both of the first device and the second device, or a stand-alone device separate from them, which stand-alone device may communicate with the first device and the second device to receive the acquired input signals therefrom.
FIG. 11 illustrates a block diagram of an electronic device in accordance with an embodiment of the disclosure.
As shown in fig. 11, the electronic device 110 includes one or more processors 1101 and memory 1102.
The processor 1101 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities, and may control other components in the electronic device 110 to perform desired functions.
In one example, the electronic device 110 may further include: an input device 1103 and an output device 1104, which are interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, when the electronic device is a first device or a second device, the input device 1103 can be a microphone or a microphone array. When the electronic device is a stand-alone device, the input device 1103 may be a communication network connector for receiving the acquired input signals from the first device and the second device.
The input device 1103 may also include, for example, a keyboard, a mouse, and the like.
The output device 1104 can output various kinds of information to the outside. The output devices 1104 may include, for example, a display, speakers, a printer, and a communication network and its connected remote output devices, among others.
Of course, for simplicity, only some of the components of the electronic device 110 relevant to the present disclosure are shown in fig. 11, omitting components such as buses, input/output interfaces, and the like. In addition, electronic device 110 may include any other suitable components, depending on the particular application.
Exemplary computer program product and computer-readable storage Medium
In addition to the above-described methods and apparatus, embodiments of the present disclosure may also be a computer program product comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the detection method of the processor according to various embodiments of the present disclosure described in the "exemplary methods" section of this specification above.
The computer program product may write program code for carrying out operations for embodiments of the present disclosure in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, embodiments of the present disclosure may also be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform steps in a detection method of the processor according to various embodiments of the present disclosure described in the "exemplary methods" section above in this specification.
The computer-readable storage medium may take any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The block diagrams of devices, apparatuses, systems referred to in this disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order for the steps of the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be embodied as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.
It is also noted that in the devices, apparatuses, and methods of the present disclosure, each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (10)
1. A method of detection of a processor, comprising:
determining parameters stored in a first type register in a detected processor, wherein the parameters stored in the first type register are related to data needing to be processed currently by the detected processor;
and determining the working state of the detected processor based on the parameters stored in the first type register.
2. The method of claim 1, wherein said determining an operational state of said detected processor based on parameters stored in said first type of register comprises:
reading parameters stored in a first preset register, wherein the first preset register is a register in the first type of register, and the parameters stored in the first preset register are used for identifying current processing data of the detected processor;
determining the change state of the current processing data within a first preset time length;
and determining the working state of the detected processor based on the change state of the current processing data within a first preset time length.
3. The method of claim 2, wherein the determining the working state of the detected processor based on the changing state of the current processing data within a first preset time period comprises:
if the current processing data does not change within a first preset time length, determining the working state of the processor to be detected as a first type working state; otherwise, determining the working state of the detected processor as a second working state.
4. The method of claim 1, wherein said determining an operational state of said detected processor based on parameters stored in said first type of register comprises:
reading parameters stored in a second preset register, wherein the second preset register is a register in the first type of register, the parameters stored in the second preset register are used for representing the number of target instructions, and the number of the target instructions is the number of instructions for processing currently processed data of the detected processor;
determining the change state of the instruction quantity in a second preset time length;
and determining the working state of the detected processor based on the change state of the instruction quantity in a second preset time length.
5. The method of claim 4, wherein the determining the operating state of the detected processor based on the state of change of the number of instructions within a second preset time period comprises:
if the instruction number does not change within a second preset time length, determining that the working state of the detected processor is a first type working state; otherwise, determining the working state of the detected processor as a second working state.
6. The method of any of claims 1-5, wherein after determining the operating state of the detected processor based on the parameters stored in the first type of register, the method further comprises:
and if the working state of the detected processor is the first type of working state, executing the interruption loss processing operation.
7. The method of claim 6, wherein said performing an interrupt loss handling operation comprises:
outputting an interrupt loss alarm signal;
and/or the presence of a gas in the gas,
generating a signal simulating an interrupt trigger signal sent by the detected processor, and sending the generated signal to a designated receiving element of the interrupt trigger signal.
8. A detection apparatus of a processor, comprising:
the system comprises a first determining module, a second determining module and a control module, wherein the first determining module is used for determining parameters stored in a first type register in a detected processor, and the parameters stored in the first type register are related to data which needs to be processed currently by the detected processor;
and the second determining module is used for determining the working state of the detected processor based on the parameters stored in the first type register determined by the first determining module.
9. A computer-readable storage medium, which stores a computer program for executing the detection method of the processor of any one of claims 1 to 7.
10. An electronic device, the electronic device comprising:
a processor;
a memory for storing the processor-executable instructions;
the processor is used for reading the executable instructions from the memory and executing the instructions to realize the detection method of the processor of any one of the claims 1 to 7.
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| CN202010533804.3A CN111679945A (en) | 2020-06-12 | 2020-06-12 | Processor detection method and device and computer readable storage medium |
| US17/344,117 US20210389974A1 (en) | 2020-06-12 | 2021-06-10 | Processor detection method and device and computer-readable storage medium |
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