CN111679788B - NAND memory with auxiliary computing function - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of memories, in particular to a NAND memory with an auxiliary computing function, which comprises: a memory array and a NAND controller; the NAND controller includes: the central interconnection module is connected with the bus interface, the central processing module, the data preprocessing module and the data conversion module; the central processing module comprises: a central processing unit and a read-only memory which are connected with each other; the read-only memory stores a firmware program. The central processing unit calls the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, so that the data transmission quantity of the electronic equipment bus is reduced, and the calculation speed of the electronic equipment bus is improved. The CPU calls the data conversion module to open the computing resources in the NAND controller to the bus interface through the firmware program, so that the computing resources when the NAND controller is idle are fully utilized, and the utilization rate of the system is improved.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a NAND memory with an auxiliary computing function.
Background
With the rise of applications such as big data and cloud computing, there is an increasing demand for large-scale high-speed memories, wherein computer flash memory devices (NAND flash memory, NAND) have great advantages in the memory field due to their large capacity, high speed and low cost. As shown in fig. 1, the conventional NAND memory and the processor (central processing unit, CPU) generally operate in the following manner: the NAND memory is used as an off-chip memory of a computer whose CPU needs to access the NAND memory through a secondary cache.
However, the above prior art has the following technical drawbacks:
in the above conventional scheme, the NAND memory belongs to a larger off-chip device, but is only responsible for storing and transmitting data, so that the utilization rate is low, and the throughput of the computer bus is high, and the throughput of the bus data restricts the speed of the computer, so-called "von neumann bottleneck" is caused.
Disclosure of Invention
The invention aims to provide a NAND memory with an auxiliary calculation function, so as to solve the technical problem of low utilization rate of the NAND memory in the prior art.
The embodiment of the invention provides the following scheme:
according to a first aspect of the present invention, an embodiment of the present invention provides a NAND memory with an auxiliary computing function, including: a memory array and a NAND controller, the memory array and the NAND controller being connected;
the NAND controller includes: the system comprises a central interconnection module, a bus interface connected with the central interconnection module, a central processing module, a data preprocessing module and a data conversion module;
the central processing module comprises: the central processing unit is connected with the central interconnection module;
the read-only memory is used for storing firmware programs;
the central interconnection module is used for receiving data processing instructions sent by the associated electronic equipment through the bus interface and forwarding the data processing instructions to the central processor;
and the central processing unit is used for calling the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, or calling the data conversion module to perform auxiliary calculation on the data corresponding to the data processing instruction.
Preferably, the memory array includes: at least one first ONFI interface (Open NAND Flash Interface, open NAND flash memory interface);
the NAND controller further includes: the system comprises a channel selection module, one or more flash memory control modules and one or more second ONFI interfaces, wherein the channel selection module is respectively connected with the central interconnection module and each flash memory control module, the flash memory control modules are in one-to-one correspondence connection with the second ONFI interfaces, and the first ONFI interfaces and the second ONFI interfaces are in one-to-one correspondence connection to form one or more channels;
the central interconnection module is further configured to receive a control instruction sent by the electronic device through the bus interface, and forward the control instruction to the channel selection module;
the channel selection module is used for distributing a target flash memory control module and a corresponding target channel for the control instruction and sending the control instruction to the target flash memory control module;
the target flash memory control module is used for transmitting the control instruction to the memory array through the target channel and controlling the transmission time of the control instruction in the target channel;
the memory array is further configured to respond to the control instruction after receiving the control instruction.
Preferably, the data processing instruction is a first data conversion instruction;
the memory array is used for storing access data between the memory and the electronic device;
the central processing unit is further used for reading first data from the memory array according to the first data conversion instruction;
the central processing unit is further configured to call the data conversion module to convert the first data from a first type to a second type through the firmware program, where the second type is the same as the type of the bus interface, and the first type is different from the second type;
the central processing unit is further used for forwarding the converted first data to the central interconnection module;
the central interconnection module is further configured to send the converted first data to the electronic device through the bus interface.
Preferably, the data processing instruction is a second data conversion instruction;
the central processing unit is further used for extracting second data from the second data conversion instruction;
the central processing unit is further used for calling the data conversion module through the firmware program and converting the second data from the second type to the first type;
the central processing unit is also used for writing the converted second data into the memory array.
Preferably, the data processing instruction is a data writing instruction;
the central processing unit is also used for extracting third data from the data writing instruction;
the central processing unit is further configured to compress the third data, and write the compressed third data into the memory array.
Preferably, the data processing instruction is a data reading instruction;
the central processing unit is further used for reading fourth data from the memory array according to the data reading instruction;
the central processing unit is further used for calling the data preprocessing module through the firmware program, preprocessing the fourth data, and sending the preprocessed fourth data to the central interconnection module;
and the central interconnection module is further used for sending the preprocessed fourth data to the electronic equipment through the bus interface.
Preferably, the pretreatment includes: at least one of addition, convolution, and power operations.
Preferably, the central processing unit is further configured to delete the target page data in the memory array according to a least recently used algorithm.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the NAND memory with auxiliary computing function of the present invention includes: a memory array and a NAND controller, the memory array and the NAND controller being connected; the NAND controller includes: the system comprises a central interconnection module, a bus interface, a central processing unit, a data preprocessing module and a data conversion module, wherein the bus interface, the central processing unit, the data preprocessing module and the data conversion module are connected with the central interconnection module; the central processing module comprises: the central processing unit is connected with the central interconnection module; the read-only memory is used for storing firmware programs; the central interconnection module is used for receiving data processing instructions sent by the associated electronic equipment through the bus interface and forwarding the data processing instructions to the central processor; and the central processing unit is used for calling the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, or calling the data conversion module to perform auxiliary calculation on the data corresponding to the data processing instruction. The CPU calls the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, so that the operation of the electronic equipment terminal is reduced, the transmission quantity of the data bus of the electronic equipment is reduced, and the calculation speed of the bus of the electronic equipment is improved. And the central processing unit calls the data conversion module to open computing resources in the NAND controller to a bus interface through the firmware program, performs auxiliary computation on data corresponding to the data processing instruction, fully utilizes the computing resources when the NAND controller is idle, and improves the utilization rate of the system.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present description, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a NAND memory and a processor in the prior art;
FIG. 2 is a schematic diagram of a NAND memory with auxiliary computing function according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the embodiments of the present invention.
First embodiment
Referring to fig. 2, fig. 2 is a schematic diagram of a NAND memory with auxiliary computing function according to an embodiment of the invention.
In this embodiment, the NAND memory includes: a memory array and a NAND controller, the memory array and the NAND controller being connected.
The memory array is connected to the NAND controller such that the NAND controller can access stored data in the memory array.
The NAND controller includes: a central interconnect (central interconnect) module, a bus interface connected to the central interconnect module, a central processor, a data preprocessing module, and a data conversion module.
The central processing module comprises: a central processing unit (central processing unit, CPU) and a Read-Only Memory (ROM) connected to each other, the central processing unit being connected to the central interconnect module.
The read-only memory is used for storing firmware programs.
The firmware program is a program written in the read-only memory and serves as the bottommost layer of the most basic work, and an operating system can realize the running action of a specific machine according to the standard device driver through the firmware program. The flash translation (Flash translation layer, FTL) software layer is the core of the firmware program, and the FTL can complete mapping from the logic address space of the central processing unit to the physical address space of the memory array, namely, an address mapping function, and can also realize functions of cache management, address mapping, garbage collection, ECC verification, instruction queue management, data acceleration management, virtual slave, and the like. The central processing unit accesses the firmware program, so that hardware devices in the NAND controller, such as the data preprocessing module and the data conversion module, can be called according to the firmware program.
And the central interconnection module is used for receiving the data processing instruction sent by the associated electronic equipment through the bus interface and forwarding the data processing instruction to the central processor.
The NAND memory is connected with the associated electronic equipment through the bus interface, when the electronic equipment needs to use the NAND memory for storage or operation, a data processing instruction is sent to the NAND memory through the bus interface, the bus interface sends the data processing instruction to the central interconnection module, and the central interconnection module forwards the data processing instruction to the central processor. The bus interface is any one of a high-speed serial computer expansion bus standard (peripheral component interconnect Express, PCI-Express) interface, an industry standard architecture bus (Industrial Standard Architecture, ISA) interface, an expansion industry standard architecture (Enhanced Industry Standard Architecture, EISA) interface, a video electronics standards association (Video Electronics Standards Association, VESA) interface, or an Accelerated Graphics-Port (AGP) interface.
And the central processing unit is used for calling the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, or calling the data conversion module to perform auxiliary calculation on the data corresponding to the data processing instruction.
The central processing module further comprises: a direct Memory Access controller (Direct Memory Access Controller, DMAC) and a Static Random-Access Memory (SRAM). The central processing module is a System-on-a-chip (SOC) with an independent CPU, can access a firmware program in the read-only memory, and can call a hardware device in the NAND controller through the firmware program.
Specifically, the central processing unit will choose to call a data preprocessing module or call the data conversion module according to the type of the data processing instruction. In one aspect, the central processing unit invokes the data preprocessing module to preprocess data corresponding to the data processing instruction through the firmware program, where the preprocessing includes: at least one of addition operation, convolution operation and power operation, because the data volume after pretreatment is far smaller than the data volume before pretreatment, the data after pretreatment is transmitted to the electronic equipment, so that the operation of the electronic equipment end is reduced, the transmission volume of a data bus between the NAND and the electronic equipment is reduced, and the calculation speed of the bus of the electronic equipment is improved. On the other hand, the central processing unit calls the data conversion module through the firmware program to perform type conversion on the data corresponding to the data processing instruction, for example, an on-chip bus protocol (Advanced eXtensible Interface, AXI) command is converted into a PCIE data packet, CPU computing resources in the NAND controller are fully utilized, and when the NAND controller is idle, the NAND controller is used as a slave of the electronic device to assist in computing of the electronic device, so that conversion between two memory spaces is realized, and system efficiency is improved.
In one possible implementation, the memory array includes: one or more first ONFI interfaces. The NAND controller further includes: the system comprises a channel selection module, one or more flash memory control modules and one or more second ONFI interfaces, wherein the channel selection module is respectively connected with the central interconnection module and each flash memory control module, the flash memory control modules are in one-to-one correspondence connection with the second ONFI interfaces, and the first ONFI interfaces and the second ONFI interfaces are in one-to-one correspondence connection to form one or more channels.
The central interconnection module is further configured to receive a control instruction sent by the electronic device through the bus interface, and forward the control instruction to the channel selection module.
The channel selection module is used for distributing a target flash memory control module and a corresponding target channel for the control instruction and sending the control instruction to the target flash memory control module.
The target flash memory control module is used for transmitting the control instruction to the memory array through the target channel and controlling the transmission time of the control instruction in the target channel.
The memory array is further configured to respond to the control instruction after receiving the control instruction.
The ONFI interface can transmit data between the memory array and the NAND controller, one or more channels are formed by one-to-one correspondence connection of the first ONFI interface and the second ONFI interface, each channel can be used for realizing time division multiplexing through the channel selection module, specifically, the central interconnection module forwards a control instruction to the channel selection module when receiving the control instruction through the bus interface, the channel selection module distributes a target flash memory control module and a corresponding target channel for the control instruction, the target flash memory control module belongs to the one or more flash memory control modules, and the target channel belongs to the one or more channels. For the control instruction which can be transmitted in parallel in multiple channels, a multiple-item target channel is allocated for the control instruction, and for the control instruction which can not be transmitted in parallel in multiple channels, a target channel is allocated for the control instruction, and different control instructions can be allocated in different transmission time slots of the same target channel. The channel selection module sends the control instruction to the corresponding target flash memory control module after channel allocation, the target flash memory control module transmits the control instruction to the memory array through the target channel and controls the transmission time of the control instruction in the target channel according to the allocated time slot, wherein the control instruction allocated with a plurality of target channels is split and then transmitted in the plurality of target channels, and the memory array responds to the control instruction after receiving the control instruction, for example, when the control instruction is block erasing or page reading, the corresponding data in the memory array is block erasing or page reading according to the control instruction.
In one possible implementation, the data processing instruction is a first data conversion instruction.
The memory array is used for storing access data between the memory and the electronic device.
The central processing unit is further configured to read first data from the memory array according to the first data conversion instruction.
The central processing unit is further configured to call the data conversion module to convert the first data from a first type to a second type through the firmware program, where the second type is the same as the type of the bus interface, and the first type is different from the second type.
The central processing unit is further configured to forward the converted first data to the central interconnection module.
The central interconnection module is further configured to send the converted first data to the electronic device through the bus interface.
The first data conversion instruction is an instruction for converting first data in the memory array from a first type to a second type, wherein the second type is the same as the type of the bus interface, and the first type is different from the second type, for example, when the bus interface is a PCIE interface, the second type is PCIE data, and the first type is AXI data. The first data conversion instruction is to convert first data in the memory array from AXI data to PCIE data. Specifically, the central processing unit calls the data conversion module through the firmware program, converts the first data from AXI data into PCIE data, and sends the PCIE data to the electronic device through the bus interface through the central interconnection module, so that CPU computing resources in the NAND controller are fully utilized, and when the NAND controller is idle, the NAND controller is used as a slave of the electronic device to assist in computing of the electronic device, so that conversion from AXI memory space to PCIE memory space is achieved, and system efficiency is improved.
In one possible implementation, the data processing instruction is a second data conversion instruction.
The central processing unit is further configured to extract second data from the second data conversion instruction.
The central processing unit is further configured to call the data conversion module through the firmware program, and convert the second data from the second type to the first type.
The central processing unit is also used for writing the converted second data into the memory array.
The second data conversion instruction is an instruction to convert second data in the second data conversion instruction from the second type to the first type, for example, the second data conversion instruction is to convert second data in the memory array from PCIE data to AXI data. Specifically, the central processing unit calls the data conversion module through the firmware program, converts the second data from PCIE data to AXI data, and sends the AXI data to the electronic device through the bus interface by the central interconnection module, so that CPU computing resources in the NAND controller are fully utilized, and when the NAND controller is idle, the NAND controller is used as a slave of the electronic device to assist the electronic device to calculate, thereby realizing conversion from PCIE memory space to AXI memory space and improving system efficiency.
In one possible implementation, the data processing instruction is a data writing instruction.
The central processing unit is further configured to extract third data from the data writing instruction.
The central processing unit is further configured to compress the third data, and write the compressed third data into the memory array.
When the data processing instruction is a data writing instruction, the central processing unit compresses third data after extracting the third data from the data writing instruction, so that the data quantity of the third data is reduced, the storage space in the memory array is saved after writing the compressed third data into the memory array, and the storage quantity of the memory array is increased.
In one possible implementation, the data processing instruction is a data read instruction.
The central processing unit is further configured to read fourth data from the memory array according to the data reading instruction.
The central processing unit is further configured to call the data preprocessing module through the firmware program, perform data preprocessing on the fourth data, and send the preprocessed fourth data to the central interconnection module.
And the central interconnection module is further used for sending the preprocessed fourth data to the electronic equipment through the bus interface.
When the data processing instruction is a data reading instruction, the central processing unit reads fourth data from the memory array, and before the fourth data is sent to the electronic device, the firmware program is used for calling the data and processing module to preprocess the fourth data, for example, when the electronic device is an image processing device, the preprocessing is to convolve, square and the like the image data, and the preprocessed fourth data is sent to the central interconnection module, so that the central interconnection module sends the preprocessed fourth data to the electronic device through the bus interface.
In one possible implementation, the central processor is further configured to delete target page data in the memory array according to a least recently used algorithm (Least Recently Used, LRU), and when the memory space of the memory array is insufficient, take page data having a longest elapsed time since the last access as target page data, and delete the target page data.
The technical scheme provided in the embodiment of the application has at least the following technical effects or advantages:
the NAND memory with the auxiliary computing function of the present embodiment includes: a memory array and a NAND controller, the memory array and the NAND controller being connected; the NAND controller includes: the system comprises a central interconnection module, a bus interface, a central processing unit, a data preprocessing module and a data conversion module, wherein the bus interface, the central processing unit, the data preprocessing module and the data conversion module are connected with the central interconnection module; the central processing module comprises: the central processing unit is connected with the central interconnection module; the read-only memory is used for storing firmware programs; the central interconnection module is used for receiving data processing instructions sent by the associated electronic equipment through the bus interface and forwarding the data processing instructions to the central processor; and the central processing unit is used for calling the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, or calling the data conversion module to perform auxiliary calculation on the data corresponding to the data processing instruction. The central processing unit calls the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, and the preprocessed data is transmitted to the electronic equipment because the preprocessed data size is far smaller than the data size before preprocessing, so that the operation of the electronic equipment terminal is reduced, the transmission amount of a data bus between the NAND and the electronic equipment is reduced, and the calculation speed of the electronic equipment bus is improved. And the central processing unit calls the data conversion module to open computing resources in the NAND controller to a bus interface through the firmware program, performs auxiliary computation on data corresponding to the data processing instruction, fully utilizes the computing resources when the NAND controller is idle, and improves the utilization rate of the system.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (modules, systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (6)
1. A NAND memory with auxiliary computing function, the NAND memory comprising: a memory array and a NAND controller, the memory array and the NAND controller being connected;
the NAND controller includes: the system comprises a central interconnection module, a bus interface connected with the central interconnection module, a central processing module, a data preprocessing module and a data conversion module;
the central processing module comprises: the central processing unit is connected with the central interconnection module;
the read-only memory is used for storing firmware programs;
the central interconnection module is used for receiving data processing instructions sent by the associated electronic equipment through the bus interface and forwarding the data processing instructions to the central processor;
the central processing unit is used for calling the data preprocessing module to preprocess the data corresponding to the data processing instruction through the firmware program, or calling the data conversion module to perform auxiliary calculation on the data corresponding to the data processing instruction;
the memory array includes: one or more first ONFI interfaces;
the NAND controller further includes: the system comprises a channel selection module, one or more flash memory control modules and one or more second ONFI interfaces, wherein the channel selection module is respectively connected with the central interconnection module and each flash memory control module, the flash memory control modules are in one-to-one correspondence with the second ONFI interfaces, and the first ONFI interfaces and the second ONFI interfaces are in one-to-one correspondence to form one or more channels;
the central interconnection module is further configured to receive a control instruction sent by the electronic device through the bus interface, and forward the control instruction to the channel selection module;
the channel selection module is used for distributing a target flash memory control module and a corresponding target channel for the control instruction and sending the control instruction to the target flash memory control module;
the target flash memory control module is used for transmitting the control instruction to the memory array through the target channel and controlling the transmission time of the control instruction in the target channel;
the memory array is further used for responding to the control instruction after receiving the control instruction;
the data processing instruction is a first data conversion instruction;
the memory array is used for storing access data between the memory and the electronic device;
the central processing unit is further used for reading first data from the memory array according to the first data conversion instruction;
the central processing unit is further configured to call the data conversion module to convert the first data from a first type to a second type through the firmware program, where the second type is the same as the type of the bus interface, and the first type is different from the second type;
the central processing unit is further used for forwarding the converted first data to the central interconnection module;
the central interconnection module is further configured to send the converted first data to the electronic device through the bus interface.
2. The memory of claim 1, wherein the data processing instruction is a second data conversion instruction;
the central processing unit is further used for extracting second data from the second data conversion instruction;
the central processing unit is further used for calling the data conversion module through the firmware program and converting the second data from the second type to the first type;
the central processing unit is also used for writing the converted second data into the memory array.
3. The memory of any one of claims 1-2, wherein the data processing instruction is a data write instruction;
the central processing unit is also used for extracting third data from the data writing instruction;
the central processing unit is further configured to compress the third data, and write the compressed third data into the memory array.
4. A memory according to claim 3, wherein the data processing instruction is a data read instruction;
the central processing unit is further used for reading fourth data from the memory array according to the data reading instruction;
the central processing unit is further used for calling the data preprocessing module through the firmware program, preprocessing the fourth data, and sending the preprocessed fourth data to the central interconnection module;
and the central interconnection module is further used for sending the preprocessed fourth data to the electronic equipment through the bus interface.
5. The memory of claim 4, wherein the preprocessing comprises: at least one of an addition operation, a convolution operation, and a power operation.
6. The memory of any of claims 1-2, wherein the central processor is further configured to delete target page data in the memory array according to a least recently used algorithm.
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