CN111669230A - Phased array antenna error correction circuit, system, method, and storage medium - Google Patents

Phased array antenna error correction circuit, system, method, and storage medium Download PDF

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Publication number
CN111669230A
CN111669230A CN201910174067.XA CN201910174067A CN111669230A CN 111669230 A CN111669230 A CN 111669230A CN 201910174067 A CN201910174067 A CN 201910174067A CN 111669230 A CN111669230 A CN 111669230A
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channel
switch
receiving
transmitting
signal
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CN111669230B (en
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潘未庄
孙平
常桂林
常纯晔
张品春
王宁
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Guangzhou Haige Communication Group Inc Co
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Guangzhou Haige Communication Group Inc Co
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/12—Monitoring; Testing of transmitters for calibration of transmit antennas, e.g. of the amplitude or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/20—Monitoring; Testing of receivers
    • H04B17/21—Monitoring; Testing of receivers for calibration; for correcting measurements

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Radio Transmission System (AREA)

Abstract

The present application relates to phased array antenna error correction circuits, systems, methods, and storage media. The circuit includes: the antenna array is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch, and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; an array element in an auxiliary reference receiving channel in the antenna array is connected with the input end of a receiving radio frequency front end in the auxiliary reference receiving channel through a third switch and is connected with the output end of an up-conversion radio frequency front end through the third switch and a second switch; and the processor is connected with the output end of each receiving radio frequency front end of the receiving radio frequency front end circuit and is connected with the input end of the up-conversion radio frequency front end. The circuit reduces the modification cost of the traditional phased array antenna in the error correction process of each receiving channel.

Description

Phased array antenna error correction circuit, system, method, and storage medium
Technical Field
The present application relates to the field of antennas, and more particularly, to a phased array antenna error correction circuit, system, method, and storage medium.
Background
In practical application, various errors of the phased array antenna exist, such as processing errors, installation errors, channel amplitude and phase errors, mutual coupling between array elements, inconsistency of the radiation characteristics of the phased array antenna in all directions and the like. These errors will cause the indexes such as field pattern and beam pointing accuracy of the phased array antenna to be reduced, and the performance of the phased array antenna is seriously affected. Therefore, correcting errors between channels during the service life of the phased array antenna is the key to the normal operation of the phased array antenna.
In the conventional technology, a wireless near field self-correction method is generally adopted to correct errors among channels of a phased array antenna. The specific process is as follows: increase transmission array element and receiving array element at the electric center of phase place of traditional phased array antenna array, through transmission array element transmission correction signal to the realization is rectified the error between the receiving channel in the phased array antenna, receives the correction signal after the transmitting channel transmission through receiving array element, corrects the error between the transmitting channel in the phased array antenna with the realization.
However, because the newly added transmitting array element and receiving array element need to be installed in the phase electrical center of the traditional phased array antenna, the array area is occupied, and the modification cost of the phased array antenna is increased.
Disclosure of Invention
Therefore, it is necessary to provide a circuit, a system, a method and a storage medium for correcting an error of a phased array antenna, aiming at the technical problems that the traditional method occupies an array area and increases the modification cost of the phased array antenna.
A phased array antenna error correction circuit, comprising: the antenna array, a receiving radio frequency front end circuit, a processor and an up-conversion radio frequency front end, wherein each receiving radio frequency front end of the receiving radio frequency front end circuit and an array element in the antenna array form a receiving channel, and one channel is respectively selected from the receiving channels as a reference receiving channel and an auxiliary reference receiving channel;
an array element in the antenna array, which is positioned in the reference receiving channel, is connected with the input end of a receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch;
an array element in the auxiliary reference receiving channel in the antenna array is connected with an input end of a receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with an output end of the up-conversion radio frequency front end through the third switch and the second switch;
the processor is connected with the output end of each receiving radio frequency front end of the receiving radio frequency front end circuit, connected with the input end of the up-conversion radio frequency front end, and used for controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining with a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
A phased array antenna error correction circuit, comprising: the antenna array comprises an antenna array, a transmitting radio frequency front end circuit, a processor and a down-conversion radio frequency front end, wherein each transmitting radio frequency front end of the transmitting radio frequency front end circuit and an array element in the antenna array form a transmitting channel, and one channel is respectively selected from the transmitting channels to serve as a reference transmitting channel and an auxiliary reference transmitting channel;
an array element in the reference transmitting channel in the antenna array is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch, and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch;
an array element in the auxiliary reference transmitting channel in the antenna array is connected with an output end of a transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with an input end of a down-conversion radio frequency front end through the sixth switch and the fifth switch;
the processor is connected with the output end of the down-conversion radio frequency front end, connected with the input end of each transmission radio frequency front end of the transmission radio frequency front end circuit, and used for controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and carrying out error correction on each transmission channel by combining with a transmission correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
A phased array antenna error correction system comprises a phased array antenna error correction circuit used for correcting errors of all receiving channels and a phased array antenna error correction circuit used for correcting errors of all transmitting channels, wherein two phased array antenna error correction circuits share one antenna array.
A method of error correction for a phased array antenna, comprising:
selecting one channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel respectively; the array element in the reference receiving channel is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; the array element in the auxiliary reference receiving channel is connected with the input end of the receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with the output end of the up-conversion radio frequency front end through the third switch and the second switch;
controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
A method of error correction for a phased array antenna, comprising:
selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively; the array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch; controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
selecting one channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel respectively; the array element in the reference receiving channel is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; the array element in the auxiliary reference receiving channel is connected with the input end of the receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with the output end of the up-conversion radio frequency front end through the third switch and the second switch;
controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively; the array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch;
controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
The phased array antenna error correction circuit, system, method, and storage medium provided in this embodiment are based on a phased array antenna, and may perform error correction on each receiving channel by selecting any one of a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel, setting a switch in the reference receiving channel and the auxiliary reference receiving channel, setting a switch at an output end of an up-conversion radio frequency front end, and controlling operating states of the switch in the reference receiving channel, the switch in the auxiliary reference receiving channel, and the switch at the output end of the up-conversion radio frequency front end by a processor, and combining with a received correction signal. In the whole error correction process, a special auxiliary array element is not required to be added in the phased array antenna, the excitation of the receiving correction signal to each receiving channel can be realized by directly utilizing the array element in the existing antenna array, and the change cost of the phased array antenna is reduced. In addition, because the transmitting array element for radiating the receiving correction signal is the array element in the reference receiving channel or the array element in the auxiliary reference receiving channel, and the reference receiving channel and the auxiliary reference receiving channel are any one of the multiple receiving channels of the phased array antenna, the transmitting array element for radiating the receiving correction signal is not required to be arranged in the electrical center of the antenna array, and the modification cost of the traditional phased array antenna is further reduced.
Drawings
Fig. 1 is a schematic diagram of an error correction circuit of a phased array antenna according to an embodiment;
fig. 2 is a schematic diagram of an error correction circuit of a phased array antenna according to another embodiment;
fig. 3 is a schematic diagram of an error correction circuit of a phased array antenna according to an embodiment;
fig. 4 is a schematic diagram of an error correction circuit of a phased array antenna according to another embodiment;
FIG. 5 is a schematic diagram of an error correction system for a phased array antenna according to an embodiment;
fig. 6 is a schematic flowchart of an error correction method for a phased array antenna according to an embodiment;
fig. 7 is a schematic flowchart of an error correction method for a phased array antenna according to another embodiment;
fig. 8 is a schematic flowchart of an error correction method for a phased array antenna according to another embodiment;
fig. 9 is a schematic flowchart of an error correction method for a phased array antenna according to another embodiment;
fig. 10 is a schematic flowchart of an error correction method for a phased array antenna according to another embodiment;
fig. 11 is a flowchart illustrating a method for correcting errors of a phased array antenna according to another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application are further described in detail by the following embodiments in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 is a schematic structural diagram of an error correction circuit of a phased array antenna according to an embodiment. As shown in fig. 1, the phased array antenna error correction circuit may include: the antenna comprises an antenna array 10, a receiving radio frequency front end circuit 11, a processor 12 and an up-conversion radio frequency front end 13, wherein each receiving radio frequency front end of the receiving radio frequency front end circuit 11 and an array element in the antenna array 10 form a receiving channel, and one channel is respectively selected from the receiving channels to be used as a reference receiving channel and an auxiliary reference receiving channel; the array elements in the reference receiving channel in the antenna array 10 are connected to the input end of the receiving rf front end in the reference receiving channel through the first switch S1, and connected to the output end of the up-converting rf front end 13 through the first switch S1 and the second switch S2; the array elements in the antenna array 10 located in the auxiliary reference receive channel are connected to the input end of the receive rf front end in the auxiliary reference receive channel through the third switch S3, and connected to the output end of the up-conversion rf front end 13 through the third switch S3 and the second switch S2; the processor 12 is connected to an output end of each receiving rf front end of the receiving rf front end circuit 11, and connected to an input end of the up-conversion rf front end 13, and configured to control operating states of the first switch S1, the second switch S2, and the third switch S3 according to a working mode of a phased array antenna, and perform error correction on each receiving channel in combination with a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
Specifically, referring to fig. 1, the antenna array 10 may include N array elements, which are used to implement reception of N downlink frequencies and transmission of N uplink frequencies. Wherein N is an integer greater than or equal to 2. Each of the receiving rf front-end circuits 11 may include a low noise amplifier, a mixer, a filter, and an analog-to-digital converter, which are respectively configured to perform low noise amplification, frequency mixing, filtering, and analog-to-digital conversion on the N paths of rf signals received from the antenna array 10 to obtain N paths of low frequency or baseband signals.
Since each receiving rf front end of the receiving rf front end circuit 11 and the array elements in the antenna array 10 form one receiving channel, there are multiple receiving channels in the phased array antenna error correction circuit. In order to perform error correction on each receiving channel, one channel can be arbitrarily selected from a plurality of receiving channels as a reference receiving channel and an auxiliary reference receiving channel; and a first switch S1 is provided in the reference receive channel, a second switch S2 is provided at the output of the up-conversion rf front-end 13, and a third switch S3 is provided in the auxiliary reference receive channel, such that the array elements in the reference receive channel are connected to the input of the receive rf front-end in the reference receive channel through the first switch S1 and to the output of the up-conversion rf front-end 13 through the first switch S1 and the second switch S2, such that the array elements in the auxiliary reference receive channel are connected to the input of the receive rf front-end in the auxiliary reference receive channel through the third switch S3 and to the output of the up-conversion rf front-end 13 through the third switch S3 and the second switch S2. Optionally, the first switch S1, the second switch S2, and the third switch S3 may be single-pole multi-throw switches, and the first switch S1 and the third switch S3 may also be single-pole double-throw switches, which is not limited in this embodiment.
The processor 12 is connected to an output of each receiving rf front end of the receiving rf front end circuit 11 and to an input of the up-conversion rf front end 13 (as shown in fig. 1, the processor 12 is connected to the input of the up-conversion rf front end 13 through a receiving beam synthesizer). When the phased array antenna is powered on and started up, the processor 12 controls the working states of the first switch S1, the second switch S2 and the third switch S3, so that the phased array antenna works in the error acquisition mode, and at the same time, the processor 12 controls the up-conversion radio frequency front end 13 to receive the receiving correction signal. Thus, the receiving correction signal can be radiated out through the array element in the reference receiving channel or the array element in the auxiliary reference receiving channel, and the radiated receiving correction signal is received by other array elements except the radiating receiving correction signal in the antenna array, so that each receiving channel is excited by the receiving correction signal. The processor 12 obtains the error of each receiving channel relative to the reference receiving channel according to the excitation result of each receiving channel. After obtaining the error of each receiving channel relative to the reference receiving channel, the processor 12 controls the operating states of the first switch S1, the second switch S2, and the third switch S3 to operate the phased array antenna in the error correction mode. The processor 12 performs error correction on each receiving channel based on the obtained error of each receiving channel relative to the reference receiving channel. Thus, after the signals received by the antenna array 10 enter each receiving rf front end, the processor may perform error correction on the signals output by the corresponding receiving rf front end according to the error of each receiving channel with respect to the reference receiving channel, and input the corrected signals to the receiving beam synthesizer for beam synthesis. The receiving calibration signal may be a spread spectrum signal, a chirp signal, a single tone signal, or the like.
When the antenna array 10 is simultaneously used for receiving N downlink frequencies and transmitting N uplink frequencies, with continued reference to fig. 1, the phased array antenna error correction circuit may further include: a transmitting radio frequency front end circuit and a down-conversion radio frequency front end. Wherein the transmit rf front-end circuitry and the receive rf front-end circuitry 12 are separated by a transmit-receive isolator. The transceiver isolator can be a diplexer, a duplexer and the like. The transmitting radio frequency front end circuit is connected with the down-conversion radio frequency front end through a transmitting beam combiner.
In summary, by setting switches in the reference receiving channel and the auxiliary reference receiving channel of the phased array antenna error correction circuit and setting a switch at the output end of the up-conversion rf front end 13, the processor 12 controls the operating states of the switches in the reference receiving channel, the switches in the auxiliary reference receiving channel, and the switches at the output end of the up-conversion rf front end 13, and combines the received correction signal, so as to realize error correction for each receiving channel.
It should be noted that fig. 1 only illustrates the first switch S1, the third switch S3 as a single-pole double-throw switch, and the second switch S2 as a single-pole multi-throw switch, and the specific types of the first switch S1, the second switch S2, and the third switch S3 are not specifically limited.
The phased array antenna error correction circuit provided in this embodiment is based on a phased array antenna, and can arbitrarily select one receiving channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel, set a switch in the reference receiving channel and the auxiliary reference receiving channel, set a switch at an output end of an up-conversion radio frequency front end, and perform error correction on each receiving channel by controlling the operating states of the switch in the reference receiving channel, the switch in the auxiliary reference receiving channel, and the switch at the output end of the up-conversion radio frequency front end through a processor and combining with a received correction signal. In the whole error correction process, a special auxiliary array element is not required to be added in the phased array antenna, the excitation of the receiving correction signal to each receiving channel can be realized by directly utilizing the array element in the existing antenna array, and the change cost of the traditional phased array antenna is reduced. In addition, because the transmitting array element for radiating the receiving correction signal is the array element in the reference receiving channel or the array element in the auxiliary reference receiving channel, and the reference receiving channel and the auxiliary reference receiving channel are any one of the multiple receiving channels of the phased array antenna, the transmitting array element for radiating the receiving correction signal is not required to be arranged in the electrical center of the antenna array, and the modification cost of the traditional phased array antenna is further reduced.
In an embodiment, optionally, when the operation mode of the phased array antenna is the error acquisition mode, the processor 12 is further configured to control the operation states of the first switch S1, the second switch S2, and the third switch S3, so that the array element in the reference receiving channel communicates with the up-conversion rf front end 13, and the array element in the auxiliary reference receiving channel communicates with the receiving rf front end in the auxiliary reference receiving channel; the up-conversion radio frequency front end 13 is configured to receive the receive correction signal, perform up-conversion processing on the receive correction signal, output the receive correction signal after the up-conversion processing to an array element in the reference receive channel, and radiate the receive correction signal after the up-conversion processing through the array element in the reference receive channel;
the processor 12 is further configured to receive a first signal through each non-reference receive channel; the first signal is related to a signal radiated by an array element in the reference receiving channel; and controlling the operating states of the first switch S1, the second switch S2, and the third switch S3 so that the array elements in the reference receive channel communicate with the receive rf front end in the reference receive channel and the array elements in the auxiliary reference receive channel communicate with the upconverting rf front end 13;
the up-conversion radio frequency front end 13 is configured to receive the receive correction signal, perform up-conversion processing on the receive correction signal, and output the receive correction signal after the up-conversion processing to an array element in the auxiliary reference receive channel, so that the receive correction signal after the up-conversion processing is radiated by the array element in the auxiliary reference receive channel;
the processor 12 is further configured to receive a second signal through each non-auxiliary reference receive channel; the second signal is related to a signal radiated by an array element in the auxiliary reference receiving channel; and determining a first error of each receive channel relative to the reference receive channel based on the first receive signal, the second receive signal, and the receive correction signal.
The phased array antenna error correction circuit that this embodiment provided, the treater can loop through the array element of reference receiving channel and the array element radiation reception correction signal of supplementary reference receiving channel for receive correction signal can excite each receiving channel, and need not increase dedicated supplementary array element in traditional phased array antenna, realizes receiving correction signal and to each receiving channel's excitation, thereby has reduced the change cost to traditional phased array antenna. In addition, in the error acquisition process, the first error of each receiving channel relative to the reference receiving channel can be determined according to the first signal and the second signal of the excitation results twice and by combining the receiving correction signals, so that the accuracy of the determined error result is improved.
Optionally, when the operation mode of the phased array antenna is the error correction mode, the processor 12 is further configured to control the operation states of the first switch S1, the second switch S2, and the third switch S3, so that the array element in the reference receiving channel communicates with the receiving rf front end in the reference receiving channel, the array element in the auxiliary reference receiving channel communicates with the receiving rf front end in the auxiliary reference receiving channel, and the up-converting rf front end communicates with the beam receiving end; and correcting the errors of the receiving channels according to the first errors of the receiving channels relative to the reference receiving channel.
According to the phased array antenna error correction circuit provided by the embodiment, the processor can control the working state of each switch, so that the working mode of the phased array antenna is switched to the error correction mode from the error acquisition mode, the phased array antenna can be switched between two working modes through the same switch, the number of the switches is reduced, and the change cost of the traditional phased array antenna is further reduced; in addition, since the first error of each receiving channel with respect to the reference receiving channel is determined based on the first signal and the second signal of the two excitation results and in combination with the reception correction signal, the accuracy of the determined first error is improved, thereby improving the accuracy of the error correction result for each receiving channel based on the first error.
The following describes the process of performing error correction on each receiving channel by taking the first switch S1, the third switch S3 as a single-pole double-throw switch, and the second switch S2 as a single-pole 4-throw switch as an example, specifically, refer to fig. 2:
assuming that the receiving channel 1 is selected as a reference receiving channel and the receiving channel 2 is selected as an auxiliary reference receiving channel, the connection relationship of the switches in the phased array antenna error correction circuit is as follows: a common terminal pin of the first switch S1 is connected with a receiving port of the transmitting isolator D1, a pin 2 of the first switch S1 is connected with a pin 2 of the second switch S2, and a pin 3 of the first switch S1 is connected with a receiving radio frequency front end of a reference receiving channel; a pin 1 of the common terminal of the third switch S3 is connected with a receiving port of the transmitting isolator D2, a pin 2 of the third switch S3 is connected with a pin 3 of the second switch S2, and a pin 3 of the third switch S3 is connected with a receiving radio frequency front end of the auxiliary reference receiving channel; a pin 1 at the common end of the second switch S2 is connected with the output end of the upper variable-frequency radio frequency front end 13; and the other N-2 array elements are respectively connected with the corresponding receiving radio frequency front end through the receiving port of the receiving and transmitting isolator and connected with the transmitting radio frequency front end circuit through the transmitting port of the receiving and transmitting isolator.
When the phased array antenna is powered on, the processor 12 controls the common port 1 pin of the first switch S1 to be switched to the 2 pin, the common port 1 pin of the second switch S2 to be switched to the 2 pin, and the common port 1 pin of the third switch S3 to be switched to the 3 pin, so that the array element in the reference receiving channel is communicated with the up-conversion radio frequency front end 13, and the array element in the auxiliary reference receiving channel is communicated with the receiving radio frequency front end in the auxiliary reference receiving channel. Then, the receiving calibration signal is outputted, and the up-conversion RF front end 13 is controlled to receive the receiving calibration signal. Thus, the received calibration signal is radiated out through the second switch S2, the first switch S1 and the array element a1 in the reference receiving channel after being up-converted by the up-conversion rf front end 13, enters the receiving rf front end in each non-reference receiving channel after being received by the array element a 2-array element AN, is processed by the receiving rf front end in each non-reference receiving channel to obtain a first signal, and is output to the processor 12.
Next, the receive calibration signal is turned off, and the processor 12 controls the common terminal 1 pin of the first switch S1 to switch to 3 pins, the common terminal 1 pin of the second switch S2 to switch to 3 pins, and the common terminal 1 pin of the third switch S3 to switch to 2 pins, so that the array element in the reference receive channel communicates with the receive rf front end in the reference receive channel and the array element in the auxiliary reference receive channel communicates with the up-conversion rf front end. Then, the receiving calibration signal is outputted, and the up-conversion RF front end 13 is controlled to receive the receiving calibration signal. Thus, the received calibration signal is radiated out through the second switch S2, the third switch S3 and the array element a2 in the auxiliary reference receiving channel after being up-converted by the up-conversion rf front end 13, and enters the receiving rf front end in each non-auxiliary reference receiving channel after being received by the array element a 1-array element AN, and is processed by the receiving rf front end in each non-auxiliary reference receiving channel to obtain a second signal, which is output to the processor 12. The processor 12 determines a first error for each receive channel relative to a reference receive channel based on the received first signal, the second signal, and the receive correction signal.
Then, the processor 12 controls the common terminal 1 pin of the first switch S1 to switch to 3 pins, the common terminal 1 pin of the second switch S2 to switch to 5 pins, and the common terminal 1 pin of the third switch S3 to switch to 3 pins, so that the array element in the reference receiving channel communicates with the receiving rf front end in the reference receiving channel, the array element in the auxiliary reference receiving channel communicates with the receiving rf front end in the auxiliary reference receiving channel, and the up-conversion rf front end 13 communicates with the beam receiving end. At this time, the processor 12 may perform error correction on the low-frequency or baseband signals output from the receiving rf front ends of the corresponding receiving channels according to the obtained first errors of the N receiving channels with respect to the reference receiving channel, and output the N corrected low-frequency or baseband signals to the receiving beam synthesizer, so that the receiving beam synthesizer synthesizes the N corrected low-frequency or baseband signals into one path of signal, and outputs the synthesized one path of signal to the up-conversion rf front end 13, so that the up-conversion rf front end 13 performs up-conversion on the synthesized one path of low-frequency or baseband signal, and outputs the up-converted rf signal to the beam receiving end.
Optionally, the processor 12 is further configured to determine a second error of each receiving channel relative to the reference receiving channel according to the first signal and the receiving correction signal; determining an error of the reference receive channel relative to the auxiliary reference receive channel based on the second signal and the receive correction signal; and determining a first error of each receiving channel relative to the reference receiving channel according to a second error of each receiving channel relative to the reference receiving channel and an error of the reference receiving channel relative to the auxiliary reference receiving channel.
In the error correction circuit of the phased array antenna provided by this embodiment, since the processor can output the reception correction signal based on the reference reception channel and calculate the second error by using the first signal received by the other non-reference reception channel and the reception correction signal by switching the reference reception channel and the auxiliary reference reception channel, and output the reception correction signal based on the auxiliary reference reception channel and calculate the error of the reference reception channel with respect to the auxiliary reference reception channel by using the second signal received by the other non-auxiliary reference reception channel and the reception correction signal, and determine the first error based on the second error and the error of the reference reception channel with respect to the auxiliary reference reception channel, the accuracy of the determined first error is improved by calculating the third error.
Optionally, the processor 12 is further configured to determine a signal correlation value of each receiving channel according to the first signal and the receiving correction signal; and determining a second error of each receiving channel relative to the reference receiving channel according to the signal correlation value of each receiving channel and the receiving correction signal.
Wherein, the first signal is assumed to be xr (n) ═ xr1(n),xr2(n),...,xrN(n)]TWherein x isr1And (n) is 0, and n is the number of sampling points. The processor 12 may be based on a formula
Figure BDA0001988968350000081
Or comprises
Figure BDA0001988968350000082
Determining the signal correlation value Rx of each receiving channelr(n), wherein i is the serial number of the sampling point, and CR (i) is the receiving correction signal. After obtaining the signal correlation value Rx of each receiving channelrAfter (n), processor 12 formulates a formula
Figure BDA0001988968350000083
Or comprises
Figure BDA0001988968350000084
Determining the respective receiving channelSecond error e relative to reference receiving channelr(n) of (a). Wherein,
Figure BDA0001988968350000085
pr(n)＝[pr1(n),pr2(n),...,prN(n)]Treal is the real part operation and imag is the imaginary part operation.
In the error correction circuit of the phased array antenna provided by this embodiment, the processor may determine the second error of each receiving channel relative to the reference receiving channel based on the signal correlation value between each receiving channel. Because the signal correlation values among the receiving channels can indirectly represent the errors among the receiving channels, the second error of each receiving channel relative to the reference receiving channel is determined by adopting the signal correlation values among the receiving channels, and the accuracy of the result of the determined second error is improved. Optionally, the processor 12 is further configured to determine a signal correlation value of the reference receiving channel and the auxiliary reference receiving channel according to the second signal and the reception correction signal; and determining the error of the reference receiving channel relative to the auxiliary reference receiving channel according to the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel and the receiving correction signal.
Wherein, it is assumed that the second signal is X 'r (n) ═ X'r1(n),x'r2(n),...,x'rN(n)]TWherein, x'r2And (n) is 0, and n is the number of sampling points. The processor 12 may be based on a formula
Figure BDA0001988968350000086
Or comprises
Figure BDA0001988968350000087
Determining the signal correlation value R' x of the reference receiving channel and the auxiliary reference receiving channelr(1) Wherein i is the serial number of the sampling point, and CR (i) is the receiving calibration signal. After obtaining the signal correlation value R' x of each receiving channelr(1) Processor 12 may then formulate a formula
Figure BDA0001988968350000088
Or comprises
Figure BDA0001988968350000089
Determining the error e of the reference reception channel relative to the auxiliary reference reception channelr'(1). Wherein,
Figure BDA0001988968350000091
pr'(1)＝[p'r1(1),p'r2(1)]Treal is the real part operation and imag is the imaginary part operation.
Obtaining a second error e of each receiving channel relative to the reference receiving channelr(n) error e of the sum reference reception channel with respect to the auxiliary reference reception channelr' (1) thereafter, the processor 12 may follow the formula
Figure BDA0001988968350000092
Or comprises
Figure BDA0001988968350000093
Determining a first error E of each receive channel relative to a reference receive channelr(n)。
In the error correction circuit for a phased array antenna provided by this embodiment, the processor may determine an error of the reference receiving channel relative to the auxiliary reference receiving channel based on the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel. Because the signal correlation values among the receiving channels can indirectly represent the errors among the receiving channels, the method for determining the errors of the reference receiving channels relative to the auxiliary reference receiving channels by adopting the signal correlation values of the reference receiving channels and the auxiliary reference receiving channels improves the accuracy of the result of the determined errors.
Fig. 3 is a schematic structural diagram of an error correction circuit of a phased array antenna according to an embodiment. As shown in fig. 3, the phased array antenna error correction circuit may include: the antenna array comprises an antenna array 20, a transmitting radio frequency front end circuit 21, a processor 22 and a down-conversion radio frequency front end 23, wherein each transmitting radio frequency front end of the transmitting radio frequency front end circuit 21 and an array element in the antenna array 20 form a transmitting channel, and one channel is respectively selected from the transmitting channels to be used as a reference transmitting channel and an auxiliary reference transmitting channel; the array elements in the antenna array 20 located in the reference transmit channel are connected to the output end of the transmit rf front end in the reference transmit channel through a fourth switch S4, and connected to the input end of the down-conversion rf front end 23 through the fourth switch S4 and a fifth switch S5; the array elements in the auxiliary reference transmit channel in the antenna array 20 are connected to the output of the transmit rf front end in the auxiliary transmit channel through a sixth switch S6, and connected to the input of the down-conversion rf front end 23 through the sixth switch S6 and the fifth switch S5; the processor 22 is connected to an output end of the down-conversion rf front end 23 (as shown in the figure, the processor 22 is connected to an output end of the down-conversion rf front end 23 through a transmit beam combiner), and is connected to an input end of each transmit rf front end of the transmit rf front end circuit 21, and is configured to control operating states of the fourth switch S4, the fifth switch S5, and the sixth switch S6 according to an operating mode of a phased array antenna, and perform error correction on each transmit channel in combination with a transmit correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
Specifically, referring to fig. 3, the antenna array 20 may include N array elements for receiving N downlink frequencies and transmitting N uplink frequencies. Wherein N is an integer greater than or equal to 2. Each of the transmitting rf front-end circuits 21 may include a digital-to-analog converter, a mixer, a filter, a power amplifier, and the like, and is respectively configured to perform digital-to-analog conversion, frequency mixing, filtering, power amplification, and the like on the obtained N low-frequency or baseband signals to obtain N rf signals, so as to radiate the N array elements of the antenna array 20.
Since each rf front end of the rf front end circuit 21 and the array elements in the antenna array 20 form one transmission channel, there are multiple transmission channels in the phased array antenna error correction circuit. In order to perform error correction on each transmitting channel, one channel can be arbitrarily selected from a plurality of transmitting channels to be used as a reference transmitting channel and an auxiliary reference transmitting channel; and a fourth switch S4 is provided in the reference transmit channel, a fifth switch S5 is provided at the input end of the down-conversion rf front-end 23, and a sixth switch S6 is provided in the auxiliary reference transmit channel, so that the array element in the reference transmit channel is connected to the output end of the transmit rf front-end in the reference transmit channel through the fourth switch S4 and is connected to the input end of the down-conversion rf front-end 23 through the fourth switch S4 and the fifth switch S5, so that the array element in the auxiliary reference transmit channel is connected to the output end of the transmit rf front-end in the auxiliary reference transmit channel through the sixth switch S6 and is connected to the input end of the down-conversion rf front-end 23 through the sixth switch S6 and the fifth switch S5. Optionally, the fourth switch S4, the fifth switch S5, and the sixth switch S6 may be single-pole multi-throw switches, and the fourth switch S4 and the sixth switch S6 may also be single-pole double-throw switches, which is not limited in this embodiment.
The processor 22 is connected to an input of each rf front end of the rf front end circuits 11 and to an output of the down-conversion rf front end 23. When the phased array antenna is powered on and started up, the processor 22 controls the operating states of the fourth switch S4, the fifth switch S5 and the sixth switch S6, so that the phased array antenna operates in the error acquisition mode, and at the same time, the processor 22 controls each transmitting radio frequency front end in each non-reference transmitting channel or each transmitting radio frequency front end in each non-auxiliary reference transmitting channel to receive and transmit the correction signal. Thus, the emission correction signal can be radiated through the array elements in each non-reference emission channel or the array elements in each non-auxiliary reference emission channel, and the radiated emission correction signal is received by the array elements in the reference emission channels or the array elements in the auxiliary reference emission channels in the antenna array, so that each emission channel is excited by the emission correction signal. The processor 22 obtains the error of each transmitting channel relative to the reference transmitting channel according to the excitation result of each transmitting channel. After obtaining the error of each transmitting channel relative to the reference transmitting channel, the processor 12 controls the operating states of the fourth switch S4, the fifth switch S5 and the sixth switch S6, so that the phased array antenna operates in the error correction mode. The processor 22 performs error correction on each transmit channel based on the obtained error of each transmit channel relative to the reference transmit channel.
When the antenna array 20 is simultaneously used for receiving the N downlink frequencies and transmitting the N uplink frequencies, with continued reference to fig. 3, the phased array antenna error correction circuit may further include: a receiving radio frequency front end circuit and an up-conversion radio frequency front end. The receiving radio frequency front-end circuit and the transmitting radio frequency front-end circuit are separated by a receiving isolator and a transmitting isolator. The transceiver isolator can be a diplexer, a duplexer and the like. The receiving radio frequency front end circuit is connected with the up-conversion radio frequency front end through a receiving beam synthesizer.
In summary, by setting switches in the reference transmission channel and the auxiliary reference transmission channel of the phased array antenna error correction circuit, and setting a switch at the input end of the down-conversion rf front end 23, the processor 22 controls the operating states of the switch in the reference transmission channel, the switch in the auxiliary reference transmission channel, and the switch at the input end of the down-conversion rf front end 23, and combines the transmission correction signal, the error correction for each transmission channel can be realized.
The phased array antenna error correction circuit provided by this embodiment is based on a phased array antenna, and can arbitrarily select one transmission channel from a plurality of transmission channels of the phased array antenna as a reference transmission channel and an auxiliary reference transmission channel, set a switch in the reference transmission channel and the auxiliary reference transmission channel, set a switch at an input end of a down-conversion radio frequency front end, control the working states of the switch in the reference transmission channel, the switch in the auxiliary reference transmission channel, and the switch at the input end of the down-conversion radio frequency front end through a processor, and perform error correction on each transmission channel by combining with a transmission correction signal. In the whole error correction process, a special auxiliary array element is not required to be added in the phased array antenna, the excitation of the emission correction signal to each emission channel can be realized by directly utilizing the array elements in the existing antenna array, and the change cost of the traditional phased array antenna is reduced. In addition, because the transmitting array element for radiating the transmitting correction signal and the receiving array element for receiving the radiated transmitting correction signal are the array elements in the existing antenna array, the transmitting array element and the receiving array element do not need to be arranged in the electrical center of the antenna array, and the modification cost of the traditional phased array antenna is further reduced.
In an embodiment, optionally, when the operation mode of the phased array antenna is the error acquisition mode, the processor 22 is further configured to control the operation states of the fourth switch S4, the fifth switch S5, and the sixth switch S6, so that the array element in the reference transmit channel is communicated with the down-conversion rf front end 23, and the array element in the auxiliary reference transmit channel is communicated with the transmit rf front end in the auxiliary reference transmit channel; each transmitting radio frequency front end in each non-reference transmitting channel receives and processes a transmitting correction signal, and the processed transmitting correction signal is output to an array element in each non-reference transmitting channel so as to radiate the processed transmitting correction signal through the array element in each non-reference transmitting channel;
the processor 22 is further configured to receive a third signal output by the down-conversion rf front end 23; the third signal is the processed emission correction signal radiated by the array element of each non-reference emission channel, is received by the array element in the reference emission channel, and is processed by the down-conversion radio frequency front end; the processor 22 is further configured to control the operating states of the fourth switch S4, the fifth switch S5, and the sixth switch S6, so that the array element in the reference transmit channel is communicated with the transmit rf front end in the reference transmit channel, and the array element in the auxiliary reference transmit channel is communicated with the down-conversion rf front end; each transmitting radio frequency front end in each non-auxiliary reference transmitting channel receives and processes a transmitting correction signal, and the processed transmitting correction signal is output to an array element in each non-auxiliary reference transmitting channel so as to radiate the processed transmitting correction signal through the array element in the non-reference transmitting channel;
the processor 22 is further configured to receive a fourth signal output by the down-conversion rf front end 23; the fourth signal is the processed emission correction signal radiated by the array element of each non-auxiliary reference emission channel, is received by the array element in the auxiliary reference emission channel, and is processed by the down-conversion radio frequency front end; and determining a third error of each transmit channel relative to the reference transmit channel based on the third signal, the fourth signal, and the transmit correction signal.
The phased array antenna error correction circuit that this embodiment provided, the treater can loop through the array element of reference transmitting channel and the transmission correction signal after the array element of supplementary reference transmitting channel received the radiation for transmission correction signal can excite each transmitting channel, and need not increase dedicated supplementary array element in traditional phased array antenna, realizes the excitation of transmission correction signal to each transmitting channel, thereby has reduced the change cost to traditional phased array antenna. In addition, in the error acquisition process, the third error of each transmitting channel relative to the reference transmitting channel can be determined according to the third signal and the fourth signal of the two excitation results and the transmitting correction signal, so that the accuracy of the determined error result is improved.
Optionally, when the operating mode of the phased array antenna is an error correction mode, the processor 22 is further configured to control the operating states of the fourth switch, the fifth switch, and the sixth switch, so that the array element in the reference receiving channel is communicated with the transmit rf front end in the reference receiving channel, the array element in the auxiliary reference receiving channel is communicated with the transmit rf front end in the auxiliary reference receiving channel, and the up-conversion rf front end is communicated with the beam output end; and correcting errors of the transmitting channels according to the errors of the transmitting channels relative to the reference transmitting channel.
According to the phased array antenna error correction circuit provided by the embodiment, the processor can control the working state of each switch, so that the working mode of the phased array antenna is switched to the error correction mode from the error acquisition mode, the phased array antenna can be switched between two working modes through the same switch, the number of the switches is reduced, and the change cost of the traditional phased array antenna is further reduced; in addition, because the third error of each transmitting channel relative to the reference transmitting channel is determined based on the third signal and the fourth signal of the excitation results of two times and combined with the transmitting correction signal, the accuracy of the determined third error is improved, and the accuracy of the error correction result of each transmitting channel based on the third error is improved.
The following describes the process of performing error correction on each receiving channel by taking the fourth switch S4, the sixth switch S5 as a single-pole double-throw switch, and the fifth switch S6 as a single-pole 4-throw switch as an example, and specifically, refer to fig. 4:
assuming that the transmitting channel 2 is selected as a reference transmitting channel and the receiving channel 1 is selected as an auxiliary reference transmitting channel, for this case, the connection relationship of each switch in the phased array antenna error correction circuit is as follows: a pin 1 at the common end of the fourth switch S4 is connected with a transmitting port of the transmitting isolator D2, a pin 2 of the fourth switch S4 is connected with a pin 4 of the fifth switch S5, and a pin 3 of the fourth switch S4 is connected with a transmitting radio frequency front end of a reference transmitting channel; a pin 1 at the common end of the sixth switch S6 is connected with a transmitting port of the transmitting isolator D1, a pin 2 of the sixth switch S6 is connected with a pin 5 of the fifth switch S5, and a pin 3 of the sixth switch S6 is connected with the transmitting radio frequency front end of the auxiliary reference transmitting channel; a pin 1 at the common end of the fifth switch S5 is connected to the input end of the down-conversion radio frequency front end 23; and the other N-2 array elements are respectively connected with the corresponding transmitting radio frequency front end through the transmitting port of the transmitting-receiving isolator and connected with the receiving radio frequency front end circuit through the receiving port of the transmitting-receiving isolator.
The error correction procedure for each transmit channel may be: when the phased array antenna is powered on, the processor 22 controls the common terminal 1 pin of the fourth switch S4 to be switched to the 2 pin, the common terminal 1 pin of the fifth switch S5 to be switched to the 4 pin, and the common terminal 1 pin of the sixth switch S6 to be switched to the 3 pin, so that the array element in the reference transmission channel is communicated with the down-conversion radio frequency front end 23, and the array element in the auxiliary reference transmission channel is communicated with the transmission radio frequency front end in the auxiliary reference transmission channel. Then, N-1 emission correction signals are output, and the emission radio frequency front end of each non-reference emission channel is controlled to receive the emission correction signals. Thus, the emission correction signal is processed by the emission rf front end of each non-reference emission channel (emission channel 1, emission channel 3 … … emission channel N, where the emission channel where a1 is located is emission channel 1, the emission channel where A3 is located is emission channel 3, and the emission channel where AN is located is emission channel N), then radiated by the array element (array element a1, array element A3 … … array element AN) of each non-reference emission channel, received by the array element a2 of the reference emission channel, and processed by the fourth switch S4, the fifth switch S5, and the up-conversion rf front end 23 to obtain a third signal, which is output to the processor 22.
Next, the transmit calibration signal is turned off, and the processor 12 controls the common terminal 1 pin of the fourth switch S4 to switch to 3 pins, the common terminal 1 pin of the fifth switch S5 to switch to 5 pins, and the common terminal 1 pin of the sixth switch S6 to switch to 2 pins, so that the array element in the reference transmit channel communicates with the transmit rf front end in the reference transmit channel, and the array element in the auxiliary reference transmit channel communicates with the down-conversion rf front end 23. Then, outputting N-1 emission correction signals and controlling the emission radio frequency front end of each non-auxiliary reference emission channel to receive the emission correction signals. Thus, after the emission correction signal is processed by the emission rf front end of each non-auxiliary reference emission channel (emission channel 2, emission channel 3 … … emission channel N, where the emission channel where a2 is located is emission channel 2), the emission correction signal is radiated by the array elements (array element a2, array element A3 … … array element AN) of each non-auxiliary reference emission channel, and after being received by the array element a1 of the auxiliary reference emission channel, the emission correction signal is processed by the sixth switch S6, the fifth switch S5, and the up-conversion rf front end 23 to obtain a fourth signal, which is output to the processor 22. The processor 22 determines a third error for each transmit channel relative to the reference transmit channel based on the received third signal, the fourth signal, and the transmit correction signal.
Then, the processor 22 controls the common terminal 1 pin of the fourth switch S4 to be switched to 3 pins, the common terminal 1 pin of the fifth switch S5 to be switched to 2 pins, and the common terminal 1 pin of the sixth switch S3 to be switched to 3 pins, so that the array element in the reference transmission channel is communicated with the transmission rf front end in the reference transmission channel, the array element in the auxiliary reference transmission channel is communicated with the transmission rf front end in the auxiliary reference transmission channel, and the down-conversion rf front end 23 is communicated with the beam transmission end. At this time, the processor 22 may perform error correction on the N low-frequency or baseband signals output from the transmit beam combiner according to the obtained third errors of the N transmit channels relative to the reference transmit channel, and output the N corrected low-frequency or baseband signals to the transmit rf front end of the corresponding transmit channel, so that the transmit rf front end processes the corresponding low-frequency or baseband signals, and radiates the processed radio frequency signals out through the corresponding array elements.
In one embodiment, the processor 22 is further configured to determine a fourth error of each of the transmit channels relative to the reference transmit channel based on the third signal and the transmit correction signal; determining an error of the reference transmit channel relative to the auxiliary reference transmit channel based on the fourth signal and the receive correction signal; and determining a third error of each transmitting channel relative to the reference transmitting channel according to a fourth error of each transmitting channel relative to the reference transmitting channel and an error of the reference transmitting channel relative to the auxiliary reference transmitting channel.
In the error correction circuit of the phased array antenna provided by this embodiment, since the processor can receive the transmission correction signal excited by each of the other non-reference transmission channels based on the reference transmission channel by switching the reference transmission channel and the auxiliary reference transmission channel, and calculates a fourth error by reference to the third signal received by the transmit channel and the transmit correction signal, and receiving the transmission correction signals excited by other non-auxiliary reference transmission channels based on the auxiliary reference transmission channel, and calculates the error of the reference transmitting channel relative to the auxiliary reference transmitting channel by using the fourth signal received by the auxiliary reference transmitting channel and the transmitting correction signal, and determining a third error based on the fourth error and the error of the reference transmitting channel relative to the auxiliary reference transmitting channel, and improving the accuracy of the determined third error in a three-time error calculation mode.
Optionally, the processor 22 is further configured to determine a signal correlation value of each transmission channel according to the first signal and the transmission correction signal; and determining a fourth error of each transmitting channel relative to the reference transmitting channel according to the signal correlation value of each transmitting channel and the transmitting correction signal.
Specifically, let the third signal be xt (n) ═ xt1(n),xt2(n),...,xtN(n)]TWherein x ist2And (n) is 0, and n is the number of sampling points. The processor 22 may be based on a formula
Figure BDA0001988968350000131
Or comprises
Figure BDA0001988968350000132
Determining the signal correlation value Rx of each transmission channelt(n), wherein i is the serial number of the sampling point, and CT (i) is the emission correction signal. After obtaining the signal correlation value Rx of each transmitting channeltAfter (n), processor 22 may then formulate a formulaOr comprises
Figure BDA0001988968350000134
Determining a fourth error e of each transmit channel relative to the reference transmit channelt(n) of (a). Wherein,
Figure BDA0001988968350000135
pt(n)＝[pt1(n),pt2(n),...,ptN(n)]Treal is the real part operation and imag is the imaginary part operation.
In the error correction circuit for a phased array antenna provided by this embodiment, the processor may determine the fourth error of each transmission channel with respect to the reference transmission channel based on the signal correlation value between the transmission channels. Because the signal correlation values among the transmitting channels can indirectly represent the errors among the transmitting channels, the fourth error of each transmitting channel relative to the reference transmitting channel is determined by adopting the signal correlation values among the transmitting channels, and the accuracy of the result of the determined fourth error is improved.
Optionally, the processor 22 is further configured to determine a signal correlation value of the reference transmission channel and the auxiliary reference transmission channel according to the fourth signal and the transmission correction signal; and determining the error of the reference transmission channel relative to the auxiliary reference transmission channel according to the signal correlation values of the reference transmission channel and the auxiliary reference transmission channel and the transmission correction signal.
Specifically, the fourth signal is assumed to be X't (n) ═ X't1(n),x't2(n),...,x'tN(n)]TWherein, x't1And (n) is 0, and n is the number of sampling points. The processor 22 may be based on a formula
Figure BDA0001988968350000141
Or comprises
Figure BDA0001988968350000142
Determining the signal correlation value R' x of the reference transmission channel and the auxiliary reference transmission channelt(1) Wherein i is the serial number of the sampling point, and CT (i) is the emission correction signal. After obtaining the signal correlation value R' x of each transmitting channelt(1) Processor 22 may then formulate a formula
Figure BDA0001988968350000143
Or comprises
Figure BDA0001988968350000144
Determining the error e of the reference transmission channel relative to the auxiliary reference transmission channelt'(1). Wherein,
Figure BDA0001988968350000145
pt'(1)＝[p't1(1),p't2(1)]Treal is the real part operation and imag is the imaginary part operation.
Obtaining a fourth error e of each transmitting channel relative to the reference transmitting channelt(n) error e of sum reference transmission channel relative to auxiliary reference transmission channelt' (1) thereafter, the processor 22 may follow the formula
Figure BDA0001988968350000146
Or comprises
Figure BDA0001988968350000147
Determining a third error E of each transmit channel relative to the reference transmit channelt(n)。
In the error correction circuit for a phased array antenna provided by this embodiment, the processor may determine an error of the reference transmission channel with respect to the auxiliary reference transmission channel based on the signal correlation values of the reference transmission channel and the auxiliary reference transmission channel. Because the signal correlation values among the transmitting channels can indirectly represent the errors among the transmitting channels, the method for determining the errors of the reference transmitting channels relative to the auxiliary reference transmitting channels by adopting the signal correlation values of the reference transmitting channels and the auxiliary reference transmitting channels improves the accuracy of the result of the determined errors.
Fig. 5 is a schematic structural diagram of an error correction system of a phased array antenna according to an embodiment. As shown in fig. 5, the phased array antenna error correction system may include: the antenna system comprises a phased array antenna error correction circuit used for correcting errors of all receiving channels and a phased array antenna error correction circuit used for correcting errors of all receiving channels, wherein the two phased array antenna error correction circuits share one antenna array.
Specifically, referring to fig. 5, the phased array antenna error correction system may include: an antenna array 30, a receiving rf front-end circuit 31, a processor 32, an up-conversion rf front-end 33, a transmitting rf front-end circuit 34, and a down-conversion rf front-end 35. Each receiving rf front end of the receiving rf front end circuit 31 and the array element in the antenna array 30 form a receiving channel, and one channel is selected from the receiving channels as a reference receiving channel and an auxiliary reference receiving channel; each rf front end of the rf front end circuit 34 and the array elements in the antenna array 30 form a transmit channel, and one channel is selected from the transmit channels as a reference transmit channel and an auxiliary reference transmit channel.
The array elements in the reference receive channel in the antenna array 30 are connected to the input end of the receive rf front end in the reference receive channel through the first switch S1, and connected to the output end of the up-conversion rf front end 33 through the first switch S1 and the second switch S2; the array elements in the antenna array 30 located in the auxiliary reference receive channel are connected to the input of the receive rf front end in the auxiliary reference receive channel through the third switch S3, and are connected to the output of the up-conversion rf front end 33 through the third switch S3 and the second switch S2.
The array elements in the antenna array 30 located in the reference transmit channel are connected to the output end of the transmit rf front end in the reference transmit channel through a fourth switch S4, and connected to the input end of the down-conversion rf front end 35 through the fourth switch S4 and a fifth switch S5; the array elements in the auxiliary reference transmit channel in the antenna array 30 are connected to the output of the transmit rf front end in the auxiliary transmit channel through a sixth switch S6, and connected to the input of the down-conversion rf front end 35 through the sixth switch S6 and the fifth switch S5.
The error correction procedure for each receive channel may be: the processor 32 is connected to an output end of each receiving rf front end of the receiving rf front end circuit, connected to an input end of the up-conversion rf front end 33, and configured to control operating states of the first switch S1, the second switch S2, and the third switch S3 according to an operating mode of the phased array antenna, and perform error correction on each receiving channel in combination with a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
The error correction procedure for each transmit channel may be: the processor 32 is connected to the output end of the down-conversion rf front end 35, connected to the input end of each rf front end of the rf front end circuit, and configured to control the operating states of the fourth switch, the fifth switch, and the sixth switch according to the operating mode of the phased array antenna, and perform error correction on each transmit channel in combination with a transmit correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
It should be noted that, as to how the processor 32 controls the operating states of the switches to implement the processes of error correction for each receiving channel and error correction for each transmitting channel, reference may be made to the detailed description of the above embodiments, and this implementation is not described herein again.
The error correction system of phased array antenna that this embodiment provided, because this system not only can realize the error correction to each transmission channel, also can realize the error correction to each receiving channel, and in whole error correction process, need not increase dedicated supplementary array element in phased array antenna, the excitation of receiving correction signal to each receiving channel can be realized to array element in the direct existing antenna array that utilizes, the excitation of transmission correction signal to each transmission channel, the change cost to traditional phased array antenna has been reduced.
Fig. 6 is a flowchart illustrating an error correction method for a phased array antenna according to an embodiment, which is applied to the phased array antenna, and as shown in fig. 1, the method may include:
s101, selecting one channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel respectively.
The array element in the reference receiving channel is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch, and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; the array element in the auxiliary reference receiving channel is connected with the input end of the receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with the output end of the up-conversion radio frequency front end through the third switch and the second switch.
Because each receiving radio frequency front end in the phased array antenna error correction circuit and the array element in the antenna array form a receiving channel, a plurality of receiving channels exist in the phased array antenna error correction circuit. The reference receiving channel and the auxiliary reference receiving channel are respectively any one of a plurality of receiving channels. Optionally, the first switch, the second switch, and the third switch may be single-pole multi-throw switches, and the first switch and the third switch may also be single-pole double-throw switches, which is not limited in this embodiment.
S102, controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
When the phased array antenna is powered on and started, the processor controls the working states of the first switch, the second switch and the third switch to enable the phased array antenna to work in an error acquisition mode, and meanwhile, the up-conversion radio frequency front end is controlled to receive and receive the correction signal. Thus, the receiving correction signal can be radiated out through the array element in the reference receiving channel or the array element in the auxiliary reference receiving channel, and the radiated receiving correction signal is received by other array elements except the radiating receiving correction signal in the antenna array, so that each receiving channel is excited by the receiving correction signal. And the processor acquires the error of each receiving channel relative to the reference receiving channel according to the excitation result of each receiving channel. After the error of each receiving channel relative to the reference receiving channel is obtained, the processor controls the working states of the first switch, the second switch and the third switch to enable the phased array antenna to work in an error correction mode. And the processor corrects the errors of all the receiving channels according to the obtained errors of all the receiving channels relative to the reference receiving channel. Alternatively, the reception correction signal may be a spread spectrum signal, a chirp signal, a tone signal, or the like.
In the error correction method for the phased array antenna provided in this embodiment, in the whole error correction process, the processor controls the operating states of the first switch, the second switch, and the third switch, so that the excitation of the received correction signal to each receiving channel can be realized by using the array elements in the existing antenna array, and the error correction to each receiving channel is realized by combining the received correction signal. The error correction method does not need to add special auxiliary array elements in the phased array antenna, so that the change cost of the traditional phased array antenna is reduced. Meanwhile, the error correction process is simplified, and therefore the error correction efficiency is improved.
In another embodiment, referring to fig. 7, on the basis of the above embodiment, when the operation mode of the phased array antenna is the error acquisition mode, the manner of acquiring the first error of each receiving channel relative to the reference receiving channel may include:
s201, controlling the working states of the first switch, the second switch and the third switch to enable the array element in the reference receiving channel to be communicated with the up-conversion radio frequency front end and the array element in the auxiliary reference receiving channel to be communicated with the receiving radio frequency front end in the auxiliary reference receiving channel.
S202, receiving first signals through the non-reference receiving channels.
The first signal is a signal obtained by performing up-conversion processing on the reception correction signal by the up-conversion radio frequency front end, radiating the reception correction signal by an array element in the reference receiving channel, and receiving the reception correction signal by each non-reference receiving channel.
S203, controlling the working states of the first switch, the second switch and the third switch to enable the array element in the reference receiving channel to be communicated with the receiving radio frequency front end in the reference receiving channel and the array element in the auxiliary reference receiving channel to be communicated with the up-conversion radio frequency front end.
And S204, receiving a second signal through each non-auxiliary reference receiving channel.
The second signal is a signal obtained by performing up-conversion processing on the reception correction signal by the up-conversion radio frequency front end, radiating the reception correction signal by an array element in the auxiliary reference receiving channel, and receiving the reception correction signal by each non-auxiliary reference receiving channel.
S205, determining a first error of each receiving channel relative to the reference receiving channel according to the first signal, the second signal and the receiving correction signal.
Optionally, when the operating mode of the phased array antenna is an error correction mode, the method for performing error correction on each receiving channel may include: controlling the working states of the first switch, the second switch and the third switch to enable the array element in the reference receiving channel to be communicated with the receiving radio frequency front end in the reference receiving channel, the array element in the auxiliary reference receiving channel to be communicated with the receiving radio frequency front end in the auxiliary reference receiving channel, and the up-conversion radio frequency front end to be communicated with the beam receiving end; and correcting the errors of the receiving channels according to the errors of the receiving channels relative to the reference receiving channel.
The error correction method for the phased array antenna provided by this embodiment can sequentially receive the correction signal through the array element of the reference receiving channel and the array element radiation of the auxiliary reference receiving channel, so that the reception correction signal can excite each receiving channel, and it is not necessary to add a dedicated auxiliary array element in the phased array antenna to realize the excitation of the reception correction signal to each receiving channel, thereby reducing the change cost of the conventional phased array antenna. In addition, in the error correction process, the first error of each receiving channel relative to the reference receiving channel can be determined according to the first signal and the second signal of the excitation results twice and the receiving correction signal, so that the accuracy of the determined error result is improved.
In another embodiment, as shown in fig. 8, on the basis of the above embodiment, the above S205 may include:
s301, according to the first signal and the receiving correction signal, determining a second error of each receiving channel relative to the reference receiving channel.
As an alternative embodiment, the processor may determine a signal correlation value for each receiving channel based on the first signal and the reception correction signal; and determining a second error of each receiving channel relative to the reference receiving channel according to the signal correlation value of each receiving channel and the receiving correction signal.
Wherein, the first signal is assumed to be xr (n) ═ xr1(n),xr2(n),...,xrN(n)]TWherein x isr1And (n) is 0, and n is the number of sampling points. The processor may be based on a formula
Figure BDA0001988968350000171
Or comprises
Figure BDA0001988968350000172
Determining the signal correlation value Rx of each receiving channelr(n), wherein i is the serial number of the sampling point, and CR (i) is the receiving correction signal. After obtaining the signal correlation value Rx of each receiving channelrAfter (n), processor 12 formulates a formula
Figure BDA0001988968350000173
Or comprises
Figure BDA0001988968350000174
Determining a second error e of each receive channel relative to the reference receive channelr(n) of (a). Wherein,
Figure BDA0001988968350000175
pr(n)＝[pr1(n),pr2(n),...,prN(n)]Treal is the real part operation and imag is the imaginary part operation.
S302, determining the error of the reference receiving channel relative to the auxiliary reference receiving channel according to the second signal and the receiving correction signal.
As an alternative embodiment, the processor may determine the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel according to the second signal and the reception correction signal; and determining the error of the reference receiving channel relative to the auxiliary reference receiving channel according to the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel and the receiving correction signal.
Wherein, it is assumed that the second signal is X 'r (n) ═ X'r1(n),x'r2(n),...,x'rN(n)]TWherein, x'r2And (n) is 0, and n is the number of sampling points. The processor 12 may be based on a formula
Figure BDA0001988968350000181
Or comprises
Figure BDA0001988968350000182
Determining the signal correlation value R' x of the reference receiving channel and the auxiliary reference receiving channelr(1) Wherein i is the serial number of the sampling point, and CR (i) is the receiving calibration signal. After obtaining the signal correlation value R' x of each receiving channelr(1) Processor 12 may then formulate a formula
Figure BDA0001988968350000183
Or comprises
Figure BDA0001988968350000184
Determining the error e of the reference reception channel relative to the auxiliary reference reception channelr'(1). Wherein,
Figure BDA0001988968350000185
p'(1)＝[p'r1(1),p'r2(1)]Treal is the real part operation and imag is the imaginary part operation.
S303, determining a first error of each receiving channel relative to the reference receiving channel according to a second error of each receiving channel relative to the reference receiving channel and an error of the reference receiving channel relative to the auxiliary reference receiving channel.
Wherein the second error of each receiving channel relative to the reference receiving channel is obtainedDifference er(n) error e of the sum reference reception channel with respect to the auxiliary reference reception channelr' (1) thereafter, the processor may be based on the formula
Figure BDA0001988968350000186
Or comprises
Figure BDA0001988968350000187
Determining a first error E of each receive channel relative to a reference receive channelr(n)。
In the method for correcting errors of the phased array antenna provided by this embodiment, since the processor can output the reception correction signal based on the reference reception channel and calculate the second error by using the first signal received by the other non-reference reception channel and the reception correction signal by switching the reference reception channel and the auxiliary reference reception channel, and output the reception correction signal based on the auxiliary reference reception channel and calculate the error of the reference reception channel with respect to the auxiliary reference reception channel by using the second signal received by the other non-auxiliary reference reception channel and the reception correction signal, and determine the first error based on the second error and the error of the reference reception channel with respect to the auxiliary reference reception channel, the accuracy of the determined first error is improved by calculating the third error.
The above embodiment of the method can implement error correction for each receiving channel, and in practical application, errors also exist between each transmitting channel, and the following embodiment also provides a process for error correction for each transmitting channel, and the specific correction process may refer to the description of the following embodiment.
In another embodiment, referring to fig. 9, on the basis of the above embodiment, the method may further include:
s401, selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively.
The array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch, and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; and the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch.
Because each transmitting radio frequency front end in the phased array antenna error correction circuit and the array element in the antenna array form a transmitting channel, a plurality of transmitting channels exist in the phased array antenna error correction circuit. The reference transmission channel and the auxiliary reference transmission channel are respectively any one of a plurality of transmission channels. Optionally, the fourth switch, the fifth switch, and the sixth switch may be single-pole multi-throw switches, and the fourth switch and the sixth switch may also be single-pole double-throw switches, which is not limited in this embodiment.
S402, controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and carrying out error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
When the phased array antenna is powered on and started, the processor controls the working states of the fourth switch, the fifth switch and the sixth switch to enable the phased array antenna to work in an error acquisition mode, and meanwhile, the processor controls each transmitting radio frequency front end in each non-reference transmitting channel or each transmitting radio frequency front end in each non-auxiliary reference transmitting channel to receive and transmit a correction signal. Thus, the emission correction signal can be radiated through the array elements in each non-reference emission channel or the array elements in each non-auxiliary reference emission channel, and the radiated emission correction signal is received by the array elements in the reference emission channels or the array elements in the auxiliary reference emission channels in the antenna array, so that each emission channel is excited by the emission correction signal. And the processor acquires the error of each transmitting channel relative to the reference transmitting channel according to the excitation result of each transmitting channel. And after the error of each transmitting channel relative to the reference transmitting channel is obtained, the processor controls the working states of the fourth switch, the fifth switch and the sixth switch to enable the phased array antenna to work in an error correction mode. And the processor corrects the errors of all the transmitting channels according to the obtained errors of all the transmitting channels relative to the reference transmitting channel. Of course, the processor may also output the transmission correction signal to the transmission rf front end of each non-reference transmission channel by using a time-sharing transmission method, or output the transmission correction signal to the transmission rf front end of the non-auxiliary reference transmission channel by using a time-sharing transmission method, which is not limited in this embodiment.
In the error correction method for the phased array antenna provided in this embodiment, in the whole error correction process, by controlling the operating states of the fourth switch, the fifth switch, and the sixth switch, excitation of the transmission correction signal to each transmission channel can be realized by using the array elements in the existing antenna array, and by combining the transmission correction signal, error correction to each transmission channel is realized. The error correction method does not need to add special auxiliary array elements in the phased array antenna, so that the change cost of the traditional phased array antenna is reduced. Meanwhile, the error correction process is simplified, and therefore the error correction efficiency is improved.
In another embodiment, referring to fig. 10, on the basis of the above embodiment, when the operation mode of the phased array antenna is the error obtaining mode, the obtaining the first error of each transmission channel with respect to the reference transmission channel includes:
s501, controlling the working states of the fourth switch, the fifth switch and the sixth switch to enable the array elements in the reference transmitting channel to be communicated with the down-conversion radio frequency front end, and the array elements in the auxiliary reference transmitting channel to be communicated with the transmitting radio frequency front end in the auxiliary reference transmitting channel.
And S502, receiving a third signal.
The third signal is a signal which is obtained by processing the emission correction signal by each emission radio frequency front end in each non-reference emission channel, radiating the emission correction signal by an array element corresponding to each emission radio frequency front end, receiving the emission correction signal by an array element in a reference emission channel, and processing the emission correction signal by the down-conversion radio frequency front end.
And S503, controlling the working states of the fourth switch, the fifth switch and the sixth switch to enable the array elements in the reference transmitting channel to be communicated with the transmitting radio frequency front end in the reference transmitting channel, and the array elements in the auxiliary reference transmitting channel to be communicated with the down-conversion radio frequency front end.
S504, receiving a fourth signal; the fourth signal is a signal which is obtained by processing the emission correction signal by each emission radio frequency front end in each non-auxiliary reference emission channel, radiating the emission correction signal by an array element corresponding to each emission radio frequency front end, receiving the emission correction signal by an array element in an auxiliary reference emission channel, and processing the emission correction signal by the down-conversion radio frequency front end.
And S505, determining a third error of each transmitting channel relative to the reference transmitting channel according to the third signal, the fourth signal and the transmitting correction signal.
As an alternative implementation, the step S505 may be: determining a fourth error of each transmitting channel relative to the reference transmitting channel according to the third signal and the transmitting correction signal; determining an error of the reference transmission channel relative to the auxiliary reference transmission channel according to the fourth signal and the transmission correction signal; and determining a third error of each transmitting channel relative to the reference transmitting channel according to the fourth error of each transmitting channel relative to the reference transmitting channel and the error of the reference transmitting channel relative to the auxiliary reference transmitting channel.
Optionally, when the operating mode of the phased array antenna is an error correction mode, the method for performing error correction on each transmission channel may include: controlling the working states of the fourth switch, the fifth switch and the sixth switch to enable the array elements in the reference receiving channel to be communicated with the transmitting radio frequency front end in the reference receiving channel, the array elements in the auxiliary reference receiving channel to be communicated with the transmitting radio frequency front end in the auxiliary reference receiving channel, and the up-conversion radio frequency front end to be communicated with the beam output end; and correcting errors of the transmitting channels according to the errors of the transmitting channels relative to the reference transmitting channel.
The phased array antenna error correction method provided by this embodiment can receive the transmission correction signal through the array element of the reference transmission channel and the array element of the auxiliary reference transmission channel in sequence, so that the transmission correction signal can excite each transmission channel, and it is not necessary to add a dedicated auxiliary array element in the phased array antenna to realize excitation of the transmission correction signal to each transmission channel, thereby reducing the change cost of the conventional phased array antenna. In addition, in the whole error correction process, a plurality of emission correction signals can be emitted simultaneously, so that the emission correction signals can excite a plurality of emission channels simultaneously, the error correction time is shortened, and the error correction efficiency is further improved.
In practical applications, there are also cases where error correction is performed only for each transmission channel in a phased array antenna, for which case the error correction can be performed with reference to the following procedure as shown in fig. 11. As shown in fig. 11, the method may include:
s601, selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively.
The array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch, and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; and the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch.
S602, controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
In the error correction method for the phased array antenna provided in this embodiment, in the whole error correction process, by controlling the operating states of the fourth switch, the fifth switch, and the sixth switch, excitation of the transmission correction signal to each transmission channel can be realized by using the array elements in the existing antenna array, and by combining the transmission correction signal, error correction to each transmission channel is realized. The error correction method does not need to add special auxiliary array elements in the phased array antenna, so that the change cost of the traditional phased array antenna is reduced. Meanwhile, the error correction process is simplified, and therefore the error correction efficiency is improved.
It should be understood that although the various steps in the flowcharts of fig. 6-11 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Also, at least some of the steps in fig. 6-11 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
selecting one channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel respectively; the array element in the reference receiving channel is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; the array element in the auxiliary reference receiving channel is connected with the input end of the receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with the output end of the up-conversion radio frequency front end through the third switch and the second switch;
controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively; the array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch;
controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (23)

1. A phased array antenna error correction circuit, comprising: the antenna array, a receiving radio frequency front end circuit, a processor and an up-conversion radio frequency front end, wherein each receiving radio frequency front end of the receiving radio frequency front end circuit and an array element in the antenna array form a receiving channel, and one channel is respectively selected from the receiving channels as a reference receiving channel and an auxiliary reference receiving channel;
an array element in the antenna array, which is positioned in the reference receiving channel, is connected with the input end of a receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch;
an array element in the auxiliary reference receiving channel in the antenna array is connected with an input end of a receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with an output end of the up-conversion radio frequency front end through the third switch and the second switch;
the processor is connected with the output end of each receiving radio frequency front end of the receiving radio frequency front end circuit, connected with the input end of the up-conversion radio frequency front end, and used for controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining with a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
2. The circuit of claim 1, wherein when the operating mode of the phased array antenna is an error acquisition mode, the processor is further configured to control the operating states of the first switch, the second switch, and the third switch such that the array elements in the reference receive channel communicate with the upconverting radio frequency front end and the array elements in the auxiliary reference receive channel communicate with the receive radio frequency front end in the auxiliary reference receive channel;
the up-conversion radio frequency front end is configured to receive the receive correction signal, perform up-conversion processing on the receive correction signal, output the receive correction signal after the up-conversion processing to an array element in the reference receive channel, and radiate the receive correction signal after the up-conversion processing through the array element in the reference receive channel;
the processor is further configured to receive a first signal through each non-reference receive channel; the first signal is related to a signal radiated by an array element in the reference receiving channel; and
controlling the working states of the first switch, the second switch and the third switch so as to enable the array element in the reference receiving channel to be communicated with the receiving radio frequency front end in the reference receiving channel and the array element in the auxiliary reference receiving channel to be communicated with the up-conversion radio frequency front end;
the up-conversion radio frequency front end is configured to receive the receive correction signal, perform up-conversion processing on the receive correction signal, and output the receive correction signal after the up-conversion processing to an array element in the auxiliary reference receive channel, so that the receive correction signal after the up-conversion processing is radiated by the array element in the auxiliary reference receive channel;
the processor is further configured to receive a second signal via each non-auxiliary reference receive channel; the second signal is related to a signal radiated by an array element in the auxiliary reference receiving channel; and
determining a first error of each receive channel relative to the reference receive channel based on the first signal, the second signal, and the receive correction signal.
3. The circuit of claim 2, wherein when the operating mode of the phased array antenna is an error correction mode, the processor is further configured to control the operating states of the first switch, the second switch, and the third switch to communicate the elements in the reference receive channel with the receive rf front end in the reference receive channel, the elements in the auxiliary reference receive channel with the receive rf front end in the auxiliary reference receive channel, and the upconvert rf front end with the beam receive end; and
and correcting the errors of the receiving channels according to the first errors of the receiving channels relative to the reference receiving channel.
4. The circuit of claim 2, wherein the processor is further configured to determine a second error of the respective receive channel relative to the reference receive channel based on the first signal and the receive correction signal;
determining an error of the reference receive channel relative to the auxiliary reference receive channel based on the second signal and the receive correction signal; and
and determining a first error of each receiving channel relative to the reference receiving channel according to a second error of each receiving channel relative to the reference receiving channel and an error of the reference receiving channel relative to the auxiliary reference receiving channel.
5. The circuit of claim 4, wherein the processor is further configured to determine a signal correlation value for each receive channel based on the first signal and the receive correction signal; and
and determining a second error of each receiving channel relative to the reference receiving channel according to the signal correlation value of each receiving channel and the receiving correction signal.
6. The circuit of claim 4, wherein the processor is further configured to determine a signal correlation value for the reference receive channel and the auxiliary reference receive channel based on the second signal and the receive correction signal; and
and determining the error of the reference receiving channel relative to the auxiliary reference receiving channel according to the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel and the receiving correction signal.
7. A phased array antenna error correction circuit, comprising: the antenna array comprises an antenna array, a transmitting radio frequency front end circuit, a processor and a down-conversion radio frequency front end, wherein each transmitting radio frequency front end of the transmitting radio frequency front end circuit and an array element in the antenna array form a transmitting channel, and one channel is respectively selected from the transmitting channels to serve as a reference transmitting channel and an auxiliary reference transmitting channel;
an array element in the reference transmitting channel in the antenna array is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch, and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch;
an array element in the auxiliary reference transmitting channel in the antenna array is connected with an output end of a transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with an input end of a down-conversion radio frequency front end through the sixth switch and the fifth switch;
the processor is connected with the output end of the down-conversion radio frequency front end, connected with the input end of each transmission radio frequency front end of the transmission radio frequency front end circuit, and used for controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and carrying out error correction on each transmission channel by combining with a transmission correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
8. The circuit of claim 7, wherein when the operating mode of the phased array antenna is an error acquisition mode, the processor is further configured to control the operating states of the fourth switch, the fifth switch, and the sixth switch such that the array elements in the reference transmit channel communicate with the down-conversion rf front end and the array elements in the auxiliary reference transmit channel communicate with the transmit rf front end in the auxiliary reference transmit channel;
each transmitting radio frequency front end in each non-reference transmitting channel receives and processes a transmitting correction signal, and the processed transmitting correction signal is output to an array element in each non-reference transmitting channel so as to radiate the processed transmitting correction signal through the array element in each non-reference transmitting channel;
the processor is further configured to receive a third signal output by the down-conversion radio frequency front end; the third signal is the processed emission correction signal radiated by the array element of each non-reference emission channel, is received by the array element in the reference emission channel, and is processed by the down-conversion radio frequency front end;
the processor is further configured to control operating states of the fourth switch, the fifth switch, and the sixth switch, so that an array element in the reference transmission channel is communicated with a transmission radio frequency front end in the reference transmission channel, and an array element in the auxiliary reference transmission channel is communicated with the down-conversion radio frequency front end;
each transmitting radio frequency front end in each non-auxiliary reference transmitting channel receives and processes a transmitting correction signal, and the processed transmitting correction signal is output to an array element in each non-auxiliary reference transmitting channel so as to radiate the processed transmitting correction signal through the array element in the non-reference transmitting channel;
the processor is further configured to receive a fourth signal output by the down-conversion radio frequency front end; the fourth signal is the processed emission correction signal radiated by the array element of each non-auxiliary reference emission channel, is received by the array element in the auxiliary reference emission channel, and is processed by the down-conversion radio frequency front end;
the processor is further configured to determine a third error of each transmit channel with respect to the reference transmit channel according to the third signal, the fourth signal, and the transmit correction signal.
9. The circuit of claim 8, wherein when the operating mode of the phased array antenna is an error correction mode, the processor is further configured to control the operating states of the fourth switch, the fifth switch, and the sixth switch such that the array element in the reference receive channel is in communication with the transmit rf front end in the reference receive channel, the array element in the auxiliary reference receive channel is in communication with the transmit rf front end in the auxiliary reference receive channel, and the upconverting rf front end is in communication with the beam output; and
and correcting errors of the transmitting channels according to the errors of the transmitting channels relative to the reference transmitting channel.
10. The circuit of claim 8, wherein the processor is further configured to determine a fourth error of each transmit channel relative to the reference transmit channel based on the third signal and the transmit correction signal; and
determining an error of the reference transmission channel relative to the auxiliary reference transmission channel according to the fourth signal and the transmission correction signal; and
and determining a third error of each transmitting channel relative to the reference transmitting channel according to the fourth error of each transmitting channel relative to the reference transmitting channel and the error of the reference transmitting channel relative to the auxiliary reference transmitting channel.
11. A phased array antenna error correction system comprising a phased array antenna error correction circuit according to any of claims 1 to 6 and a phased array antenna error correction circuit according to any of claims 7 to 10, the two phased array antenna error correction circuits sharing an antenna array.
12. A method of error correction for a phased array antenna, comprising:
selecting one channel from a plurality of receiving channels of the phased array antenna as a reference receiving channel and an auxiliary reference receiving channel respectively; the array element in the reference receiving channel is connected with the input end of the receiving radio frequency front end in the reference receiving channel through a first switch and is connected with the output end of the up-conversion radio frequency front end through the first switch and a second switch; the array element in the auxiliary reference receiving channel is connected with the input end of the receiving radio frequency front end in the auxiliary reference receiving channel through a third switch, and is connected with the output end of the up-conversion radio frequency front end through the third switch and the second switch;
controlling the working states of the first switch, the second switch and the third switch according to the working mode of the phased array antenna, and carrying out error correction on each receiving channel by combining a receiving correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
13. The method of claim 12, wherein obtaining the first error for each receive channel relative to the reference receive channel when the phased array antenna is operating in the error acquisition mode comprises:
controlling the working states of the first switch, the second switch and the third switch to enable the array element in the reference receiving channel to be communicated with the up-conversion radio frequency front end and the array element in the auxiliary reference receiving channel to be communicated with the receiving radio frequency front end in the auxiliary reference receiving channel;
receiving a first signal through each non-reference receive channel; the first signal is a signal which is obtained by performing up-conversion processing on the receiving correction signal through the up-conversion radio frequency front end, radiating the receiving correction signal through an array element in the reference receiving channel and receiving the processing correction signal by each non-reference receiving channel;
controlling the working states of the first switch, the second switch and the third switch so as to enable the array element in the reference receiving channel to be communicated with the receiving radio frequency front end in the reference receiving channel and the array element in the auxiliary reference receiving channel to be communicated with the up-conversion radio frequency front end;
receiving a second signal through each non-auxiliary reference receive channel; the second signal and the receiving correction signal are subjected to up-conversion processing at the up-conversion radio frequency front end, are radiated by array elements in the auxiliary reference receiving channel, and are received by each non-auxiliary reference receiving channel;
determining a first error of each receive channel relative to the reference receive channel based on the first signal, the second signal, and the receive correction signal.
14. The method of claim 13, wherein when the phased array antenna is in an error correction mode, error correcting each receive channel comprises:
controlling the working states of the first switch, the second switch and the third switch to enable the array element in the reference receiving channel to be communicated with the receiving radio frequency front end in the reference receiving channel, the array element in the auxiliary reference receiving channel to be communicated with the receiving radio frequency front end in the auxiliary reference receiving channel, and the up-conversion radio frequency front end to be communicated with the beam receiving end;
and correcting the errors of the receiving channels according to the errors of the receiving channels relative to the reference receiving channel.
15. The method of claim 13, wherein determining a first error for each receive channel relative to the reference receive channel based on the first signal, the second signal, and the receive correction signal comprises:
determining a second error of each receiving channel relative to the reference receiving channel according to the first signal and the receiving correction signal;
determining an error of the reference receive channel relative to the auxiliary reference receive channel based on the second signal and the receive correction signal;
and determining the first error of each receiving channel relative to the reference receiving channel according to the second error of each receiving channel relative to the reference receiving channel and the error of the reference receiving channel relative to the auxiliary reference receiving channel.
16. The method of claim 15, wherein determining a second error of the respective receive path relative to the reference receive path based on the first signal and the receive correction signal comprises:
determining a signal correlation value of each receiving channel according to the first signal and the receiving correction signal;
and determining a second error of each receiving channel relative to the reference receiving channel according to the signal correlation value of each receiving channel and the receiving correction signal.
17. The method of claim 15, wherein determining an error of the reference receive channel relative to the auxiliary reference receive channel based on the second signal and the receive correction signal comprises:
determining a signal correlation value of the reference receiving channel and the auxiliary reference receiving channel according to the second signal and the receiving correction signal;
and determining the error of the reference receiving channel relative to the auxiliary reference receiving channel according to the signal correlation values of the reference receiving channel and the auxiliary reference receiving channel and the receiving correction signal.
18. The method of claim 12, further comprising:
selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively; the array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch;
controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
19. The method of claim 18, wherein obtaining the first error for each transmit channel relative to the reference transmit channel when the phased array antenna is operating in the error acquisition mode comprises:
controlling the working states of the fourth switch, the fifth switch and the sixth switch to enable the array elements in the reference transmitting channel to be communicated with the down-conversion radio frequency front end, and the array elements in the auxiliary reference transmitting channel to be communicated with the transmitting radio frequency front end in the auxiliary reference transmitting channel;
receiving a third signal; the third signal is a signal which is obtained by processing the emission correction signal by each emission radio frequency front end in each non-reference emission channel, radiating the emission correction signal by an array element corresponding to each emission radio frequency front end, receiving the emission correction signal by the array element in the reference emission channel, and processing the emission correction signal by the down-conversion radio frequency front end;
controlling the working states of the fourth switch, the fifth switch and the sixth switch so as to enable the array elements in the reference transmitting channel to be communicated with the transmitting radio frequency front end in the reference transmitting channel, and the array elements in the auxiliary reference transmitting channel to be communicated with the down-conversion radio frequency front end;
receiving a fourth signal; the fourth signal is a signal which is obtained by processing the emission correction signal by each emission radio frequency front end in each non-auxiliary reference emission channel, radiating the emission correction signal by an array element corresponding to each emission radio frequency front end, receiving the emission correction signal by an array element in an auxiliary reference emission channel, and processing the emission correction signal by the down-conversion radio frequency front end;
and determining a third error of each transmitting channel relative to the reference transmitting channel according to the third signal, the fourth signal and the transmitting correction signal.
20. The method of claim 19, wherein when the phased array antenna is operating in an error correction mode, error correcting each transmit channel comprises:
controlling the working states of the fourth switch, the fifth switch and the sixth switch to enable the array elements in the reference receiving channel to be communicated with the transmitting radio frequency front end in the reference receiving channel, the array elements in the auxiliary reference receiving channel to be communicated with the transmitting radio frequency front end in the auxiliary reference receiving channel, and the up-conversion radio frequency front end to be communicated with the beam output end;
and correcting errors of the transmitting channels according to the errors of the transmitting channels relative to the reference transmitting channel.
21. The method of claim 19, wherein determining a third error for each transmit channel relative to the reference transmit channel based on the third signal, the fourth signal, and the transmit correction signal comprises:
determining a fourth error of each transmitting channel relative to the reference transmitting channel according to the third signal and the transmitting correction signal;
determining an error of the reference transmission channel relative to the auxiliary reference transmission channel according to the fourth signal and the transmission correction signal;
and determining a third error of each transmitting channel relative to the reference transmitting channel according to the fourth error of each transmitting channel relative to the reference transmitting channel and the error of the reference transmitting channel relative to the auxiliary reference transmitting channel.
22. A method of error correction for a phased array antenna, comprising:
selecting one channel from a plurality of transmitting channels of the phased array antenna as a reference transmitting channel and an auxiliary reference transmitting channel respectively; the array element in the reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the reference transmitting channel through a fourth switch and is connected with the input end of the down-conversion radio frequency front end through the fourth switch and a fifth switch; the array element in the auxiliary reference transmitting channel is connected with the output end of the transmitting radio frequency front end in the auxiliary transmitting channel through a sixth switch, and is connected with the input end of the down-conversion radio frequency front end through the sixth switch and the fifth switch; controlling the working states of the fourth switch, the fifth switch and the sixth switch according to the working mode of the phased array antenna, and performing error correction on each transmitting channel by combining a transmitting correction signal; the phased array antenna operates in a mode including an error acquisition mode and an error correction mode.
23. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 12 to 22.
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