CN111668231A - 3D NAND memory and forming method thereof - Google Patents

3D NAND memory and forming method thereof Download PDF

Info

Publication number
CN111668231A
CN111668231A CN202010466027.5A CN202010466027A CN111668231A CN 111668231 A CN111668231 A CN 111668231A CN 202010466027 A CN202010466027 A CN 202010466027A CN 111668231 A CN111668231 A CN 111668231A
Authority
CN
China
Prior art keywords
layer
silicon layer
stacked structure
amorphous silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010466027.5A
Other languages
Chinese (zh)
Other versions
CN111668231B (en
Inventor
董明
曾凡清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202010466027.5A priority Critical patent/CN111668231B/en
Publication of CN111668231A publication Critical patent/CN111668231A/en
Application granted granted Critical
Publication of CN111668231B publication Critical patent/CN111668231B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A3D NAND memory and a forming method thereof are provided, the forming method comprises the steps of providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking control gates and isolation layers is formed on the semiconductor substrate, and gate separation grooves penetrating the stacked structure in the vertical direction are formed in the stacked structure; forming a polycrystalline silicon layer on the side wall and the bottom surface of the grid isolation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove. The stress of the array common source formed by the method is small, and the bending or deformation of the stacked structure is prevented.

Description

3D NAND memory and forming method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a 3D-reduced NAND memory and a method thereof.
Background
The NAND flash memory is a nonvolatile memory product with low power consumption, light weight and good performance, and is widely applied to electronic products. At present, a NAND flash memory with a planar structure is approaching the limit of practical expansion, and in order to further improve the storage capacity and reduce the storage cost per bit, a NAND memory with a 3D structure is proposed.
The formation process of existing 3D NAND memories generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on a substrate; etching the stacked structure to form a channel through hole in the stacked structure, etching the substrate at the bottom of the channel through hole after the channel through hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the trench via by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a charge storage layer and a channel layer in the channel through hole, wherein the channel layer is connected with the epitaxial silicon layer; forming gate spacers penetrating the stacked structure; removing the sacrificial layer along the grid isolation groove, and forming a control grid or a word line at the position where the sacrificial layer is removed; and filling a polysilicon layer in the grid isolation groove to form an array common source.
The stress of the conventional array common source is high, and the bending or deformation of the stacked structure is easily caused.
Disclosure of Invention
The invention aims to solve the technical problem of how to reduce the stress of an array common source and prevent the bending or deformation of a stacked structure.
To this end, the present invention provides a method of forming a 3D NAND memory, comprising:
providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking a control gate and an isolation layer is formed on the semiconductor substrate, and a gate separation groove penetrating through the stacked structure along the vertical direction is formed in the stacked structure;
forming a polycrystalline silicon layer on the side wall and the bottom surface of the grid isolation groove;
forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer;
and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove.
Optionally, the polysilicon layer forming process is a chemical vapor deposition process.
Optionally, the amorphous silicon layer is formed by chemical vapor deposition.
Optionally, before annealing, the polysilicon layer and the amorphous silicon layer with a part of thickness in the gate isolation trench are removed by etching back, a metal layer is formed on the surfaces of the polysilicon layer and the amorphous silicon layer remaining in the gate isolation trench, the gate isolation trench is filled with the metal layer, and the metal layer is a part of the array common source.
Optionally, the metal layer is made of one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
Optionally, the annealing is spike annealing, and the annealing temperature is 950-1050 ℃.
Optionally, before forming the polysilicon layer on the sidewall and the bottom surface of the gate isolation trench, an isolation sidewall is formed on the sidewall of the gate isolation trench.
Optionally, a plurality of channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure on the two sides of the gate separation groove, and a storage structure is formed in each channel through hole.
Optionally, the storage structure includes a charge storage layer on a sidewall surface of the trench via and a channel layer on a sidewall surface of the charge storage layer, where the charge storage layer includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.
Optionally, a plurality of dummy channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure on both sides of the gate separation groove, and a dummy channel structure is formed in the dummy channel through holes.
The present invention also provides a 3D NAND memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a stacked structure formed by alternately stacking control gates and isolation layers is formed on the semiconductor substrate, and gate separation grooves penetrating the stacked structure in the vertical direction are formed in the stacked structure;
the array common source is positioned in the grid separation groove, the array common source is made of a polycrystalline silicon layer, and the polycrystalline silicon layer is formed on the side wall and the bottom surface of the grid separation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing to convert the amorphous silicon layer into a polysilicon layer.
Optionally, the array common source further includes a metal layer on the surface of the amorphous silicon layer.
Optionally, an isolation sidewall is further disposed on the sidewall of the gate spacer.
Optionally, a plurality of channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure on two sides of the gate separation groove, a storage structure is formed in each channel through hole, and each storage structure comprises a charge storage layer located on the surface of the side wall of each channel through hole and a channel layer located on the surface of the side wall of each charge storage layer.
Optionally, the charge storage layer includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.
Optionally, a plurality of dummy channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure on both sides of the gate separation groove, and a dummy channel structure is formed in the dummy channel through holes.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the forming method of the 3D NAND memory comprises the steps of providing a semiconductor substrate, wherein a stacked structure with control gates and isolation layers stacked alternately is formed on the semiconductor substrate, and gate separation grooves penetrating the stacked structure in the vertical direction are formed in the stacked structure; forming a polycrystalline silicon layer on the side wall and the bottom surface of the grid isolation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove. The method enables the stress of the formed array common source to be small through the specific steps, and bending or deformation of the stacked structure is prevented.
The stress of the array common source of the 3D NAND memory is small, and the bending or deformation of the stacked structure is prevented.
Drawings
FIGS. 1-6 are schematic structural diagrams illustrating a 3D NAND memory formation process according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the stress of the common source of the array formed in the prior art is high, which is likely to cause the bending or deformation of the stacked structure.
Research finds that, in one embodiment, the formation process of the array common source comprises the following steps: filling amorphous silicon layers in the grid isolation grooves of the stacked structure; and annealing is carried out, and the amorphous silicon layer is converted into a polycrystalline silicon layer to form an array common source. In the existing process for forming the array common source, the stress of the formed array common source is high.
The invention provides a 3D NAND memory and a forming method thereof, wherein the forming method comprises the steps of providing a semiconductor substrate, forming a stacked structure on the semiconductor substrate, wherein control gates and isolation layers are alternately stacked, and forming gate separation grooves penetrating the stacked structure along the vertical direction in the stacked structure; forming a polycrystalline silicon layer on the side wall and the bottom surface of the grid isolation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove. The stress of the array common source formed by the method is small, and the bending or deformation of the stacked structure is prevented.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-6 are schematic structural views illustrating a 3D NAND formation process according to another embodiment of the invention.
Referring to fig. 1, a semiconductor substrate 100 is provided, a stacked structure 111 formed by alternately stacking control gates 127 and isolation layers 104 is formed on the semiconductor substrate 100, and a gate spacer 205 penetrating the stacked structure 111 in a vertical direction is formed in the stacked structure 11.
The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).
The control gate 127 and the isolation layer 104 are alternately stacked, that is: a control gate 127 has a corresponding spacer 104 thereon, the control gate 127 and spacers 104 being alternately arranged. In this embodiment, the Bottom layer of the stacked structure 111 is a control Gate, the Top layer is an isolation layer 104, the Bottom layer of the control Gate in the stacked structure is used as a Bottom Select Gate (BSG) 128, and the Top layer of the control Gate in the stacked structure 111 is used as a Top Select Gate (TSG) 129. The number of layers of the stacked structure 111 is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the stacked structure 111, the higher the integration level can be.
In an embodiment, the control gate 127 includes a high-K dielectric layer and a metal gate located on the surface of the high-K dielectric layer, and the metal gate may be made of one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. HfO as the material of the high-K dielectric layer2、TiO2、HfZrO、HfSiNO、Ta2O5、ZrO2、ZrSiO2、Al2O3、SrTiO3Or BaSrTiO. In other embodiments, the control gate 127 may include a silicon oxide dielectric layer and a polysilicon gate on the dielectric layer. The material of the isolation layer 104 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
A plurality of channel through holes and dummy channel through holes vertically penetrating through the stacked structure 111 are formed in the stacked structure on both sides of the gate spacer 205, a storage structure 119 is formed in the channel through holes, and a dummy channel structure (not shown in the figure) is formed in the dummy channel through holes.
The memory structure 119 includes a charge storage layer 118 on a sidewall surface of the channel via and a channel layer 117 on a sidewall surface of the charge storage layer 118.
In one embodiment, the charge storage layer 118 includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer; the channel layer 117 fills the remaining channel vias. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the channel layer 117 material may be polysilicon doped with N-type impurity ions, such as phosphorus ions. In a specific embodiment, the charge storage layer 118 may be a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).
The dummy channel structure may be a single-layer or multi-layer stacked structure, and is used for stacking structures in a manufacturing process.
In one embodiment, a groove is formed in the semiconductor substrate 100 at the bottom of the trench via, the first semiconductor epitaxial layer 116 is formed in the groove and in a part of the trench via, the top surface of the first semiconductor epitaxial layer 116 is higher than the top surface of the bottom select gate 128 and is lower than the top surface of the lowermost isolation layer 104, the material of the first semiconductor epitaxial layer 116 may be silicon, germanium or silicon germanium, and the memory structure 119 is located in the trench via on the first semiconductor epitaxial layer 116; the top surface of the memory structure 119 is higher than the top surface of the top select gate 106 than the top surface of the topmost isolation layer 104, a connection plug 120 is formed on the top surface of the memory structure 119, and the material of the connection plug 120 may be silicon, germanium, silicon germanium or metal.
In a specific embodiment, the formation of the control gate 127, the first semiconductor epitaxial layer 116, the memory structure 119 and the gate spacer 205 generally comprises: forming a stacked structure in which isolation layers 104 and sacrificial layers are alternately stacked on a semiconductor substrate; etching the stacked structure to form a channel through hole in the stacked structure; after the channel through hole is formed, etching the substrate at the bottom of the channel through hole, and forming a groove in the substrate; forming a first semiconductor Epitaxial layer 116(SEG) by Selective Epitaxial Growth (Selective Epitaxial Growth) in the groove at the bottom of the channel via and in a portion of the channel via above the groove; forming a charge storage layer and a channel layer in a channel via on the first semiconductor epitaxial layer 116; forming gate spacers 205 through the stacked structure; the sacrificial layer is removed along the gate spacer and a control gate 127 or word line is formed where the sacrificial layer is removed.
In one embodiment, the formation of the charge storage layer 118 and the channel layer 117 includes: forming a charge storage layer 118 on the sidewall and the bottom of the trench via, the charge storage layer 118 including a blocking layer on the sidewall and the bottom surface of the trench via, a charge trapping layer on the surface of the blocking layer, and a tunneling layer on the surface of the charge trapping layer; forming a first channel layer on the charge storage layer 118; etching to remove the first channel layer and the charge storage layer on the bottom of the channel through hole, and forming an opening exposing the surface of the first semiconductor epitaxial layer 116; a second channel layer is formed in the opening and on the surface of the first channel layer, the second channel layer and the first channel layer constituting a channel layer 117. It should be noted that the trench layer 117 may be filled or not filled with a channel via, and when the channel layer 117 is not filled with a channel via, a filling layer filled with a channel via needs to be further formed on the surface of the channel layer 117, where the material of the filling layer may be silicon oxide.
In an embodiment, referring to fig. 2, isolation spacers 121 are formed on sidewalls of the gate spacers 205.
The isolation sidewall spacers 121 are used for isolation between the array common source and the control gate 127 formed in the gate spacer 205. The material of the isolation sidewall 121 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide. In this embodiment, the isolation sidewall 121 is made of silicon oxide.
In an embodiment, the forming process of the isolation sidewall spacers 121 is as follows: forming a side wall material layer on the side wall and the bottom surface of the gate isolation groove 205 and the surface of the stacked structure; and removing the side wall material layer on the bottom of the gate isolation groove and the surface of the stacked structure by maskless etching, and forming a side wall 121 on the side wall surface of the gate isolation groove 205.
Referring to fig. 3, a polysilicon layer 122 is formed on the sidewalls and bottom surface of the gate spacer 205.
In one embodiment, the thickness of the polysilicon layer 122 is about 25-35nm, and may be 30 nm.
The polysilicon layer 122 is a first polysilicon layer that is subsequently used as part of the common source of the array.
Referring to fig. 4, an amorphous silicon layer 123 is formed on the surface of the polysilicon layer 122, and the amorphous silicon layer 123 fills the gate spacer.
The amorphous silicon layer 123 is formed for the purpose of: the amorphous silicon layer can be converted into a polycrystalline silicon layer through subsequent annealing, and the converted polycrystalline silicon layer is also used as a part for forming the array common source.
The amorphous silicon layer is formed by chemical vapor deposition.
It should be noted that the formed polysilicon layer 122 and the amorphous silicon layer 123 may cover the surface of the stacked structure on both sides of the gate spacer.
In an embodiment, referring to fig. 5, after the amorphous silicon layer 123 is formed, a back etching process is performed to remove a part of the thickness of the polysilicon layer 122 and the amorphous silicon layer 123 in the gate spacer, and a metal layer 124 is formed on the surface of the remaining polysilicon layer 122 and amorphous silicon layer 123 in the gate spacer, where the metal layer 124 fills the gate spacer and the metal layer 124 serves as a part of the common source of the array.
The material of the metal layer 124 may be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
In other embodiments, the amorphous silicon layer 123 may be annealed first to form the array common source in the gate spacer; after annealing to form an array common source, etching back to remove part of the thickness of the array common source in the grid isolation groove; and forming a metal layer 124 on the surface of the array common source electrode remaining in the gate isolation groove, wherein the metal layer 124 fills the gate isolation groove, and the metal layer 124 is used as a part of the array common source electrode.
Referring to fig. 6, an anneal is performed to convert the amorphous silicon layer 123 (see fig. 4 or fig. 5) into a polysilicon layer 125, forming an array common source in the gate spacer.
The polysilicon layer 125 is a second polysilicon layer, and the polysilicon layer 125 is a part of the common source of the array.
The annealing is spike annealing, the annealing temperature is 950-1050 ℃, specifically 950, 980, 1000, 1050 ℃, and at the annealing temperature, the amorphous silicon layer 123 can be quickly converted into the polysilicon layer 125, the stress of the formed polysilicon layer 125 is small, and the stress between the polysilicon layer 125 and the polysilicon layer 122 is also small.
According to the method for forming the array common source, after the polycrystalline silicon layer is formed on the side wall and the bottom surface of the grid isolation groove, the amorphous silicon layer is formed on the surface of the polycrystalline silicon layer, and the grid isolation groove is filled with the amorphous silicon layer; and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove. The method enables the stress of the formed array common source to be small through the specific steps, and bending or deformation of the stacked structure is prevented.
An embodiment of the present invention further provides a 3D NAND memory, referring to fig. 6, including:
the semiconductor device comprises a semiconductor substrate 100, wherein a stacked structure 111 formed by alternately stacking control gates 127 and isolation layers 104 is formed on the semiconductor substrate 100, and a gate separation groove penetrating through the stacked structure along the vertical direction is formed in the stacked structure 111;
the array common source 126 is positioned in the gate separation groove, the material of the array common source 126 is a polysilicon layer, and the polysilicon array common source is formed by forming a polysilicon layer (a first polysilicon layer) on the side wall and the bottom surface of the gate separation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing to convert the amorphous silicon layer into a polysilicon layer (second polysilicon layer).
Specifically, in one embodiment, the array common source further includes a metal layer 124 on the surface 126 of the amorphous silicon layer.
And the side wall of the gate isolation groove is also provided with an isolation side wall 121, and the isolation side wall is positioned between the surface of the side wall of the gate isolation groove and the array common source 126.
A plurality of channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure 111 on two sides of the gate isolation groove, a storage structure 119 is formed in each channel through hole, and each storage structure 119 comprises a charge storage layer 118 located on the surface of the side wall of each channel through hole and a channel layer 117 located on the surface of the side wall of each charge storage layer 118.
In one embodiment, the charge storage layer 118 includes a blocking layer on sidewall surfaces of the trench via, a charge trapping layer on sidewall surfaces of the blocking layer, and a tunneling layer on sidewall surfaces of the charge trapping layer.
In an embodiment, a plurality of dummy channel through holes vertically penetrating through the stacked structure are further formed in the stacked structure on both sides of the gate isolation groove, and a dummy channel structure is formed in the dummy channel through holes.
It should be noted that other limitations or descriptions related to the 3D NAND memory in this embodiment are not repeated in this embodiment, and please refer to relevant limitations or descriptions of the 3D NAND memory forming process in the foregoing embodiment specifically.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (16)

1. A method for forming a 3D NAND memory, comprising:
providing a semiconductor substrate, wherein a stacked structure formed by alternately stacking a control gate and an isolation layer is formed on the semiconductor substrate, and a gate separation groove penetrating through the stacked structure along the vertical direction is formed in the stacked structure;
forming a polycrystalline silicon layer on the side wall and the bottom surface of the grid isolation groove;
forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer;
and annealing is carried out, the amorphous silicon layer is converted into a polycrystalline silicon layer, and an array common source is formed in the grid isolation groove.
2. The method of forming a 3D NAND memory of claim 1 wherein the process of forming the polysilicon layer is a chemical vapor deposition process.
3. The method of claim 1, wherein the amorphous silicon layer is formed by chemical vapor deposition.
4. The method of claim 1, wherein the annealing is performed before etching back to remove a portion of the thickness of the polysilicon layer and the amorphous silicon layer in the gate spacer, and a metal layer is formed on the surface of the remaining polysilicon layer and amorphous silicon layer in the gate spacer, wherein the metal layer fills the gate spacer and is a portion of the common source of the array.
5. The method of claim 4, wherein the metal layer is made of one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.
6. The method of forming a 3D NAND memory as claimed in claim 1 or claim 4 wherein the anneal is a spike anneal and the temperature of the anneal is 950 to 1050 degrees Celsius.
7. The method of claim 1, wherein isolation spacers are formed on the sidewalls of the gate spacer prior to forming the polysilicon layer on the sidewalls and bottom surface of the gate spacer.
8. The method of claim 1, wherein the stacked structures on both sides of the gate spacer are further formed with channel vias vertically penetrating the stacked structures, and the channel vias are formed with storage structures therein.
9. The method of forming a 3D NAND memory of claim 8 wherein the memory structure includes a charge storage layer on a sidewall surface of the trench via and a channel layer on a sidewall surface of the charge storage layer, the charge storage layer including a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.
10. The method of claim 1, wherein dummy channel vias are formed in the stacked structure on both sides of the gate spacer and vertically penetrate through the stacked structure, and dummy channel structures are formed in the dummy channel vias.
11. A3D NAND memory, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a stacked structure formed by alternately stacking control gates and isolation layers is formed on the semiconductor substrate, and gate separation grooves penetrating the stacked structure in the vertical direction are formed in the stacked structure;
the array common source is positioned in the grid separation groove, the array common source is made of a polycrystalline silicon layer, and the polycrystalline silicon layer is formed on the side wall and the bottom surface of the grid separation groove; forming an amorphous silicon layer on the surface of the polycrystalline silicon layer, wherein the gate isolation groove is filled with the amorphous silicon layer; and annealing to convert the amorphous silicon layer into a polysilicon layer.
12. The 3D NAND memory of claim 11 wherein the array common source further comprises a metal layer on a surface of an amorphous silicon layer.
13. The 3D NAND memory of claim 11 wherein the gate spacer has isolation spacers on sidewalls thereof.
14. The 3D NAND memory of claim 11 wherein the stacked structure on both sides of the gate spacer is further formed with channel vias vertically penetrating the stacked structure, the channel vias having memory structures formed therein, the memory structures including a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.
15. The 3D NAND memory of claim 14 wherein the charge storage layer comprises a blocking layer on sidewall surfaces of the trench via, a charge trapping layer on sidewall surfaces of the blocking layer, and a tunneling layer on sidewall surfaces of the charge trapping layer.
16. The 3D NAND memory of claim 11 wherein the stacked structures on both sides of the gate spacer are further formed with dummy channel vias vertically penetrating the stacked structures, the dummy channel vias having dummy channel structures formed therein.
CN202010466027.5A 2020-05-28 2020-05-28 3D NAND memory and forming method thereof Active CN111668231B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010466027.5A CN111668231B (en) 2020-05-28 2020-05-28 3D NAND memory and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010466027.5A CN111668231B (en) 2020-05-28 2020-05-28 3D NAND memory and forming method thereof

Publications (2)

Publication Number Publication Date
CN111668231A true CN111668231A (en) 2020-09-15
CN111668231B CN111668231B (en) 2021-03-30

Family

ID=72384915

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010466027.5A Active CN111668231B (en) 2020-05-28 2020-05-28 3D NAND memory and forming method thereof

Country Status (1)

Country Link
CN (1) CN111668231B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170084455A1 (en) * 2014-11-19 2017-03-23 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
CN107731833A (en) * 2017-08-31 2018-02-23 长江存储科技有限责任公司 A kind of array common source interstitital texture and preparation method thereof
CN110211960A (en) * 2019-06-20 2019-09-06 长江存储科技有限责任公司 A kind of 3D nand memory part and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170084455A1 (en) * 2014-11-19 2017-03-23 Hitachi Kokusai Electric Inc. Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
CN107731833A (en) * 2017-08-31 2018-02-23 长江存储科技有限责任公司 A kind of array common source interstitital texture and preparation method thereof
CN110211960A (en) * 2019-06-20 2019-09-06 长江存储科技有限责任公司 A kind of 3D nand memory part and its manufacturing method

Also Published As

Publication number Publication date
CN111668231B (en) 2021-03-30

Similar Documents

Publication Publication Date Title
CN110112134B (en) 3D NAND memory and forming method thereof
CN110176461B (en) 3D NAND memory and forming method thereof
CN110211965B (en) 3D NAND memory and forming method thereof
US8163617B2 (en) Vertical channel type non-volatile memory device and method for fabricating the same
US9373636B2 (en) Methods of forming semiconductor constructions
US9431416B2 (en) Vertical-type nonvolatile memory device and method of manufacturing the same
US10636808B2 (en) Vertical memory device having an epitaxial layer in contact with a channel layer
US9105666B2 (en) Methods of fabricating semiconductor structures
CN109817634B (en) 3D NAND memory and forming method thereof
CN111540752B (en) 3D NAND memory and forming method thereof
CN110289263B (en) 3D NAND memory and forming method thereof
CN110197830B (en) 3D NAND memory and forming method thereof
US20210151461A1 (en) Semiconductor devices
US20190378854A1 (en) Semiconductor device and method of manufacturing the same using preliminary sacrificial layers
CN111564448B (en) Memory and forming method thereof
CN111785733A (en) Method for forming 3D NAND memory
US10276589B2 (en) Method of manufacturing semiconductor device
CN110265402B (en) 3D NAND memory device and manufacturing method thereof
US11404433B2 (en) Vertical memory devices
CN111403400A (en) Array common source of memory and forming method thereof
CN111668231B (en) 3D NAND memory and forming method thereof
CN112331671B (en) Method for forming 3D NAND memory
CN111785727B (en) 3D NAND memory and forming method thereof
CN112864170B (en) Three-dimensional memory and preparation method thereof
CN114171533A (en) 3D NAND memory and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant