CN111668117B - Packaging method of semiconductor module and two structures in packaging process of semiconductor module - Google Patents
Packaging method of semiconductor module and two structures in packaging process of semiconductor module Download PDFInfo
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- CN111668117B CN111668117B CN201910177331.5A CN201910177331A CN111668117B CN 111668117 B CN111668117 B CN 111668117B CN 201910177331 A CN201910177331 A CN 201910177331A CN 111668117 B CN111668117 B CN 111668117B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
The application discloses a packaging method of a semiconductor module and two structures in the packaging process of the semiconductor module. The packaging method comprises the steps of providing at least one semiconductor module to be packaged, wherein the semiconductor module is provided with an effective surface and an ineffective surface; providing a carrier plate, and attaching the semiconductor module on the carrier plate with an effective surface facing the carrier plate; forming an encapsulation layer with a first preset thickness on the invalid surface of the semiconductor module and the exposed surface of the carrier plate; and removing the second preset thickness of the encapsulation layer to form the encapsulation layer with the target thickness. In another aspect, the application provides two structural embodiments in the packaging process corresponding to the above packaging method. According to the scheme, the thicker encapsulation layer is formed in advance, and then the encapsulation layer with the preset thickness is removed to form the encapsulation layer with the target thickness, so that the problem of encapsulation quality caused by more defects at the top of the encapsulation layer when the encapsulation layer with the target thickness is manufactured in one step is solved.
Description
Technical Field
The application relates to the field of semiconductor packaging, in particular to a semiconductor fan-out plate level packaging process flow and structure.
Background
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller semiconductor devices generally consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have smaller footprints, which provides the possibility to achieve smaller end products. Smaller semiconductor chips can be realized with front-end process improvements, resulting in smaller, higher density active and passive components for the semiconductor chip. Back-end processing may result in semiconductor packaged devices with smaller footprints through improvements in electrical interconnections and packaging materials.
One method of processing the back end of a packaged semiconductor device to more efficiently produce is fan-out plate level packaging. One form of fan-out board level package is a fan-out wafer level package, which is not described in any great detail herein. Another form of fan-out board level package is a fan-out board level package, generally processed as shown in fig. 1-2. As shown in fig. 1, a protective layer 2 is formed on a wafer 1 on which a chip 10 is fabricated, and an opening 20 is formed on the protective layer 2. The subsequent process will divide the wafer 1 into a plurality of chips 10. As shown in fig. 2, the plurality of chips 10 are disposed on the carrier 3 with the surface of the protective layer 2 facing the carrier 30. Typically, the surface of the carrier 3 on which the chip 10 is disposed is attached with an adhesive layer 30, so that the chip 10 is adhered to the carrier 3. The side of the chip where the protective layer 2 is located is the active side of the chip, which is interconnected with the metal outside the chip through the opening 20, while the other side of the chip opposite to the protective layer 2 is the back side of the chip, which is the inactive side of the chip. The carrier plate 3 can be removed in a subsequent process by simultaneously overmolding the inactive faces of several chips 10 on the carrier plate 3.
As the packaged chip finished product tends to be thinner, the plastic sealing layer for wrapping the chip is naturally thinner. However, in the process of forming the plastic sealing layer by the over-molding, the cavity defect is easily caused by the bubbles in the plastic sealing layer, so that the packaging quality of the chip is easily reduced.
Disclosure of Invention
The application provides a packaging method of a semiconductor module and a structure in a packaging process of the semiconductor module.
One aspect of the present application provides a method for packaging a semiconductor module, including: providing at least one semiconductor module to be packaged, wherein the semiconductor module is provided with an effective surface and an ineffective surface; providing a carrier plate, and attaching the semiconductor module on the carrier plate with an effective surface facing the carrier plate; forming an encapsulation layer with a first preset thickness on the invalid surface of the semiconductor module and the exposed surface of the carrier plate; and removing the second preset thickness of the encapsulation layer to form the encapsulation layer with the target thickness.
The object of this is to improve the quality of the encapsulation layer by removing the second predetermined thickness of the encapsulation layer on top to form the encapsulation layer of the target thickness, and to eliminate the effect of the defect of the encapsulation layer on the encapsulation quality of the semiconductor module, if the defect of the encapsulation layer is easily generated on top of the defect under the limitation of the process conditions. Thus, the problem of the packaging quality of the semiconductor chip caused by the cavity defect in the plastic sealing layer mentioned in the background art can be solved.
Further, the encapsulation layer with the first preset thickness is formed by adopting a molding hot-pressing process. The molding hot-pressing process comprises the following steps: step S1: placing the carrier plate on which the semiconductor module to be packaged is attached in a hot-pressing die; step S2: filling solid encapsulation particles between the hot-pressing mold and the semiconductor module to be encapsulated; step S3: heating the solid encapsulated particles in step S2 to form a liquid encapsulant; step S4: and hot-pressing the liquid encapsulating material, and cooling to form an encapsulating layer with a first preset thickness. Under this manufacturing process, in order to prevent the liquid encapsulating material from entering the back plate of the carrier plate, the back surface of the carrier plate needs to be tightly attached to the hot-pressing mold. The solid encapsulated particles are solid particles or powder resins. The resin material is selected because the thermal expansion coefficient of the material is the same as or close to that of the semiconductor module, and the cost is relatively low.
Further, removing the encapsulation layer with the second preset thickness by adopting a grinding process.
Therefore, the encapsulation layer is not required to be made too thick when the encapsulation layer with the first preset thickness is formed, which takes a long time when the encapsulation layer with the second preset thickness is removed by adopting a grinding process later, and meanwhile, waste of materials is easy to generate. Therefore, it is necessary to determine the thickness of the encapsulation layer according to the grinding accuracy of the grinder, the speed, and the defect localization of the encapsulation layer formed by the molding hot press process. The first predetermined thickness of the encapsulation layer should be greater than 0.3mm, depending on the current encapsulation process and process equipment. In combination with the current distribution of void defects of the encapsulation layer and the precision of the grinder station, the first preset thickness of the encapsulation layer is preferably 0.35mm.
Typically the carrier plate comprises a carrier plate layer and an adhesive layer. The adhesive layer may help to fix the semiconductor module in a predetermined position. In order to facilitate the grinding machine to hold the carrier plate for grinding the encapsulation layer with the first preset thickness, the carrier plate layer is preferably a carrier plate made of metal magnetic material. Also, the material of the carrier layer may be selected according to the characteristics of the grinder, so that the grinder is easy to grip, and is not limited to the magnetic material defined herein. In order to make the encapsulation layer adhere well to the inactive surface of the semiconductor module and the exposed carrier plate, the thermal expansion coefficient of the carrier plate layer is preferably similar or identical to that of the encapsulation layer.
The semiconductor module at least comprises one semiconductor chip. The circuit surface of the semiconductor chip corresponds to the effective surface of the semiconductor module. In order to prevent the circuit surface of the semiconductor chip from being polluted and damaged in the subsequent packaging process, a protective layer is attached to the circuit surface of the semiconductor chip, and an opening is arranged at a position, corresponding to a welding pad in the circuit surface of the semiconductor chip, of the protective layer so as to realize rewiring of the semiconductor chip or electric connection with other conductive units through the opening in the subsequent packaging process. The semiconductor module may further include a conductive unit. The conductive element may be, for example, some passive device or an electrical element that cannot be integrated with the semiconductor chip.
In a subsequent packaging process, the carrier plate may be removed, typically after forming an encapsulation layer of a target thickness. This is done so as to expose the circuit face of the semiconductor chip. And forming a first layer of rewiring structure on the protective layer of the semiconductor chip, wherein the first layer of rewiring structure is used for electrically connecting the welding pad of the circuit surface of the semiconductor chip and forming an electrical connection point of the semiconductor chip on the first layer of rewiring structure.
When the semiconductor module further comprises a conductive unit, a first layer of rewiring structure is formed on the protective layer, and the bonding pads are used for electrically connecting the circuit surface of the semiconductor chip and forming the electrical connection points of the semiconductor chip on the first layer of rewiring structure, and meanwhile, the electrical connection between the semiconductor chip and the conductive unit is realized and/or the electrical connection points of the conductive unit on the first layer of rewiring structure are formed.
Another aspect of the present application proposes two structures in a semiconductor module packaging process. The first structure includes: an encapsulation layer of a first preset thickness, the encapsulation layer being provided with an inner cavity; at least one semiconductor module having an active surface and an inactive surface; the semiconductor module is arranged in the inner concave cavity body, and the ineffective surface of the semiconductor module faces the inner concave cavity body; the semiconductor module is arranged at a preset position of the carrier plate, and the effective surface of the semiconductor module faces the carrier plate. The second structure includes: an encapsulation layer of a target thickness, the encapsulation layer being provided with an inner cavity; at least one semiconductor module having an active surface and an inactive surface; the semiconductor module is arranged in the inner cavity body, and the ineffective surface of the semiconductor module faces the inner cavity body; the semiconductor module is arranged at a preset position of the carrier plate, and the effective surface of the semiconductor module faces the carrier plate. In both structures, the thickness of the encapsulation layer of the target thickness in the second structure is thinner than the first predetermined thickness of the encapsulation layer in the first structure. Carrier plate
In another aspect of the present application, another embodiment of two structures in a semiconductor module packaging process is provided, wherein a first preset thickness of an encapsulation layer in a first structure is greater than 0.3mm, and a target thickness is less than or equal to 0.3mm. Preferably, the first predetermined thickness of the encapsulation layer in the first construction is about 0.35mm. In some other embodiments, a surface of the encapsulation layer of the first predetermined thickness remote from the active face of the semiconductor module is at least 0.05mm higher than a surface of the encapsulation layer of the target thickness remote from the active face of the semiconductor module.
Further, in other embodiments, the two structures further include an adhesion layer, and the adhesion layer is located between the carrier and the active surface of the semiconductor module.
Further, in other embodiments, a sealing layer is further included in both structures, the sealing layer being located between the adhesive layer and the encapsulation layer.
Further, in order to facilitate the grinding machine to grasp the structure in the packaging process of the semiconductor module, at least part of the area of the carrier plate of the encapsulation layer with the first preset thickness is made of magnetic materials. Furthermore, the whole carrier plate is made of metal magnetic materials so as to facilitate the manufacture of the carrier plate. In order to make the manufactured encapsulation layer be well attached to the carrier plate, the carrier plate is not easy to naturally peel off, and the thermal expansion coefficient of the carrier plate is the same as or similar to that of the encapsulation layer.
According to the packaging method and the packaging structure of the semiconductor module, the packaging layer of the semiconductor module is manufactured through two processes, so that the bubble defect of the packaging layer can be effectively reduced, meanwhile, bubbles are not required to be discharged by using the pressure of the press in the molding hot-pressing process, the requirement on the performance of the press in the molding hot-pressing process is reduced, and the energy consumption of the press is reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional wafer divided into semiconductor chips to be packaged;
fig. 2 is a schematic diagram of a conventional semiconductor chip to be packaged mounted on a carrier;
fig. 3 is a schematic diagram illustrating an embodiment of a semiconductor module packaging method provided in the present application;
fig. 4 is a schematic diagram illustrating a manufacturing embodiment of a first preset thickness encapsulating layer in the semiconductor module packaging method provided in the present application;
fig. 5 is a schematic diagram illustrating a manufacturing embodiment of an encapsulation layer with a target thickness in the semiconductor module packaging method provided in the present application;
fig. 6 (a) and 6 (b) are schematic views illustrating two embodiments of structures in the semiconductor module packaging process according to another aspect of the present application;
fig. 7 (a) and 7 (b) are schematic views illustrating another embodiment of two structures in the semiconductor module packaging process according to another aspect of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of methods or structures that are consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
One aspect of the present application provides a method of packaging a semiconductor module. In one embodiment, the packaging method includes: providing at least one semiconductor module to be packaged, wherein the semiconductor module is provided with an effective surface and an ineffective surface; providing a carrier plate, and attaching the semiconductor module on the carrier plate with an effective surface facing the carrier plate; forming an encapsulation layer with a first preset thickness on the invalid surface of the semiconductor module and the exposed surface of the carrier plate; and removing the second preset thickness of the encapsulation layer to form the encapsulation layer with the target thickness.
In this embodiment, the process steps related to the manufacture of the encapsulation layer are mainly described, and the steps of other procedures may be inserted in the above-provided process steps, which are not limited to the above-described process steps. The purpose of making the encapsulation layer is to improve the quality of the encapsulation layer by removing the encapsulation layer with the second preset thickness on the top to form the encapsulation layer with the target thickness if the defect of the encapsulation layer is easy to generate on the top under the limitation of the process condition, and eliminate the influence of the defect of the encapsulation layer on the encapsulation quality of the semiconductor module.
The semiconductor module here comprises at least one semiconductor chip to be packaged. In other embodiments, the semiconductor module may further include conductive elements that are not typically integrated with the semiconductor chip or require off-chip electrical interconnection with the semiconductor chip. In the embodiments shown in the drawings, the specific conductive elements are not shown, and it should be understood from the above description that the semiconductor module may include off-chip passive devices such as antennas, inductors or capacitors, or conductive elements formed by them, or metal pillars, etc., without being limited to the devices illustrated herein. With the development of panel-level packaging technology, more and more devices can be interconnected and packaged with semiconductor chips (bare chips, unpackaged semiconductor chips) on a chip in the future, so as to achieve the effect of reducing the product size, improve the packaging output and reduce the packaging cost.
Here, the effective surface and the ineffective surface of the semiconductor module will be described: since the semiconductor module at least comprises a semiconductor chip to be packaged, the circuit surface of the semiconductor chip corresponds to the effective surface of the semiconductor module, and the back surface of the semiconductor chip corresponds to the ineffective surface of the semiconductor module. If the semiconductor module further includes other conductive units, the surface where the electrical interconnection is required or the electrical connection point is located corresponds to the effective surface of the semiconductor module, and the surface where the electrical interconnection is not required or the electrical connection point is not located corresponds to the ineffective surface of the semiconductor module.
In order to prevent the semiconductor module from being disturbed by the external environment and affecting the performance or stability thereof, it is necessary to package the semiconductor module. The package is typically insulated over the exterior of the semiconductor module. In this case, a complete packaging process of the entire semiconductor module is not completely described, and only innovative parts made in the packaging process are relatively completely disclosed, and emphasis is placed on explaining and explaining the manufacturing method and structure of the ineffective surface package of the semiconductor module.
Referring to fig. 3, fig. 3 is an exemplary illustration of a semiconductor module including only semiconductor chips. The number of semiconductor chips packaged in panel level is not limited to the number shown in the figure, but in order to improve the packaging yield, it is of course better to have more semiconductor modules on the same carrier plate that can be packaged simultaneously. As shown in fig. 3, a plurality of semiconductor chips 10 are mounted on the carrier 3, and the adhesive layer 30 on the carrier 3 facilitates mounting the circuit surface of the semiconductor chips 10 on the carrier 3. One of the functions of the adhesive layer 30 is to enable the side of the semiconductor chip 10 having the protective layer 2 to be mounted on the carrier 3 relatively firmly. The adhesive layer 30 may be made of a material that is easily peeled so as to peel the carrier 3 and the back-side packaged semiconductor chip 10 apart. For example, a thermal separation material which can be made to lose its tackiness by heating can be used. In other embodiments, the adhesive layer 3 may be a two-layer structure, a thermal separation material layer and a chip attach layer. The thermal separation material layer is adhered to the carrier plate 3, loses viscosity when heated, and can be peeled off from the carrier plate 3, and the chip adhesion layer adopts the material layer with viscosity, which can be used for adhering the semiconductor chip 10 to be packaged. After the semiconductor chip 10 is peeled from the carrier plate 3, the chip attachment layer thereon may be removed by chemical cleaning. In an embodiment, the adhesive layer 30 may be formed on the carrier plate 3 by lamination, printing, or the like.
In an embodiment, referring to fig. 3, an encapsulation layer 4 with a first thickness PH is formed on the surface of the carrier 3 to which the semiconductor chip 10 is attached in advance to improve the quality of the back surface encapsulation layer of the semiconductor chip. It can be seen that there are more defects 41 in the upper part of the encapsulation layer 4 of the first thickness PH. In the exemplary illustration, the material of the encapsulation layer 4 is illustrated as a resin-based material, and the defect 41 is mainly a void defect, but other defects are not excluded. In the subsequent process, the encapsulating layer 4 with a proper thickness on the upper part can be removed to form the encapsulating layer 4 with the target thickness TH. Therefore, the quality of the back surface sealing layer of the semiconductor chip can be effectively improved, and the packaging quality problem caused by the defect at the top of the sealing layer is reduced.
In other embodiments of the encapsulation method, referring to fig. 4, fig. 4 illustrates a method of forming an encapsulation layer of a first predetermined thickness. In this method, the encapsulation layer of a first predetermined thickness PH is formed using a molding hot press process. The molding hot-pressing process comprises the following steps: step S1: placing the carrier plate 3 on which the semiconductor chip 10 to be packaged is mounted in a hot-press mold (51 and 52); step S2: filling solid encapsulation particles 40 between the thermo- compression molds 51 and 52 and the semiconductor chip; step S3: heating the solid encapsulated particles 40 in step S2 to form a liquid encapsulant; step S4: after hot pressing the liquid encapsulating material, cooling to form the encapsulating layer 4 with a first preset thickness PH. In this manufacturing process, in order to prevent the liquid encapsulating material from entering the back plate of the carrier plate 3, the back surface of the carrier plate 3 needs to be closely attached to the lower plate 52 of the hot-pressing mold. The solid encapsulated particles 40 are preferably solid particles or powder resins. The reason for choosing such a resin material is that the thermal expansion coefficient of such a material is the same as or close to that of the semiconductor chip 10, and the cost is relatively low.
In the process of manufacturing the encapsulation layer with the first preset thickness PH illustrated in fig. 4, in the compression molding process, the encapsulation layer 4 with the first preset thickness PH is formed first. Since more resin particles 40 can be filled in the cavity during the molding process. After heating more of the resin particles 40, more of the molten resin flows more easily throughout the mold cavity, thereby more easily forming a uniform encapsulation layer. Thus, the pressure of the upper plate 51 of the hot press mold is more easily uniformly distributed over the entire molten resin layer, so that the solidified encapsulating layer is more uniform.
In the molten state of the resin material, air bubbles rise and accumulate in the upper portion of the encapsulation layer 4 due to buoyancy. Therefore, a large number of air bubbles are collected at the upper portion of the encapsulation layer 4 near the surface, and a large number of voids are formed after the resin is cured. While the bottom of the encapsulation layer 4, i.e. the position close to the semiconductor chip 10, has a small number of air bubbles or is substantially free of air bubbles, and after curing of the resin, the voids in the encapsulation layer are small. Since the encapsulation layer of the first preset thickness PH is made thicker, a space is provided for the air bubbles to float up, and all the air bubbles are not completely discharged by completely using the pressure of the upper plate 51 of the hot pressing mold, but the bubbles are gathered at the upper position of the encapsulation layer away from the semiconductor chip by using the buoyancy of the bubbles in the molten resin. Thus, the pressure requirement in the molding hot-pressing process is reduced, and the energy consumption of equipment is reduced. In order to better adhere the encapsulation layer 4 with the first preset thickness PH to the carrier plate 3, the thermal expansion coefficients of the encapsulation layer and the carrier plate are the same or similar. For example, the thermal expansion coefficient of the encapsulation layer is 4, and the thermal expansion coefficient of the carrier plate is 3 to 5.
According to the description of the above embodiment, the material of the encapsulating layer is a cured resin material, and correspondingly, the encapsulating layer with the second pre-thickness removed is removed by a grinding process. However, the removal is not necessarily performed by a grinding process, and the upper portion of the encapsulating layer may be removed by a suitable chemical reaction according to the material of the encapsulating layer, or may be removed by other methods, which is not limited to the grinding process described herein.
Referring to fig. 5, fig. 5 illustrates the formation of an encapsulation layer of a target thickness TH using a polishing process. The carrier plate on which the encapsulation layer of the first preset thickness is fabricated is placed on a carrier table 62 of a polishing apparatus, and the encapsulation layer 4 is polished by a polishing head 63. Fig. 5 is illustrative only and does not represent an encapsulation layer in which the polishing head 63 is polished once over the entire surface to achieve the target thickness TH. To facilitate easier gripping and easier fixing of the carrier plate by the grinding apparatus, such as the grinding carriage 62, or the robot of the grinding apparatus (shown and described in fig. 5), a portion of the material of the carrier plate may be correspondingly selected to be magnetic, or the carrier plate may be entirely magnetic.
As can be seen from the above-described embodiments, it is not preferable to make the encapsulation layer too thick when forming the encapsulation layer of the first predetermined thickness, which is time-consuming when removing the encapsulation layer of the second predetermined thickness by a subsequent grinding process, and also easily causes waste of material. Therefore, it is necessary to determine the thickness of the encapsulation layer according to the grinding accuracy of the grinder, the speed, and the defect localization of the encapsulation layer formed by the molding hot press process. The first predetermined thickness of the encapsulation layer should be greater than 0.3mm, depending on the current encapsulation process and process equipment. In combination with the current distribution of void defects of the encapsulation layer and the precision of the grinder station, the first preset thickness of the encapsulation layer is preferably 0.35mm.
In order to prevent the circuit surface of the semiconductor chip from being polluted and damaged in the subsequent packaging process, a protective layer is attached to the circuit surface of the semiconductor chip, and an opening is arranged at a position, corresponding to a welding pad in the circuit surface of the semiconductor chip, of the protective layer so as to realize rewiring of the semiconductor chip or electric connection with other conductive units through the opening in the subsequent packaging process.
In a subsequent packaging process, the carrier plate may be removed, typically after forming an encapsulation layer of a target thickness. This is done so as to expose the circuit face of the semiconductor chip. And forming a first layer of rewiring structure on the protective layer of the semiconductor chip, wherein the first layer of rewiring structure is used for electrically connecting with a welding pad of the circuit surface of the semiconductor chip and/or forming an electrical connection point of the semiconductor chip on the first layer of rewiring structure. If the first layer rewiring structure cannot finish the external lead wiring of the semiconductor chip, a second protection layer can be paved and opened on the first layer rewiring structure, and then the second layer rewiring structure is formed on the second layer protection layer, so that the subsequent packaging flow of the semiconductor chip is finished.
If the semiconductor module further comprises a conductive unit, a first layer of rewiring structure is formed on the protective layer, and the bonding pad for electrically connecting the circuit surface of the semiconductor chip and the electrical connection point of the semiconductor chip on the first layer of rewiring structure are formed to simultaneously realize the electrical connection between the semiconductor chip and the conductive unit and/or form the electrical connection point of the conductive unit on the first layer of rewiring structure. If the first layer rewiring structure cannot complete the external lead wiring of the semiconductor module or the internal electrical property of the semiconductor module, a second protection layer can be paved and opened on the first layer rewiring structure, and then the second layer rewiring structure is formed on the second layer protection layer, so that the subsequent packaging flow of the semiconductor module is completed.
Another aspect of the present application proposes two structures in a semiconductor module packaging process: a first structure and a second structure. The first structure corresponds to a structure of the semiconductor module on the carrier when the encapsulation layer with the first preset thickness is formed. In one embodiment, the semiconductor module is illustrated as including only semiconductor chips. Referring to fig. 6 (a), the semiconductor module is only a semiconductor chip 10. The first structure as shown in fig. 6 (a) includes: an envelope layer 4 of a first predetermined thickness PH provided with an inner cavity 42; at least one semiconductor module having an active surface and an inactive surface; the semiconductor module is arranged in the inner concave cavity 42, and the ineffective surface of the semiconductor module faces the inner concave cavity 42; the carrier plate 3, the semiconductor module is set up in the preset position of the carrier plate 3, the effective surface of the semiconductor module faces the carrier plate 3. The second structure as illustrated in fig. 6 (b) includes: an envelope layer 4 of a target thickness TH, provided with an inner cavity 42; at least one semiconductor module having an active surface and an inactive surface; the semiconductor module is disposed in the inner cavity 42, and the inactive surface of the semiconductor module faces the inner cavity; the carrier plate 3, the semiconductor module is set up in the preset position of the carrier plate 3, the effective surface of the semiconductor module faces the carrier plate. As shown in fig. 6 (a) and 6 (b), in both structures, the thickness of the encapsulation layer 4 of the target thickness TH in the second structure is thinner than the thickness of the encapsulation layer 4 of the first preset thickness PH in the first structure.
In other embodiments of both structures, the first predetermined thickness of the encapsulation layer in the first structure may be selected to be greater than 0.3mm and the target thickness to be less than or equal to 0.3mm in combination with specific process parameters of the semiconductor module package. The first predetermined thickness of the encapsulation layer in the first configuration is about 0.35mm. Thus, the burden of removing the second preset thickness encapsulating layer is not increased under the condition that the target thickness of the encapsulating layer meets the requirement. In some other embodiments, illustrated in fig. 6 (a) and 6 (b), the surface 43 of the encapsulation layer 4 away from the active surface of the semiconductor module of the first predetermined thickness PH shown in fig. 6 (a) is at least 0.05mm higher than the surface 43 of the encapsulation layer 4 away from the active surface of the semiconductor module of the target thickness TH shown in fig. 6 (b).
In both of the structural schematic diagrams shown in fig. 6 (a) and 6 (b), both structures further include an adhesive layer 30. The adhesion layer 30 is located between the carrier plate 3 and the front side of the semiconductor chip 10. The adhesive layer is formed on the surface of the carrier plate 3 on which the semiconductor chip 10 is to be mounted. The adhesive layer is also mentioned in the above embodiments and will not be described again here. As can be seen from fig. 6, the front side of the semiconductor chip 10 is also provided with a protective layer 2 to protect the front side of the semiconductor chip 10 from contamination and damage during the manufacture of the encapsulation layer 4.
In other embodiments of both structures, the structures further comprise a sealing layer. Please refer to the embodiment shown in fig. 7 (a) and 7 (b). In the schematic view of the first structure shown in fig. 7 (a), the sealing layer 5 is located between the adhesive layer 30 and the first preset thickness PH encapsulating layer 4. In this embodiment, the sealing layer 5 also surrounds the back surface of the semiconductor chip 10. A schematic view of the second structure shown in fig. 7 (b), the sealing layer 5 is located between the adhesive layer 30 and the TH encapsulation layer 4 of target thickness. In this embodiment, the sealing layer 5 also wraps around the back surface of the semiconductor chip 10.
In other embodiments of both structures, the structures may include a sealing layer, but the sealing layer is only between the adhesion layer and the encapsulation layer, and the back side of the semiconductor chip is free of the sealing layer. The distribution of such sealants is not shown here. The purpose of the sealant is to prevent the relative displacement between the semiconductor chips 10 on the carrier 3 from occurring during the manufacture of the encapsulating layer 4, which would affect the alignment steps involved in the subsequent process of the semiconductor chips.
In the above embodiments, only the semiconductor module including only the semiconductor chip 10 is explained and explained. But as previously described the semiconductor module may obviously comprise other conductive elements. In this way, the conductive unit and the semiconductor chip can be integrally packaged in the whole packaging process, and compared with the method that the semiconductor chip and the conductive unit are packaged respectively and then are connected in panel level, or the semiconductor chip is packaged and then is connected with the conductive unit in panel level, the whole packaging of the semiconductor module can improve the packaging integration level and simultaneously reduce the size of the packaged semiconductor product and the packaging cost.
In connection with the above description, it is not possible to exemplify the structure during all encapsulation in the process of forming the encapsulation layer one by one to support the protection scope of both structures as claimed in the appended claims. As described in the above examples, the above two structures are mainly described with respect to the encapsulation layer and the layers associated with the encapsulation layer structure.
In other embodiments of the two structures, at least a part of the area of the carrier 3 is made of magnetic material in order to facilitate the grinding machine to hold the structure in the packaging process of the semiconductor module to grind the encapsulation layer with the first preset thickness. Further, the whole carrier plate 3 is made of metal magnetic materials so as to facilitate the manufacture and material selection of the carrier plate. In order to make the manufactured encapsulation layer well attached to the carrier plate 3, the carrier plate 3 is not easy to peel off naturally, and the thermal expansion coefficient of the carrier plate 3 is the same as or similar to that of the encapsulation layer.
The above-proposed structure of the two semiconductor package module packaging processes is only explained and illustrated with respect to a structure that may exist when the second preset thickness package layer is removed by using a grinding process. When the encapsulating layer adopts other chemical processes to remove the encapsulating layer with the second preset thickness to form the encapsulating layer with the target thickness, equipment is different along with the process change, and the requirements on the material of the carrier plate are different. The material requirements of the carrier may be different according to the process of removing the second preset thickness encapsulation layer.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (26)
1. A method of packaging a semiconductor module, comprising:
providing at least one semiconductor module to be packaged, wherein the semiconductor module is provided with an effective surface and an ineffective surface;
providing a carrier plate, and attaching the semiconductor module on the carrier plate with an effective surface facing the carrier plate;
forming an encapsulation layer with a first preset thickness on the invalid surface of the semiconductor module and the exposed surface of the carrier plate;
removing the second preset thickness of the encapsulation layer to form an encapsulation layer with a target thickness;
the encapsulation layer of the first preset thickness is formed using a molding hot press process configured to cause air bubbles to accumulate at an upper portion of the encapsulation layer.
2. The packaging method of a semiconductor module according to claim 1, wherein: the molding hot-pressing process comprises the following steps:
step S1: placing the carrier plate on which the semiconductor module to be packaged is attached in a hot-pressing die;
step S2: filling solid encapsulation particles between the hot-pressing mold and the semiconductor module to be encapsulated;
step S3: heating the solid encapsulated particles in step S2 to form a liquid encapsulant;
step S4: and hot-pressing the liquid encapsulating material, and cooling to form the encapsulating layer with the first preset thickness.
3. The packaging method of a semiconductor module according to claim 2, wherein: the carrier plate is clung to the hot-pressing die relative to the other surface on which the semiconductor module is clung.
4. The packaging method of a semiconductor module according to claim 2, wherein: the solid encapsulated particles are solid particles or powder resins.
5. The packaging method of a semiconductor module according to any one of claims 1 to 4, characterized in that: and removing the encapsulation layer with the second preset thickness by adopting a grinding process.
6. The packaging method of a semiconductor module according to claim 5, wherein: the carrier plate comprises a carrier plate layer and an adhesion layer.
7. The packaging method of a semiconductor module according to claim 6, wherein: the carrier plate layer is made of metal magnetic materials.
8. The packaging method of a semiconductor module according to claim 6, wherein: the carrier layer has a coefficient of thermal expansion similar to or the same as the coefficient of thermal expansion of the encapsulation layer.
9. The packaging method of a semiconductor module according to claim 1, wherein: the semiconductor module comprises at least one semiconductor chip, and a circuit surface of the semiconductor chip corresponds to an effective surface of the semiconductor module.
10. The packaging method of a semiconductor module according to claim 9, wherein: the circuit surface of the semiconductor chip is provided with a protective layer, and the position of the protective layer corresponding to the welding pad in the circuit surface of the semiconductor chip is provided with an opening.
11. The packaging method of a semiconductor module according to claim 10, wherein: the semiconductor module further includes a conductive unit.
12. The packaging method of a semiconductor module according to claim 11, wherein: and after forming the encapsulation layer with the target thickness, removing the carrier plate.
13. The method of packaging a semiconductor module according to claim 12, wherein: forming a first layer of rewiring structure on the protective layer, wherein the first layer of rewiring structure is used for electrically connecting a welding pad of a circuit surface of the semiconductor chip and/or forming an electrical connection point of the semiconductor chip on the first layer of rewiring structure; or forming a first layer of rewiring structure on the protection layer, wherein the first layer of rewiring structure is used for electrically connecting a welding pad of a circuit surface of the semiconductor chip and forming an electrical connection point of the semiconductor chip on the first layer of rewiring structure, and simultaneously realizing the electrical connection between the semiconductor chip and the conductive unit and/or forming an electrical connection point of the conductive unit on the first layer of rewiring structure.
14. The packaging method of a semiconductor module according to claim 1, wherein: the first predetermined thickness of the encapsulation layer is greater than 0.3mm.
15. The method of packaging a semiconductor module of claim 14, wherein: the first predetermined thickness of the encapsulation layer is 0.35mm.
16. Two structures in the packaging process of a semiconductor module are characterized in that,
the first structure includes:
an encapsulation layer of a first preset thickness configured to be formed using a molding hot press process configured to cause air bubbles to accumulate at an upper portion of the encapsulation layer; the encapsulation layer is provided with an inner concave cavity;
at least one semiconductor module having an active face and an inactive face; the semiconductor module is arranged in the inner concave cavity body, and the ineffective surface of the semiconductor module faces the inner concave cavity body;
the semiconductor module is arranged at a preset position of the carrier, and the effective surface of the semiconductor module faces to the carrier;
the second structure includes:
an encapsulation layer of a target thickness, the encapsulation layer being provided with an inner cavity;
at least one semiconductor module having an active face and an inactive face; the semiconductor module is arranged in the inner concave cavity body, and the ineffective surface of the semiconductor module faces the inner concave cavity body;
the semiconductor module is arranged at a preset position of the carrier, and the effective surface of the semiconductor module faces to the carrier;
the thickness of the encapsulating layer with the target thickness in the second structure is thinner than that of the encapsulating layer with the first preset thickness in the first structure.
17. The two structures in the semiconductor module packaging process of claim 16, wherein the first predetermined thickness of the encapsulation layer is greater than 0.3mm and the target thickness of the encapsulation layer is less than or equal to 0.3mm.
18. The two structures in the semiconductor module packaging process of claim 16, wherein the surface of the encapsulation layer of the first predetermined thickness remote from the active surface of the semiconductor module is at least 0.05mm higher than the surface of the encapsulation layer of the target thickness remote from the active surface of the semiconductor module.
19. The two structures in the packaging process of a semiconductor module according to any one of claims 16 to 18, wherein at least a part of the carrier is made of a magnetic material.
20. The semiconductor module packaging process of claim 19, wherein the carrier is entirely metal magnetic.
21. The two structures in the packaging process of a semiconductor module of claim 19, wherein the semiconductor module comprises at least one semiconductor chip.
22. The semiconductor module packaging process of claim 19, further comprising an adhesion layer between the carrier and the active semiconductor module surface.
23. The semiconductor module packaging process of claim 20, further comprising an adhesion layer between the carrier and the active semiconductor module surface.
24. The semiconductor module packaging process of claim 21, further comprising an adhesion layer between the carrier and the active semiconductor module surface.
25. The two structures in the packaging process of a semiconductor module according to claim 22, wherein the carrier has a coefficient of expansion that is the same as or similar to the coefficient of expansion of the encapsulation layer.
26. The semiconductor module packaging process of claim 22, further comprising a sealant layer between the adhesive layer and the encapsulation layer.
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| CN103525322A (en) * | 2012-07-05 | 2014-01-22 | 日东电工株式会社 | Sealing resin sheet, method for producing electronic component package and electronic component package |
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