CN111667767A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN111667767A CN111667767A CN202010604405.1A CN202010604405A CN111667767A CN 111667767 A CN111667767 A CN 111667767A CN 202010604405 A CN202010604405 A CN 202010604405A CN 111667767 A CN111667767 A CN 111667767A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Abstract
The application provides an array substrate and a display panel, in the array substrate, a first conducting layer is arranged on a substrate and comprises a plurality of scanning lines and a plurality of redundant signal lines, the redundant signal lines and the scanning lines are arranged in an insulating mode and located on two sides of the scanning lines, and the redundant signal lines are at least arranged in redundant pixel areas; the second conducting layer comprises a plurality of signal lines, the signal lines and the scanning lines are arranged in a crossed mode, and the signal lines are connected to corresponding redundant signal lines through first through holes. This application sets up redundant signal line in redundant pixel district to with the connection in signal line that redundant signal line corresponds, reached the voltage between balanced scanning line and the signal line, avoid static to explode and hinder.
Description
Technical Field
The present disclosure relates to display technologies, and particularly to an array substrate and a display panel.
Background
In the redundant pixel area of the display panel, the pixel electrode layer is electrically connected to the corresponding data line, and in the display pixel, the pixel electrode layer is electrically connected to the corresponding data line. Because the metal tail end is easy to accumulate static electricity, and after a large amount of static electricity is accumulated for a long time, the tail end of the scanning line and the data line of the redundant pixel area form a voltage difference, and then the abnormal phenomenon of static electricity explosion injury occurs.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, and aims to solve the technical problem that a redundant pixel area of an existing display panel is easy to generate electrostatic blasting due to the fact that a large amount of static charges are accumulated at the tail end of a scanning line.
The embodiment of the application provides an array substrate, it includes display pixel district and sets up the redundant pixel district of display pixel district week side, array substrate includes:
a substrate base plate;
the first conducting layer is arranged on the substrate and comprises a plurality of scanning lines and a plurality of redundant signal lines, and the redundant signal lines are insulated from the scanning lines and positioned on one side or two sides of the scanning lines;
a first insulating layer disposed on the first conductive layer, the first insulating layer having a first via hole disposed thereon corresponding to the redundant signal line disposed at least in the redundant pixel region; and
the second conducting layer is arranged on the first insulating layer and comprises a plurality of signal lines, the signal lines and the scanning lines are arranged in a crossed mode, and the signal lines are connected to the corresponding redundant signal lines through the first through holes.
In the array substrate according to the embodiment of the present application, the redundant signal line is further disposed in the display pixel region.
In the array substrate according to the embodiment of the application, the plurality of redundant signal lines are arranged in an array, each row of the redundant signal lines and the scanning lines are alternately arranged, and the extension directions of the redundant signal lines in each row are consistent or parallel.
In the array substrate according to the embodiment of the present application, the extension directions of the redundant signal lines in each row are the same; the orthographic projection of each row of the redundant signal lines on the plane of the substrate base plate is positioned in the orthographic projection of the signal lines electrically connected with the redundant signal lines on the plane of the substrate base plate.
In the array substrate according to the embodiment of the present application, the signal lines include data lines and/or power lines.
In the array substrate according to the embodiment of the present application, the array substrate further includes an active layer and a second insulating layer disposed on the substrate, and a planarization layer, a pixel electrode layer and a passivation layer sequentially disposed on the second conductive layer; the first conducting layer is arranged on the second insulating layer, and the second conducting layer further comprises a drain electrode and a source electrode correspondingly connected to the data line; the pixel electrode layer comprises a pixel electrode;
in the display pixel region, a second through hole corresponding to the drain electrode is formed in the flat layer, and the pixel electrode is connected to the drain electrode through the second through hole.
In the array substrate according to the embodiment of the present application, the pixel electrode layer includes a connection trace located in the redundant pixel region;
in the redundant pixel area, a third via hole is formed in the flat layer, the data line is exposed out of the third via hole, and the connecting routing line is connected to the corresponding data line through the third via hole.
In the array substrate according to the embodiment of the present application, the first conductive layer and the second conductive layer are both a single-layer structure or a multi-layer stacked structure.
In the array substrate according to the embodiment of the present application, the second conductive layer is one of Mo/Al/Mo, Mo/Cu, and Mo/Ti/Cu.
The embodiment of the application also relates to a display panel, wherein the display panel comprises the array substrate.
The array substrate and the display panel are provided with the redundant signal lines in the redundant pixel area and are connected to the signal lines correspondingly, voltage between the balance scanning lines and the signal lines is achieved, and static electricity explosion is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments are briefly described below. The drawings in the following description are only some embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1 and 2, fig. 1 is a schematic top view structure diagram of an array substrate according to an embodiment of the present disclosure; fig. 2 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present application.
In the present embodiment, the bottom gate thin film transistor array substrate is taken as an example, but the present invention is not limited to this, and the array substrate 100 of the present application may be a top gate thin film transistor array substrate, for example.
The embodiment provides an array substrate 100, which includes a display pixel area AA and a redundant (dummy) pixel area DU disposed on the periphery of the display pixel area AA. The array substrate 100 includes a substrate 11, an active layer 12, a second insulating layer 13, a first conductive layer 14, a first insulating layer 15, a second conductive layer 16, a planarization layer 17, a pixel electrode layer 18, and a passivation layer 19, which are sequentially disposed.
The first conductive layer 14 is provided on the substrate base plate 11. The first conductive layer 14 includes a plurality of scan lines 141 and a plurality of redundant signal lines 142, and the redundant signal lines 142 are insulated from the scan lines 141 and located on one side or two sides of the scan lines 141. The redundant signal line 142 is disposed at least in the redundant pixel area DU.
In the embodiment, the redundant signal lines 142 are disposed on two sides of the scan lines 141.
The first insulating layer 15 is disposed on the first conductive layer 14. The first insulating layer 15 is provided with a first via 151 corresponding to the redundant signal line 142.
The second conductive layer 16 is disposed on the first insulating layer 15. The second conductive layer 16 includes a plurality of signal lines 161, and the signal lines 161 are arranged to cross the scan lines 141. The signal line 161 is connected to the corresponding redundant signal line 142 through the first via 151.
The array substrate 100 of the present application sets the redundant signal line 142 in the redundant pixel area DU, and connects the redundant signal line 142 to the signal line 161 correspondingly, so as to balance the voltage between the scan line 141 and the signal line 161 and avoid electrostatic explosion. Specifically, the signal line 161 is connected to the redundant signal line 142 so that the signal line and the redundant signal line form the same signal line, thereby reducing the impedance of the signal line 161, reducing the voltage difference between the signal line 161 and the scanning line 141 during operation, and further achieving the effect of balancing the voltage between the signal line and the scanning line.
In the array substrate 100 of the present embodiment, the redundant signal line 142 is further disposed in the display pixel area AA. The redundant signal lines 142 are also arranged in the display pixel area AA, and the signal lines 161 in the display pixel area AA are also connected to the corresponding redundant signal lines 142, so that the signal lines 161 in the whole pixel area are consistent in area, and the condition of signal asynchronization in the signal transmission process is avoided.
In the array substrate 100 of the present embodiment, the plurality of redundant signal lines 142 are arranged in an array. The redundant signal lines 142 are alternately arranged with the scan lines 141 in each row. The extension directions of all the redundant signal lines 142 in each column of the redundant signal lines 142 are the same or parallel.
Specifically, the extension directions of all the redundant signal lines 142 in each column of the redundant signal lines 142 are the same. The orthographic projection of each row of the redundant signal lines 142 on the plane of the substrate 11 is positioned in the orthographic projection of the signal lines 161 electrically connected with each row on the plane of the substrate 11.
In the array substrate 100 of the present embodiment, the signal line 161 includes a data line and/or a power line. The signal lines 161 are data lines in this embodiment.
In the array substrate 100 of the present embodiment, the second conductive layer 16 further includes a drain 162, a source (not shown) correspondingly connected to the data line 161, and a touch trace 163. The pixel electrode layer 18 includes a pixel electrode 181.
In the display pixel area AA, a second via 171 corresponding to the drain 162 is formed on the planarization layer 17. The pixel electrode 181 is connected to the drain electrode 162 through the second via 171.
In the redundant pixel area DU, the pixel electrode 181 is disposed corresponding to the drain electrode 162, and the pixel electrode 181 is disposed insulated from the corresponding drain electrode 162.
In some embodiments, the pixel electrode layer 18 includes a connection trace 182 located in the redundant pixel region DU. In the redundant pixel area DU, a third via 172 is disposed on the planarization layer 17. The third via 172 exposes the data line 161. The connecting trace 182 is connected to the corresponding data line 161 through the third via 172. The data line 161 is connected to the connection trace 182 to further reduce the impedance of the signal line 161, so that the voltage difference between the signal line 161 and the scan line 141 is reduced when the signal line 161 works, and the voltage between the two is balanced.
The first conductive layer 14 and the second conductive layer 16 are each a single-layer structure or a multi-layer stacked structure. The second conductive layer 16 may be one of Mo (molybdenum)/Al (aluminum)/Mo (molybdenum), Mo (molybdenum)/Cu (copper), Mo (molybdenum)/Ti (titanium)/Cu (copper); it may be one of Cu (copper), Ti (titanium), Al (aluminum), Ag (silver), and ITO (indium tin oxide).
In some embodiments, the signal lines 161 in the redundant pixel regions DU include a plurality of signal line segments, which are arranged in a column direction and extend in the same direction, and the signal line segments and the scan lines are alternately disposed. The pixel electrode layer 18 includes a bridge, and two adjacent signal line segments in the same column are electrically connected through the bridge.
The part of the signal line 161 overlapping the scanning line 141 is replaced by the gap bridge, so that the distance between the overlapping part of the signal line 161 and the scanning line 141 is increased, and the risk of electrostatic explosion is reduced.
The embodiment of the present application also relates to a display panel, wherein the display panel includes the array substrate 100 of the above embodiment.
The array substrate and the display panel are provided with the redundant signal lines in the redundant pixel area and are connected to the signal lines correspondingly, voltage between the balance scanning lines and the signal lines is achieved, and static electricity explosion is avoided.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate comprising a display pixel region and a redundant pixel region disposed on a peripheral side of the display pixel region, the array substrate comprising:
a substrate base plate;
the first conducting layer is arranged on the substrate and comprises a plurality of scanning lines and a plurality of redundant signal lines, the redundant signal lines are insulated from the scanning lines and positioned on one side or two sides of the scanning lines, and the redundant signal lines are at least arranged in the redundant pixel area;
a first insulating layer disposed on the first conductive layer, the first insulating layer having a first via hole disposed thereon corresponding to the redundant signal line; and
the second conducting layer is arranged on the first insulating layer and comprises a plurality of signal lines, the signal lines and the scanning lines are arranged in a crossed mode, and the signal lines are connected to the corresponding redundant signal lines through the first through holes.
2. The array substrate of claim 1, wherein the redundant signal line is further disposed in the display pixel region.
3. The array substrate of claim 1 or 2, wherein the plurality of redundant signal lines are arranged in an array, each row of the redundant signal lines and the scan lines are alternately arranged, and the extension directions of the redundant signal lines in each column are consistent or parallel.
4. The array substrate of claim 3, wherein the redundant signal lines in each column extend in the same direction; the orthographic projection of each row of the redundant signal lines on the plane of the substrate base plate is positioned in the orthographic projection of the signal lines electrically connected with the redundant signal lines on the plane of the substrate base plate.
5. The array substrate of claim 1, wherein the signal lines comprise data lines and/or power lines.
6. The array substrate of claim 5, further comprising an active layer and a second insulating layer disposed on the substrate, and a planarization layer, a pixel electrode layer and a passivation layer sequentially disposed on the second conductive layer; the first conducting layer is arranged on the second insulating layer, and the second conducting layer further comprises a drain electrode and a source electrode correspondingly connected to the data line; the pixel electrode layer comprises a pixel electrode;
in the display pixel region, a second through hole corresponding to the drain electrode is formed in the flat layer, and the pixel electrode is connected to the drain electrode through the second through hole.
7. The array substrate of claim 6, wherein the pixel electrode layer comprises a connection trace in the redundant pixel region;
in the redundant pixel area, a third via hole is formed in the flat layer, the data line is exposed out of the third via hole, and the connecting routing line is connected to the corresponding data line through the third via hole.
8. The array substrate of claim 1, wherein the first conductive layer and the second conductive layer are each a single layer structure or a multi-layer stacked structure.
9. The array substrate of claim 8, wherein the second conductive layer is one of Mo/Al/Mo, Mo/Cu, Mo/Ti/Cu.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010604405.1A CN111667767B (en) | 2020-06-29 | 2020-06-29 | Array substrate and display panel |
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| CN202010604405.1A CN111667767B (en) | 2020-06-29 | 2020-06-29 | Array substrate and display panel |
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| CN111667767B CN111667767B (en) | 2022-04-08 |
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