CN111666732A - Integrated circuit layout design method - Google Patents
Integrated circuit layout design method Download PDFInfo
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- CN111666732A CN111666732A CN201910170236.2A CN201910170236A CN111666732A CN 111666732 A CN111666732 A CN 111666732A CN 201910170236 A CN201910170236 A CN 201910170236A CN 111666732 A CN111666732 A CN 111666732A
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Abstract
The invention discloses an integrated circuit layout design method, which can reduce the circuit area and power consumption of the result of an integrated circuit layout design process. The integrated circuit layout design process includes a front stage process and a back stage process. The integrated circuit layout design method comprises the following steps: executing the front-stage process according to the initial clock delay setting to generate an initial netlist; executing at least a portion of the back-end flow according to the initial netlist to obtain an updated clock delay setting; executing at least a portion of the previous flow according to the update clock delay setting to generate an updated netlist; and executing the back-end flow according to the updated netlist to obtain a result of the integrated circuit layout design flow.
Description
Technical Field
The invention relates to a circuit layout design method, in particular to an integrated circuit layout design method.
Background
A typical ic layout design process includes a logic synthesis (synthesis) process and an automatic layout and routing (APR) process. The logic synthesis process generates a netlist (netlist) of logic gates according to Hardware Description Language (HDL) codes of an ic design, and then the automatic layout and routing process generates a physical design of the circuit according to the netlist. However, the current logic synthesis flow does not consider a clock tree from a clock root (clock root) to a clock pin of a sequential cell (sequential cell), i.e., the clock delay (clock latency) from the clock root to the clock pin of the sequential cell is considered to be zero (e.g., when the sequential cell is a flip-flop) or may be an inaccurate default value (e.g., when the sequential cell is an Integrated Clock Gating (ICG) cell or a Static Random Access Memory (SRAM) circuit); therefore, in order to meet the timing requirements of circuit operation, the timing process of the logic synthesis flow may be over-constrained, such that the circuit area and power consumption of the physical design generated by the automatic layout routing flow from the netlist may exceed the requirements. Under the trend of process scaling, circuit area and power consumption are indispensable items in the field, and thus, the current ic layout design process still has room for improvement.
Disclosure of Invention
It is an objective of the claimed invention to provide an integrated circuit layout design method to improve the prior art.
One objective of the present invention is to provide an integrated circuit layout design method to improve the result of an integrated circuit layout design process.
An embodiment of the integrated circuit layout design method of the present invention can improve the circuit area and power consumption of the result of an integrated circuit layout design process, the integrated circuit layout design process comprising a front-end process and a back-end process, the embodiment comprising the steps of: executing the front-stage process according to the initial clock delay setting to generate an initial netlist; executing at least a part of the back-end flow according to the initial netlist to obtain an updated clock delay setting; executing at least a portion of the previous flow according to the update clock delay setting to generate an updated netlist; and executing the back-end flow according to the updated netlist to obtain a result of the integrated circuit layout design flow.
The features, practical operation and efficacy of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 shows an embodiment of an integrated circuit layout design method according to the present invention;
FIG. 2 shows an exemplary actual operational flow of the integrated circuit layout design method of FIG. 1; and
FIG. 3 shows another exemplary actual operational flow of the integrated circuit layout design method of FIG. 1.
Detailed Description
The terms in the following description refer to the conventional terms in the field, and some terms are defined or explained in the specification, and are to be interpreted according to the description or the definition of the specification.
The invention discloses an integrated circuit layout design method, which can improve the result of an integrated circuit layout design flow to reduce the area and production cost of an integrated circuit (such as a processor) and reduce the leakage (leakage power) of the integrated circuit. The integrated circuit layout design process includes a front stage process and a back stage process. The front-end process includes a logic synthesis (synthesis) process, which can be executed by a tool program (e.g., design compiler of Synopsys or Cadence gene); the back-end process includes an Automatic Placement and Routing (APR) process that can be performed by a tool program (e.g., ICC/ICC2 from Synopsys or Innovus from Cadence). The logic synthesis process comprises a translation (translation) stage, a mapping (mapping) stage, and an optimization (optimization) stage; the automatic layout and Routing process comprises a layout and Optimization (Placement and Optimization) stage, a Clock Tree Synthesis (CTS) stage, a Post-CTS Optimization (Post-CTS Optimization) stage, a Signal Routing (Signal Routing) stage and a Post-Routing Optimization (Post-Routing Optimization) stage in sequence; the front-end flow may include other flows earlier than the logic synthesis flow, such as simulation flows; the back-end process may include other processes, such as verification processes, that are later than the automatic place and route process. Since the front-end flow and each stage thereof and the back-end flow and each stage thereof are well known, the details thereof are omitted herein.
FIG. 1 shows an embodiment of an IC layout design method of the present invention, which can improve the circuit area and power consumption of the IC layout design process. The embodiment of fig. 1 comprises the following steps:
step S110: the previous flow is executed according to the initial clock latency setting to generate an initial netlist (netlist). In a practical example, step S110 executes the previous flow according to an initial database to generate an initial netlist (netlist), and updates the initial database to obtain a first updated database, wherein the initial database includes initial clock delay (clock latency) settings. In an actual operation example, step S110 executes the previous-stage process including the aforementioned logic synthesis process to generate the initial netlist. In an actual operation example of step S110, according to the initial clock delay setting, a clock delay between a clock root (clock root) and a clock pin (clock pin) of a sequential cell (sequential cell) is equal to a first value; for example, the first value is zero. In an example of practical operation, the sequential cell is a flip flop (flip flop), an Integrated Clock Gating (ICG) cell, a Static Random Access Memory (SRAM) circuit, or a logic circuit including memory for storing data (for example: a counter or latch).
Step S120: at least a portion of the back-end-of-line flow is executed according to the initial netlist to obtain updated clock delay settings. In an actual operation example, step S120 performs at least a portion of the automatic placement and routing process according to the initial netlist (e.g., the placement and optimization stage, the timing tree synthesis stage, and the post-timing tree synthesis optimization stage are shown in S222-S226 of FIG. 2, or the placement and optimization stage, the timing tree synthesis stage, the post-timing tree synthesis optimization stage, the signal routing stage, and the post-routing optimization stage are shown in S322-S329 of FIG. 3) to obtain the updated clock delay setting. In an actual operation example, according to the updated clock delay setting, the clock delay between the clock root and the clock pin of the sequential unit is a second value, and the second value is different from the first value; for example, the second value is greater than the first value.
Step S130: at least a portion of the previous flow is executed according to the updated clock delay setting to generate an updated netlist. In an actual operation example, step S130 updates the first updated database according to the update clock delay setting to obtain a second updated database, and executes at least a portion of the previous flow according to the second updated database to generate the updated netlist. In an actual operation example, step S130 executes at least a portion of the logic synthesis process according to the updated clock delay setting (e.g., the optimization stage is shown as S236 in FIG. 2 or S336 in FIG. 3; or the mapping stage and the optimization stage) to generate the updated netlist.
Step S140: and executing the back-end flow according to the updated netlist to obtain the result of the integrated circuit layout design flow.
It is noted that steps S110 to S140 can be performed by a single tool program or multiple tool programs. It is noted that the database can be updated automatically by a tool program or by user input.
FIG. 2 illustrates an exemplary actual process flow of the IC layout design method of FIG. 1, wherein the stages indicated by dashed boxes (i.e., signal routing stage S228, post-routing optimization stage S229, translation stage S232, and mapping stage S234) are unexecuted processes. As shown in fig. 2, the actual operation flow includes the following procedures: the translation stage S212, mapping stage S214, and optimization stage S216 of the logic synthesis flow; a layout and optimization step S222, a timing tree synthesis step S224, and a post-timing tree synthesis optimization step S226 of the automatic layout and routing process; an optimization stage S236 of the logic synthesis flow; and a layout and optimization stage S242, a timing tree synthesis stage S244, a post-timing tree synthesis optimization stage S246, a signal routing stage S248, and a post-routing optimization stage S249 of the automatic layout routing process. In the actual operation flow of fig. 2, the updated clock delay setting is obtained after the post-synthesis optimization stage S226 of the timing tree is executed; since the actual operation flow returns to the optimization stage S236 of the previous flow after the post-sequential-tree-synthesis optimization stage S226 of the subsequent flow is executed, the actual operation flow can save the time for executing the stage (i.e., the stage indicated by the dashed box) after the post-sequential-tree-synthesis optimization stage S226.
FIG. 3 illustrates another exemplary actual process flow of the IC layout design method of FIG. 1, wherein the stages (i.e., the translate stage S332 and the map stage S334) are not executed. As shown in fig. 3, the integrated circuit layout design method of the present invention sequentially executes at least the following procedures: the translation stage S312, mapping stage S314, and optimization stage S316 of the logic synthesis flow; the layout and optimization stage of the automatic layout and routing process S322, the timing tree synthesis stage S324, the post-timing tree synthesis optimization stage S326, the signal routing stage S328, and the post-routing optimization stage S329; an optimization stage S336 of the logic synthesis flow; and a layout and optimization stage S342, a timing tree synthesis stage S344, a post-timing tree synthesis optimization stage S346, a signal routing stage S348, and a post-routing optimization stage S349 of the automatic layout routing process. In the actual operation flow of fig. 3, the updated clock delay setting is obtained after the post-routing optimization stage S329 is executed; since the actual operation flow returns to the optimization stage S336 after the optimization stage S329 is completed, the updated clock delay setting obtained by the actual operation flow is more accurate than the updated clock delay setting obtained by the actual operation flow of fig. 2, and the result of the integrated circuit layout design flow can be more effectively improved.
It should be noted that, when the implementation is possible, a person skilled in the art can selectively implement some or all of the technical features of any one of the foregoing embodiments, or selectively implement a combination of some or all of the technical features of the foregoing embodiments, thereby increasing the flexibility in implementing the invention.
In summary, the present invention can improve the circuit area and power consumption of the integrated circuit layout design process, so as to reduce the production cost of an integrated circuit and reduce the leakage (leakage power) of the integrated circuit.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ notation ] to show
S110 to S140
S212 translation stage
S214 mapping phase
S216 optimization phase
S222 layout and optimization stage
S224 sequential tree synthesis phase
S226 time series tree post-synthesis optimization stage
S228 Signal winding stage
S229 post-winding optimization stage
S232 translation stage
S234 mapping phase
S236 optimization stage of logic synthesis flow
S242 Placement and optimization stage
S244 sequential tree synthesis phase
S246 time series tree post-synthesis optimization stage
S248 signal winding stage
S249 post-winding optimization stage
S312 translation stage
S314 mapping phase
S316 optimization phase
S322 Placement and optimization stage
S324 sequential tree synthesis stage
S326 time series tree post-synthesis optimization stage
S328 Signal winding stage
S329 post-winding optimization stage
S332 translation stage
S334 mapping stage
S336 optimization stage
S342 layout and optimization stage
S344 sequential tree synthesis phase
S346 time series tree post-synthesis optimization stage
S348 Signal winding stage
Optimization stage after S349 winding
Claims (10)
1. An integrated circuit layout design method capable of improving the result of an integrated circuit layout design process, the integrated circuit layout design process comprising a front-end process and a back-end process, the integrated circuit layout design method comprising:
executing the front-stage process according to the initial clock delay setting to generate an initial netlist;
executing at least a part of the back-end flow according to the initial netlist to obtain an updated clock delay setting;
executing at least a portion of the previous flow according to the update clock delay setting to generate an updated netlist; and
and executing the back-end flow according to the updated netlist to obtain the result of the integrated circuit layout design flow.
2. The method of claim 1, wherein the front-end process comprises a logic synthesis process and the back-end process comprises an automatic layout routing process.
3. The method of claim 2, wherein at least a portion of the front-end flow is an optimization stage of the logic synthesis flow.
4. The method of claim 3, wherein the at least a portion of the front-end flow comprises only a portion of the front-end flow.
5. The method of claim 3, wherein the automatic layout routing process comprises a post-timing tree synthesis optimization stage and a post-routing optimization stage, and at least a portion of the back-end process comprises the post-timing tree synthesis optimization stage.
6. The method of claim 5, wherein the updated clock delay setting is obtained after performing the post-synthesis optimization stage of the timing tree.
7. The method of claim 5, wherein the at least a portion of the back-end flow comprises only a portion of the back-end flow.
8. The method of claim 5, wherein the at least a portion of the back-end-of-line process includes the post-routing optimization stage.
9. The method of claim 8, wherein the updated clock delay setting is obtained after performing the post-routing optimization stage.
10. The method of claim 1, wherein a clock delay between a clock root and a clock pin of a sequential cell is equal to a first value according to the initial clock delay setting; according to the updated clock delay setting, the clock delay between the clock root and the clock pin of the sequential unit is a second value, and the second value is different from the first value.
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| EP1816577A1 (en) * | 2006-02-03 | 2007-08-08 | STMicroelectronics (Research & Development) Limited | A method of making an integrated circuit including a clock tree |
| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
| US8365113B1 (en) * | 2007-01-10 | 2013-01-29 | Cadence Design Systems, Inc. | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs |
| US20150084212A1 (en) * | 2013-09-25 | 2015-03-26 | United Microelectronics Corporation | Clock skew adjusting method and structure |
| CN108416077A (en) * | 2017-02-10 | 2018-08-17 | 三星电子株式会社 | For by considering back-end process come the method and computing system of integrated design circuit |
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| EP1816577A1 (en) * | 2006-02-03 | 2007-08-08 | STMicroelectronics (Research & Development) Limited | A method of making an integrated circuit including a clock tree |
| US8365113B1 (en) * | 2007-01-10 | 2013-01-29 | Cadence Design Systems, Inc. | Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs |
| CN102169515A (en) * | 2010-02-26 | 2011-08-31 | 国际商业机器公司 | Estimation method and system of clock tree delay time in specified integrated circuit |
| US20150084212A1 (en) * | 2013-09-25 | 2015-03-26 | United Microelectronics Corporation | Clock skew adjusting method and structure |
| CN108416077A (en) * | 2017-02-10 | 2018-08-17 | 三星电子株式会社 | For by considering back-end process come the method and computing system of integrated design circuit |
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