CN111665795A - Modbus and Device Net protocol identification compatible design method - Google Patents
Modbus and Device Net protocol identification compatible design method Download PDFInfo
- Publication number
- CN111665795A CN111665795A CN202010372706.6A CN202010372706A CN111665795A CN 111665795 A CN111665795 A CN 111665795A CN 202010372706 A CN202010372706 A CN 202010372706A CN 111665795 A CN111665795 A CN 111665795A
- Authority
- CN
- China
- Prior art keywords
- modbus
- protocol
- device net
- circuit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013461 design Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000004891 communication Methods 0.000 claims abstract description 37
- 230000005540 biological transmission Effects 0.000 claims abstract description 9
- 238000005538 encapsulation Methods 0.000 claims abstract 2
- 238000012545 processing Methods 0.000 claims description 20
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 7
- 125000004122 cyclic group Chemical group 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims description 2
- 238000011161 development Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/418—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
- G05B19/4185—Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by the network communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/33—Director till display
- G05B2219/33139—Design of industrial communication system with expert system
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a design method for identifying and compatible Modbus and Device Net protocols, belonging to the field of computer communication and comprising the following steps: (1) designing an FPGA controller module to realize protocol transmission, identification and classification; (2) designing a processor module with a CPU as a core, and realizing communication between a Device Net or Modbus protocol and a master station and a slave station of an upper computer; (3) designing compatible external interface pin definition and size encapsulation to realize the compatibility requirement of Modbus protocol and Device Net protocol interface; (4) designing a CAN controller module to realize the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus; (5) and establishing a system hardware circuit and software architecture with protocol identification compatible design. The method can realize the transmission, identification and classification of Modbus and Device Net protocols through one-time development of the circuit, and is in communication control with a master station and a slave station of an upper computer. The invention has the characteristics of wide range, strong flexibility and the like, and can be widely applied to the field of intelligent manufacturing.
Description
Technical Field
The invention relates to the field of computer communication, in particular to a design method for protocol identification compatibility and a design method for Modbus and Device Net protocol identification compatibility.
Background
The field industrial bus is an important component of industrial robot control communication and is used for data exchange between a controller and peripheral equipment (such as electrode holders, vision cameras, welding machines, cutting machines, sensors and the like). Due to the fact that carrier board circuits or application modules with different interfaces need to be manufactured to meet the requirements of different interfaces and communication protocols to communicate with different peripheral devices, the product types are various, a large amount of low-level repeated labor is caused, the development cost is increased, and the working efficiency is low.
At present, many devices in domestic industrial fields are provided with RS-232, RS-485 or RS-422 serial communication hardware interfaces, and a Device Net protocol or a Modbus protocol is adopted to realize a communication function. The Modbus protocol physical interface conforms to the RS-232/422/485 specification, an RS-232C serial communication mode is adopted by a standard physical layer, and two transmission modes are adopted: modbusscii (american information exchange code) and Modbus RTU (remote terminal unit); the Device Net communication mode is a producer-consumer communication mode, is a network protocol of serial communication link, and the network can be hooked with 64 contacts at most, and the selectable communication speed is 125kbps, 250kbps and 500 kbps.
At present, along with the brisk development of the intelligent manufacturing industry, the demand for various industrial robots is in a rapid increasing trend, and the measurement and control of various industrial robots and all the component units thereof are required to be satisfied, so that the measurement and control communication ecology with high reliability and high safety is formed by the communication protocol mutual conversion module which is good in compatibility and suitable for various field industrial bus communication. Currently, a design method which meets the universality of the underlying protocols of the industrial buses and is compatible with the complex diversity of industrial robot communication is also lacked.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the defects of the prior art, the invention provides a design method for identifying and compatible with Modbus and Device Net protocols, which can effectively improve the reliability and maintainability of conversion among various protocols in industrial robot measurement and control communication and has strong universality.
The technical scheme is as follows: the invention relates to a design method for identifying and compatible Modbus and Device Net protocols, which comprises the following steps: (1) designing an FPGA controller module to realize protocol transmission, identification and classification;
(2) designing a processor module with a CPU as a core, and realizing communication between a Device Net or Modbus protocol and a master station and a slave station of an upper computer;
(3) designing compatible external interface pin definition and size package to meet the compatibility requirement of Modbus protocol and DeviceNet protocol interface;
(4) designing a CAN controller module to realize the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus;
(5) according to the steps (1) - (4), a system hardware circuit with protocol identification compatible design is built;
(6) and (5) according to the steps (1) to (5), constructing a software architecture with protocol identification and compatible design.
Further, in step (5), the system hardware circuit includes: the system comprises a communication interface logic module, an FPGA controller hardware circuit, a Modbus network module, a CAN bus transceiver, a photoelectric isolation circuit, a CAN controller circuit, an RS485 differential transceiver circuit, a CPU processor circuit and a peripheral circuit.
Further, the data processing flow of the system hardware circuit which is compatible with the design is identified according to the established protocol: the communication interface logic module is connected with the FPGA controller, and after external data is accessed, the FPGA controller identifies whether the data protocol is a Modbus protocol or a Devicenet protocol; the FPGA controller is respectively connected with the Modbus network module and the Device net module; if the FPGA controller identifies a Modbus protocol, the FPGA controller enters a Modbus network module, and then enters a CPU (central processing unit) through an RS485 differential transceiver for data processing; after the processing of the CPU processor is finished, the data is directly output through an RS485 interface; if the FPGA controller identifies a Device net protocol, the FPGA controller enters a Device net network module, receives data through the CAN bus transceiver and then carries out photoelectric isolation, receives the data through the CAN bus transceiver and then enters the CPU processor to carry out data processing, the CPU processor sends the data to the CAN bus controller after the data processing is finished, and the data is sent out from the CAN bus transceiver after the data is isolated.
Further, the processor module with the CPU as a core includes: and the CPU processor and the dual-port RAM circuit are mutually connected. The CPU model is IMX6 and compatible model thereof, and the dual-port RAM model is IDT71321 and compatible model thereof. The CPU has the characteristics of low power consumption, high speed and easy development; the adoption of the dual-port RAM ensures the processing speed of the CPU.
Further, the peripheral circuit includes: the system comprises a reset circuit, a clock circuit, a power circuit and a memory circuit, wherein the power circuit provides power supply for other hardware circuits of the system, and other peripheral circuits are connected with the CPU processor. The memory circuit adopts a chip with a model of 93CS66L and a chip with a compatible model, so that the high speed of data access is ensured.
Furthermore, the CAN controller circuit adopts an ADM3052 model controller core chip or a compatible model chip thereof. The CAN controller core chip has the characteristics of low power consumption, high speed, few peripheral devices and easy development.
Further, a software architecture with protocol identification compatible design is built, and the software architecture specifically comprises the following steps:
(61) based on the difference of the communication frame formats, the transmission of a Modbus data link layer protocol and a Device Net application layer protocol is realized through programming;
(62) protocol identification and classification are realized by adopting a software macro-definition method, CRC (cyclic redundancy check) of a Modbus data link layer and receiving and sending of Modbus messages are realized, and repeated MAC ID (media access control) detection, message sending, message receiving and processing of each specific object of a Device Net application layer are realized.
Furthermore, Verilog language programming is adopted for designing programs transmitted by a Modbus data link layer protocol and a Device Net application layer protocol, so that the robustness and reliability of the developed protocols are guaranteed, and the difficulty of program design is reduced.
Has the advantages that: the method of the invention can be compatible with various field industrial buses, provides a universal module circuit, and does not need to manufacture carrier board circuits or application modules with different interfaces to meet the communication with different peripheral equipment; the circuit can replace a series of circuit designs, and has universality, flexible applicability and expandability; development time and steps of Modbus and Device Net protocol identification compatible design are effectively shortened, and protocol identification compatible accuracy is improved.
Drawings
FIG. 1 is a schematic block diagram of the system hardware of the present invention;
FIG. 2 is a block diagram of the internal logic processing of the CAN controller of the present invention;
FIG. 3 is a diagram of a protocol identification object model of the present invention;
FIG. 4 is a flow diagram of accessing application object display information in accordance with the present invention.
Detailed Description
The technical scheme of the invention is further described in the following by combining the attached drawings and the detailed description.
The invention relates to a design method for identifying and compatible Modbus and Device Net protocols, which comprises the following steps:
(1) designing an FPGA controller module to realize protocol transmission, identification and classification;
(2) designing a processor module with a CPU as a core, and realizing communication between a Device Net or Modbus protocol and a master station and a slave station of an upper computer;
(3) designing compatible external interface pin definition and size package to meet the compatibility requirement of Modbus protocol and DeviceNet protocol interface;
(4) designing a CAN controller module to realize the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus;
(5) according to the steps (1) - (4), a system hardware circuit (shown in figure 1) with protocol identification compatible design is built, the CAN bus transceiver, the photoelectric isolation circuit, the CAN controller circuit, the RS485 differential transceiver circuit, the CPU processor circuit, the dual-port RAM circuit, the Device Net network module, the Modbus network module, the FPGA controller, the communication interface logic module, the peripheral circuit and the like, wherein the peripheral circuit comprises: reset circuit, clock circuit, power supply circuit and EEPROM memory circuit etc. its relation of connection is: the CPU processor circuit is simultaneously connected with the CAN controller circuit, the RS485 differential transceiver circuit and the double-port RAM circuit, the CAN bus transceiver is connected with the photoelectric isolation circuit, the photoelectric isolation circuit is connected with the CAN controller circuit, the RS485 differential transceiver circuit is connected with the Modbus network module, the Modbus network module and the Device Net network module are connected with the FPGA controller, the CAN bus transceiver is connected with the Device Net network module, the FPGA controller is connected with the communication interface logic module, the power supply circuit supplies power for other hardware circuits of the system, and other peripheral circuits are connected with the CPU processor. The FPGA controller hardware circuit mainly realizes transmission, identification and classification of protocols; the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus is mainly realized through the CAN controller module; the processing speed of CPU protocol conversion is improved by the double-port RAM circuit. And a peripheral interface circuit is built, and interface signals are compatible with both a Modbus protocol and a Device.
Fig. 2 is a block diagram of the internal logic processing of the CAN controller of the present invention, which includes: the internal logic processing block diagram of the CAN controller SJA100 mainly comprises: a message receiving and transmitting buffer, an interface management logic, a bit stream processor and a bit sequence logic. The CAN controller module mainly realizes the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus.
(6) According to the steps (1) to (5), a software framework with protocol identification compatible design is built:
FIG. 3 is a diagram of a protocol recognition object model of the present invention, the classification and function of each object is as follows: the Modbus object is an application object developed according to a protocol recognition function and mainly used for controlling the receiving and sending of Modbus data; the combination class object comprises two instances of an Input combination object (Input) and an Output combination object (Output); the input combined object is responsible for packaging and packaging data received from Modbus equipment and used by the I/O polling connection object and the Modbus object; and the output combination object is responsible for unpacking, processing and packaging data to be sent to the Modbus from the I/O polling connection object for the Modbus object to use.
FIG. 4 is a flow diagram of accessing application object display information in accordance with the present invention. According to the specific software functional requirements of protocol identification compatibility, Device Net based is an object oriented application layer protocol, and Modbus is only a data link layer protocol. Therefore, the software of the FPGA controller adopts a macro-definition method to complete the corresponding relation between the attribute of the specific application object in the Device Net and the address and the number of the relevant registers in the Modbus equipment so as to realize the identification of the protocol. The design of compatible identification of the Device Net and the Modbus protocol adopts a polling message triggering mode, and transmits data between the Device Net bus and the Modbus bus by using an I/O polling message. The protocol identification compatible design is adopted, and after I/O polling connection is established with the master station, a polling request of the master station is received, and required operation is executed; meanwhile, according to the polling request, polling response data is sent to the master station; when the protocol converter receives a display request message for reading or setting the attribute of the application object, calling a related subprogram to search a Modbus register address and a register number corresponding to the attribute, then confirming whether the Modbus protocol is the Modbus protocol according to the received service code and the searched register address and register number, and if the Modbus protocol is the Modbus protocol, entering a Modbus network path. If not, the communication enters the Device Net network path. And when the error response is received, calling an error program to process the message.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments and various changes can be made within the knowledge of those skilled in the art. For example, in the above embodiments, the FPGA design may be changed to other logic component designs; for another example, when the external interface meets the interface compatible with the Modbus protocol and the Device Net protocol, a specific package or a custom pin is added.
Claims (7)
1. A design method for Modbus and Device Net protocol identification compatibility is characterized by comprising the following steps:
(1) designing an FPGA controller module to realize protocol transmission, identification and classification;
(2) designing a processor module with a CPU as a core, and realizing communication between a Device Net or Modbus protocol and a master station and a slave station of an upper computer;
(3) designing compatible external interface pin definition and size encapsulation to meet the compatibility requirement of a Modbus protocol and a Device Net protocol interface;
(4) designing a CAN controller module to realize the configuration of the communication rate, the flow control mode, the data bit, the stop bit and the check bit of the UART bus;
(5) according to the steps (1) - (4), a system hardware circuit with protocol identification compatible design is built;
(6) and (5) according to the steps (1) to (5), constructing a software architecture with protocol identification and compatible design.
2. The Modbus and Device Net protocol identification compatible design method of claim 1, wherein in step (5), the system hardware circuitry comprises: the system comprises a communication interface logic module, an FPGA controller hardware circuit, a Modbus network module, a CAN bus transceiver, a photoelectric isolation circuit, a CAN controller circuit, an RS485 differential transceiver circuit, a CPU processor circuit and a peripheral circuit.
3. The Modbus and Device Net protocol identification compatible design method according to claim 1 or 2, wherein in the step (5), the data processing flow of the system hardware circuit is as follows: the communication interface logic module is connected with the FPGA controller, and after external data is accessed, the FPGA controller identifies whether the data protocol is a Modbus protocol or a Devicenet protocol; the FPGA controller is respectively connected with the Modbus network module and the Device net module; if the FPGA controller identifies a Modbus protocol, the FPGA controller enters a Modbus network module, and then enters a CPU (central processing unit) through an RS485 differential transceiver for data processing; after the processing of the CPU processor is finished, the data is directly output through an RS485 interface; if the FPGA controller identifies a Device net protocol, the FPGA controller enters a Device net network module, receives data through the CAN bus transceiver and then carries out photoelectric isolation, receives the data through the CAN bus transceiver and then enters the CPU processor to carry out data processing, the CPU processor sends the data to the CAN bus controller after the data processing is finished, and the data is sent out from the CAN bus transceiver after the data is isolated.
4. The Modbus and Device Net protocol identification compatible design method of claim 1, wherein the CPU-centric processor module comprises: and the CPU processor and the dual-port RAM circuit are mutually connected.
5. The Modbus and Device Net protocol identification compatible design method of claim 2, wherein the peripheral circuitry includes: the system comprises a reset circuit, a clock circuit, a power circuit and a memory circuit, wherein the power circuit provides power supply for other hardware circuits of the system, and other peripheral circuits are connected with the CPU processor.
6. The Modbus and Device Net protocol identification compatible design method according to claim 1, wherein the software architecture of the established protocol identification compatible design specifically comprises:
(61) based on the difference of the communication frame formats, the transmission of a Modbus data link layer protocol and a Device Net application layer protocol is realized through programming;
(62) protocol identification and classification are realized by adopting a software macro-definition method, CRC (cyclic redundancy check) of a Modbus data link layer and receiving and sending of Modbus messages are realized, and repeated MAC ID (media access control) detection, message sending, message receiving and processing of each specific object of a Device Net application layer are realized.
7. The Modbus and Device Net protocol identification compatible design method of claim 6, wherein: the step (61) adopts Verilog language programming.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010372706.6A CN111665795A (en) | 2020-05-06 | 2020-05-06 | Modbus and Device Net protocol identification compatible design method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010372706.6A CN111665795A (en) | 2020-05-06 | 2020-05-06 | Modbus and Device Net protocol identification compatible design method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN111665795A true CN111665795A (en) | 2020-09-15 |
Family
ID=72383272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010372706.6A Pending CN111665795A (en) | 2020-05-06 | 2020-05-06 | Modbus and Device Net protocol identification compatible design method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111665795A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1728703A (en) * | 2005-06-29 | 2006-02-01 | 上海大学 | Method for converting protocol between Modbus and DeviceNet |
CN102710622A (en) * | 2012-05-22 | 2012-10-03 | 天津理工大学 | Protocol conversion device based on DeviceNet-Modbus |
CN109725575A (en) * | 2018-12-27 | 2019-05-07 | 南京熊猫电子股份有限公司 | The application system of compatible adaptive various field industrial bus communication |
-
2020
- 2020-05-06 CN CN202010372706.6A patent/CN111665795A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1728703A (en) * | 2005-06-29 | 2006-02-01 | 上海大学 | Method for converting protocol between Modbus and DeviceNet |
CN102710622A (en) * | 2012-05-22 | 2012-10-03 | 天津理工大学 | Protocol conversion device based on DeviceNet-Modbus |
CN109725575A (en) * | 2018-12-27 | 2019-05-07 | 南京熊猫电子股份有限公司 | The application system of compatible adaptive various field industrial bus communication |
Non-Patent Citations (1)
Title |
---|
陈在平等: "Device Net-Modbus 协议转换器的设计及实现", 《仪表技术与传感器》 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN112799992B (en) | Fieldbus chip architecture | |
CN100521637C (en) | Optical fiber-based high speed serial industrial real-time communication bus system and its control method | |
CN103825883A (en) | Multi-protocol conversion equipment based on wireless ZigBee, CAN bus and MODBUS/TCP and realization method thereof | |
CN105939253A (en) | Industrial wireless gateway device and protocol conversion method thereof | |
CN101770442A (en) | Data interaction system with a plurality of external interfaces and method | |
CN104714907B (en) | A kind of pci bus is converted to ISA and APB bus design methods | |
CN107948059A (en) | EtherCAT and Modbus protocol conversion gateways based on SPARC architecture microprocessors | |
CN102385351A (en) | Configurable remote input/output (IO) controller host | |
CN109725575A (en) | The application system of compatible adaptive various field industrial bus communication | |
CN102291337B (en) | Gateway for switching communication based on EtherCAT (Ethernet for Control and Automation Technology) protocol and Profibus-DP (Process Field Bus-Decentralized Periphery) protocol and communication method thereof | |
CN112398714A (en) | Backboard bus master station, system and data communication method thereof | |
CN101106504A (en) | Distributed communication system for intelligent independent robot based on CAN bus | |
CN106657115B (en) | Frequency converter control system and protocol conversion card thereof | |
CN116566762B (en) | Cascading equipment based on Modbus-RTU protocol and application method thereof | |
CN111665795A (en) | Modbus and Device Net protocol identification compatible design method | |
CN201054609Y (en) | High-speed industrial real time communication bus system based on optical fiber | |
CN116074397A (en) | Data sharing system | |
CN109328449A (en) | RTEX-EtherCAT protocol conversion apparatus and industrial control system | |
CN202093355U (en) | Programmable logic controller (PLC) Ethernet communication module | |
CN201054591Y (en) | A point-to-point industrial serial real time communication system based on optical fiber | |
Guangli et al. | Research and development for the communication interface conversion of Profibus and CAN bus | |
Hao et al. | Development for protocol conversion gateway of industrial field bus | |
CN106789183A (en) | It is a kind of to communicate the method that configuration data is parsed automatically | |
CN205486081U (en) | Embedded outside memory bus extension profinet bus device of CPU | |
CN205210585U (en) | System for through PROFIBUS PA active station direct read HART instrument parameter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200915 |