CN111654353A

CN111654353A - FEC scheme facing next generation Ethernet and decoder hardware architecture thereof

Info

Publication number: CN111654353A
Application number: CN201910162244.2A
Authority: CN
Inventors: 王中风; 严增超; 李文杰; 林军
Original assignee: Nanjing University
Current assignee: Nanjing University
Priority date: 2019-03-04
Filing date: 2019-03-04
Publication date: 2020-09-11

Abstract

As the technology of 400G ethernet is becoming more mature, the research work of next generation ethernet is also being developed, and the selection of forward error correction code (FEC) scheme is still an important issue in the research of next generation ethernet. The next generation ethernet is still expected to be implemented by at least 4 optical fiber, and in order to achieve a total throughput rate higher than 800Gbps, the FEC decoder needs to achieve a throughput rate of 200Gbps or even higher under the condition of satisfying coding gain. The power consumption of the decoder is reduced as much as possible while ensuring a high throughput. The invention discloses an FEC scheme facing to next generation Ethernet and a hardware framework of a decoder thereof. A Hamming code is adopted as an outer code and an RS code is adopted as a cascade code scheme of an inner code, the outer code adopts soft decoding, and the inner code adopts hard decoding. In addition, a hardware architecture of the cascade code decoder is designed, and through hardware synthesis and analysis, the decoder can achieve the throughput rate of 200 Gbps.

Description

FEC scheme facing next generation Ethernet and decoder hardware architecture thereof

Technical Field

The invention relates to the technical field of communication, in particular to a high-gain FEC scheme facing to next generation Ethernet and a high-speed low-complexity hardware architecture thereof.

Background

ETHERNET (ETHERNET) technology was proposed and implemented by Xerox corporation in 1973, and initially the ETHERNET rate was only 2.94 Mbp. In the eighties of the twentieth century, ethernet was becoming a network technology that started to be commonly used, which managed each network node device to transmit information on a network bus using a carrier sense multiple access (CSMA/CD) Medium Access Control (MAC) mechanism for collision detection and an 802.3LAN standard made by the Institute of Electrical and Electronics Engineers (IEEE). It is the most widely used and common network technology in the world, and is widely used in local area networks and enterprise backbones around the world.

In the first 30 years after the birth of ethernet, 6 ethernet speeds from 10M-100GE were generated: 10M, 100M, 1GE, 10GE, 40GE, 100GE, is basically a trend of 10 times increase in rate every 10 years. In the last 3 to 5 years, the new rate of ethernet began to exhibit a multidimensional evolution, and the industry began to be interested in another new 6-rate ethernet: from 2.5GE to 400GE, including 2.5GE, 5GE, 25GE, 50GE, 200GE, 400 GE. In 2016 only, the industry introduced 3 ethernet rates (2.5GE, 5GE, 25GE), and currently the standard is evolving for 3 ethernet rates (50GE, 200GE, 400 GE).

The PAM4 technology is applied to the Ethernet for the first time, and provides the possibility of low cost and large bandwidth for the future Ethernet. IEEE 802.3bs-2017 for 200GbE and 400GbE standards^TMOne key decision in the development of (1) was to shift both electrical and optical signaling from 25Gb/s NRZ signaling to 50Gb/s PAM4 signaling. This decision also affects the Ethernet specifications for 50GbE and 100GbE, as well as the physical layer solutions for 200GbE and 400GbE outside of the 802.3bs standard. As the development direction of the next generation ethernet, the 50GE standard industry has completed 802.3cd project, has completed standard formulation and formal release; on 6.12.2017, the IEEE 802.3 ethernet working group formally approved new IEEE 802.3bs ethernet definition standards, including media access control parameters, physical layer, management participation, which are required for 200G ethernet (200GbE) and 400G ethernet (400 GbE).

The next generation ethernet follows the IEEE 802.3bs/cd logical architecture, the physical coding and decoding layer adopts KP4FEC or stronger FEC, the speed of the latest known electrical interface is 100GbE, and 8 or 10 lane ports are needed to be in parallel in order to reach the throughput rate design index of the sub-coding layer of 800GbE or 1 TbE. Such a design has serious compatibility problems for the next generation ethernet interface, and the electromagnetic crosstalk effect between the electrical interfaces is also multiplied by the parallel of a plurality of lane interfaces. Therefore, the present invention provides an FEC decoding scheme and its high-speed hardware architecture that can achieve 200Gbps throughput rate under the condition of satisfying the coding gain of the next generation ethernet. The speed index of 800GbE can be achieved under the condition that a single FEC decoder can reach the electric speed of 200GbE and the same lane port is kept as the Ethernet of the previous generation.

The invention relates to a Forward Error Correction (FEC) scheme of a next-generation Ethernet, which is a cascade code scheme of Hamming codes and RS codes. In the concatenated code, the Hamming code (144, 136) is used as an outer code, and the RS code (544, 514) is used as an inner code, the outer code is soft-decoded, and the inner code is hard-decoded. The parameter of the inner code Hamming code is selected to satisfy that the overhead of the whole concatenated code is about 9%, and moreover, the parameter enables the transcoding (tc) scheme in IEEE 802.3bj to be compatible.

Disclosure of Invention

The prior literature only has certain research on the coding and decoding algorithm of the Hamming-RS cascade code, and the invention firstly provides a hardware architecture of a 200Gb/s Hamming-RS cascade code decoder. In this architecture:

● soft information LLR coming out from PAM4+ AWGN channel is quantized with 0bit integer and 4bits decimal, and can achieve lossless quantization under the condition of least bit width of soft information LLR through simulation test.

The ● Hamming decoder uses 5 decoders for parallel processing. The Hamming decoder is soft-decision decoding, 5 x 48 quantized LLR soft information is input into the whole Hamming decoder, 48 quantized LLR soft information is input into each decoder in each period, and 3 periods are needed to complete the input of a complete Hamming code. For each complete Hamming code, the whole decoder needs 5 cycles to decode completely.

● reverse interleaver is essentially some bit selector, selects the 5 x 136bits from the 5 x 144bits decoded by Hamming decoder, and then inputs the 5 x 136bits according to the reverse interleaving mode, every 10bits is a group of symbols which constitutes the symbols required by RS decoding, and 5 x 17symbols are obtained.

The ● RS decoder uses 4 decoders to process in parallel, and data input to the entire decoder is input every three cycles, each time 4 × 17symbols of processed data are input. Each RS decoder is a 17-parallel decoder, and 3 × 32 cycles are required to input a complete RS code. For each complete RS code, the entire decoder requires 158 cycles to decode completely.

The cascade code decoder structure adopts high-speed optimization design. The pipeline design enables the decoder to input a cascade code for decoding every 96 cycles, the key path of the designed hardware architecture can reach criticalpath < 1ns, and the bit number of the decoder input every time is 160 x 144bits, so that the Throughput rate of the decoder of the invention meets the requirement that Throughput is more than 200 Gb/s. With DC integration, the overall decoder consumes 114.4mW at 28 nm TSMC.

Drawings

FIG. 1 is a system framework diagram of the overall FEC scheme of the present invention;

FIG. 2 is a comparison of simulated performance curves for the FEC scheme of the present invention;

FIG. 3 is a comparison graph of simulation curves for different quantization bit numbers of received channel LLR soft information in accordance with the present invention;

FIG. 4 is an overall architecture diagram of a Hamming-RS concatenated code decoder according to the present invention;

FIG. 5 is a diagram of the hardware architecture of the high-efficiency Hamming soft decoder proposed in the present invention;

fig. 6 is a schematic diagram of an interleaving method in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be further described with reference to the accompanying drawings. The embodiments described below by referring to the drawings are exemplary and intended to be illustrative of the present invention and are not to be construed as limiting the present invention.

The next generation ethernet still uses lane ports, and four lane ports transmit 4 × 66 bits at a time, change to 257 bits by transcoding, and then encode by RS (544, 514). Therefore, when the outer code is not concatenated, the ratio of the code length to the information sequence length is

Here 544 corresponds to (544, 514) RS codes, 66 corresponding to the number of bits per block transmitted from the lane port. Our expectation is that OH is about 9%, then n/k is 1.09. The code rate of the code is R_outerIs provided with

To obtain

Considering (17, 18) × 8 ═ (136, 144), we use hamming codes for (136, 144) and galois fields are GF (2)⁸). The Hamming code is reduced by 11 bits from a Hamming code (247, 255) of a primitive length. In addition, in order to improve the coding gain of the concatenated code, an interleaving technique is used between RS codes. The overall system framework of the concatenated code is shown in fig. 1.

Fig. 2 shows the comparison of performance curves of l RS codes under interleaving (interleave), and through the comparison of simulation curves of different LLR quantization bits shown in fig. 3, the present invention selects an optimal hardware implementation scheme in which 4 RS codes are interleaved, Chase II soft decoding flip bits of Hamming codes are 3, and channel LLR soft information quantization bits are equal to 5 bits, on the premise that the design requirement of net coding gain can be satisfied.

The overall architecture design of the Hamming-RS concatenated code decoder is shown in FIG. 4. And inputting a concatenated code word into the whole concatenated code decoder every 96 periods, wherein each code word is a matrix with the size of 160 × 144, and each element in the matrix is LLR soft information quantized by 5 bits. The 160 × 144 quantized LLRs enter the decoder 5 × 48 LLRs each cycle, and all LLRs enter the decoder 96 cycles, that is, the code word of the next concatenated code enters the Hamming-RS concatenated code decoder.

Each Hamming decoder hardware architecture is as shown in fig. 5, because the Hamming decoder adopts 5 coarse-grained parallel processing, 5 × 48 quantized LLR soft information is input into the whole Hamming decoder in each period, wherein each sub-decoder inputs 48 quantized LLR soft information in each period, and 3 periods are required to complete the input of a complete Hamming code. After the 3 periods, the next Hamming code can be continuously input into the Hamming code decoder. For each complete Hamming code, the whole decoder needs 5 cycles to decode completely.

Fig. 6 shows the interleaving method adopted in the present invention, and in a hardware implementation, the interleaver and the inverse interleaver are essentially bit selectors. In the decoding process, the inverse interleaver selects the 5 x 144bits from the 5 x 144bits decoded by the Hamming decoder to obtain the 5 x 136bits, and then inputs the 5 x 136bits according to the inverse mode of coding interleaving, and every 10bits is a group of symbols required by RS decoding, so as to obtain the output of 5 x 17 symbols.

The RS decoder uses a conventional sophisticated hard decoding architecture. In the invention, 4 coarse-grained parallel processes are adopted by the RS decoder, and 17 fine-grained parallel processes are adopted by each sub RS decoder. Data input to the entire decoder is input every 3 cycles, 4 × 17symbols at a time. Each sub-RS decoder requires 3 x 32 cycles to input a complete RS code. The latency of each sub-RS decoder is 127 cycles, while for each complete RS code, the entire decoder requires 158 cycles to decode completely.

The technical indicators achieved for the entire concatenated code decoder are shown in table 1. The Hamming-RS cascade code scheme in the invention can achieve 0.85dB Net Coding Gain (NCG) under the modulation and demodulation of PAM4 and AWGN channel. The hardware architecture comprehensively realizes a critical path which can reach 1ns under the 28-nanometer process of the station accumulated power TSMC, and the comprehensive area is 465310.37mm²And the power consumption is 114.40mW, and the throughput rate of the whole decoder system reaches 220.13 Gb/s.

TABLE 1 technical index achieved by the inventive concatenated code decoder under TSMC process

NCG

Process for the preparation of a coating

Area of

Critical path

Delay

Power consumption

Throughput rate

0.85dB

TSMC 28nm

465310.37mm²

Ins

127ns

114.40mW

220.13Gb/s

Claims

1. The FEC scheme facing the next generation Ethernet disclosed by the invention is a cascading code scheme of Hamming codes and RS codes. In the concatenated code, the Hamming code (144, 136) is used as an outer code, and the RS code (544, 514) is used as an inner code, the outer code is soft-decoded, and the inner code is hard-decoded.

2. As described in claim 1, the parameter of the inner code Hamming code is selected to satisfy that the overhead of the entire concatenated code is about 9%, and furthermore, the parameter enables the transcoding (tc) scheme in IEEE 802.3bj to be compatible.

3. The method of claim 1, wherein the inner code is an RS code. In the invention, each cascade code comprises 4 interleaved RS codes, and the interleaving mode adopts simple A, B, C, D, A, B.

4. The outer code employs soft decoding, as recited in claim 1. In the invention, in order to meet the coding gain of 8.5dB under PAM4 modulation, a Chase II algorithm is selected, and the number of candidate bits is 3.

5. The invention also discloses a hardware architecture of the cascade code decoder, which mainly comprises 5 parallel Hamming code soft decoders and 4 RS code hard decoders. The decoder meets the requirements of throughput rate higher than 200Gbps, delay less than 200ns and power consumption less than 200mW under a 16nm technology.

6. As described in claim 5, each Hamming soft decoder uses a partially parallel structure, 3 cycles are required to receive a complete Hamming code soft information sequence, and 5 cycles are required for a complete Hamming code decoding.

7. As described in claim 5, each RS hard decoder adopts a partially parallel structure, 32 cycles are required for receiving a complete RS code symbol sequence, and 94 cycles are required for a complete RS code decoding.