CN111653852B - On-chip transformer-based transmission zero-point adjustable filter - Google Patents
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Abstract
The invention discloses an on-chip transformer-based transmission zero adjustable filter, which comprises a first on-chip transformer, a second on-chip transformer, an on-chip inductor, a bias circuit, a first capacitor, a second capacitor, a third capacitor, a fifth capacitor, a seventh capacitor and an MOS (metal oxide semiconductor) varactor, wherein the first capacitor, the second capacitor, the third capacitor, the fifth capacitor, the seventh capacitor and the MOS varactor are connected; the first port of the transformer on the first chip is used as the input end of the filter, the second port and the third port are grounded through the first capacitor and the third capacitor respectively, the second capacitor is connected between the second port and the third port in a bridging manner, and the fourth port is connected with the first port of the inductor on the chip and the first port of the transformer on the second chip; a second port of the on-chip inductor is connected with a first port of the biasing circuit, the second port is connected with the anode of the MOS varactor, and the cathode of the MOS varactor is grounded; and the second and third ports of the second on-chip transformer are grounded through a fifth capacitor and a seventh capacitor respectively, a sixth capacitor is connected between the second and third ports, and the fourth port is used as the output end of the filter. The filter has the advantages of small volume, flexible design, easy integration with other devices and the like, and can well meet the requirements of modern communication systems.
Description
Technical Field
The invention relates to the field of filters, in particular to an on-chip transformer-based transmission zero adjustable filter.
Background
In recent decades, with the rapid development of emerging microwave technology, the design of high-performance on-chip passive devices based on standard silicon (Si) technology has received great attention from both domestic and foreign researchers. Several different new approaches for on-chip passive device implementation have been proposed in recent literature, such as antennas, baluns, slow-wave transmission lines and band-pass filters (BPFs). Microwave filters are indispensable devices for transmitting and receiving ends in modern communication systems, and are used for separating signals, allowing useful signals to pass through without attenuation as much as possible, and attenuating useless signals as much as possible to inhibit the passage of the useless signals. The design of on-chip band-pass filters (BPFs), such as CMOS, based on commercial silicon (Si) technology has gained widespread interest in recent years. The results show that the design of the filter is one of the most challenging tasks, and the trade-off needs to be made in terms of satisfying the noise, bandwidth, stopband attenuation, model size, etc. of the system.
Chinese patent 201822061717.3 discloses an improved on-chip second-order band-pass filter, which is characterized in that | S is within the frequency range of 30 GHz-55 GHz11All values of | are below-10 dB, anThe band-pass filter has two obvious resonance points, is small in size and easy to integrate with other devices, but has poor passband selectivity, and only has one transmission zero point on the right side of the passband and is far away from the passband.
The researchers of Yang Yang Yang et al published a paper entitled "Compact On-Chip Band Filter With Improved In-Band deflection and stop and Attenuation In 0.13-mum (Bi) -CMOS Technology" On IEEE ELECTRON DEVICE LETTERS, which proposed a center-tap based ring resonator and parallel capacitor loaded Bandpass Filter, | S In the frequency range of 28 GHz-42 GHz11The value of | is below-10 dB, and has two obvious resonance points, the design concept is novel, the on-chip MIM capacitor loading is ingeniously utilized, but the passband selectivity is poor, and the transmission zero point and the adjustability are not provided.
In order to obtain better performance of the Band Pass Filter (BPF), different design methods are applied to the design of the Band Pass Filter (BPF), such as: in different transmission line forms, using semi-lumped elements, combining active and passive elements, etc. The on-chip filter design has the advantages that compared with the traditional filter design, the silicon-based CMOS process has multiple metal layers and active elements which are easy to integrate with passive elements on a chip, and the like, so that greater freedom is provided for the on-chip filter design. Designers can take full advantage of silicon-based CMOS processes to improve the performance of on-chip filters.
Disclosure of Invention
The invention aims to provide an on-chip transformer-based transmission zero tunable filter aiming at the defects and shortcomings in the prior art. The invention is based on the on-chip transformer and the on-chip inductor, utilizes the inherent coupling of the transformer and combines the process advantages of CMOS multi-layer metal, combines the passive element and the active element, designs the on-chip filter with novel and miniaturized form and adjustable transmission zero, and is particularly suitable for the new generation of communication single-chip microwave integrated circuits.
The technical solution for realizing the purpose of the invention is as follows: the on-chip transformer-based transmission zero adjustable filter comprises a first on-chip transformer, an on-chip inductor, a bias circuit, a second on-chip transformer, a first capacitor, a second capacitor, a third capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an MOS varactor;
a first port of the transformer on the first chip is used as an input port of the filter, a second port is grounded through a first capacitor, a third port is grounded through a third capacitor, a second capacitor is connected between the second port and the third port in a bridging manner, and a fourth port is connected with a first port of the inductor on the chip and a first port of the transformer on the second chip;
the second port of the on-chip inductor is connected with the first port of the biasing circuit, the second port of the biasing circuit is connected with the anode of the MOS varactor, and the cathode of the MOS varactor is grounded;
and a second port of the second on-chip transformer is grounded through a fifth capacitor, a third port of the second on-chip transformer is grounded through a seventh capacitor, a sixth capacitor is connected between the second port and the third port in a bridging mode, and a fourth port of the second on-chip transformer is used as an output port of the filter.
Compared with the prior art, the invention has the following remarkable advantages: 1) the invention combines the on-chip transformer and the capacitor to form the resonator of the filter by utilizing the inherent coupling of the transformer, and can flexibly change the resonance point and the coupling coefficient of the resonator by adjusting each parameter of the on-chip transformer and selecting a proper capacitor; 2) the invention adopts the on-chip inductor, and can freely and flexibly obtain the desired inductance value by adjusting each parameter value of the on-chip inductor; 3) the invention adopts the mode of connecting the on-chip inductor and the MOS varactor in series to form a transmission zero point, thereby realizing better selection performance of the filter passband; 4) the invention adopts the MOS varactor, fully utilizes the advantage that the active element and the passive element of the CMOS process are easy to integrate, can change the capacitance value of the MOS varactor by changing the applied voltage value of the MOS varactor, realizes the tunability of a transmission zero point, and further improves the better selection performance of a filter passband; 5) the invention fully utilizes the advantages of multilayer metals in the CMOS process, and the on-chip transformer and the on-chip inductor adopt a vertical structure, thereby effectively reducing the size of the device, having compact circuit model and high space utilization rate.
The present invention is described in further detail below with reference to the attached drawing figures.
Drawings
Fig. 1 is a schematic block diagram of an on-chip transformer-based transmission-zero-tunable filter according to an embodiment.
FIG. 2 is a diagram of a lower metal layer stack structure of a 0.18- μm Bi-CMOS based process according to an embodiment.
Fig. 3 is a schematic structural diagram of a first on-chip transformer in one embodiment.
Fig. 4 is a schematic structural diagram of an on-chip inductor in one embodiment.
FIG. 5 is a diagram illustrating an exemplary bias circuit.
FIG. 6 is a diagram illustrating a second on-chip transformer according to an embodiment.
Fig. 7 is a graph of the capacitance of a MOS varactor used in one embodiment as a function of its applied voltage.
Fig. 8 is a graph showing simulation results of the frequency response of the on-chip transformer-based transmission-zero-tunable filter according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, in conjunction with fig. 1, there is provided an on-chip transformer-based transmission zero tunable filter, the filter including a first on-chip transformer 1, an on-chip inductor 2, a bias circuit 3, a second on-chip transformer 4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and a MOS varactor;
a first port 1-1 of the first on-chip transformer 1 is used as an input port of the filter, a second port 1-2 is grounded through a first capacitor C1, a third port 1-3 is grounded through a third capacitor C3, a second capacitor C2 is connected between the second port 1-2 and the third port 1-3 in a bridging manner, and a fourth port 1-4 is connected with a first port 2-1 of the on-chip inductor 2 and a first port 4-1 of the second on-chip transformer 4;
a second port 2-2 of the on-chip inductor 2 is connected with a first port 3-1 of a bias circuit, a second port 3-2 of the bias circuit is connected with the anode of the MOS varactor, and the cathode of the MOS varactor is grounded;
the second port 4-2 of the second on-chip transformer 4 is grounded through a fifth capacitor C5, the third port 4-3 is grounded through a seventh capacitor C7, a sixth capacitor C6 is connected between the second port 4-2 and the third port 4-3, and the fourth port 4-4 serves as an output port of the filter.
Further, in one embodiment, the filter is implemented using a 0.18- μm Bi-CMOS process.
Further, in one embodiment, in conjunction with fig. 2, the 0.18- μ M Bi-CMOS process bottom metal layer stack structure includes a bottom-up silicon substrate, a first layer metal M1, a second layer metal M2, a third layer metal M3, a fourth layer metal M4, a fifth layer metal M5, and a top layer metal TM.
Further, in one embodiment, referring to fig. 3, the first on-chip transformer 1 includes an eleventh microstrip line L disposed on the top metal TM1_1A twelfth microstrip line L arranged on the fifth layer metal M51_2A thirteenth microstrip line L disposed on the fourth layer of metal M41_3And a fourteenth microstrip line L1_4The first port 1-1, the second port 1-2, the third port 1-3 and the fourth port 1-4 are arranged on the top layer metal TM; the eleventh microstrip line L1_1A twelfth microstrip line L1_2The metal layer stacking structures are all octagonal spiral structures and are coaxially arranged along the vertical axial direction of the metal layer stacking structure, and the tail ends of the two octagonal spiral structures are in the same direction and are symmetrical about the centers of the octagonal spiral structures; the eleventh microstrip line L1_1One end of the upper part close to the center of the octagonal spiral structure is provided with an eleventh through hole Via connecting the top layer metal TM and the fourth layer metal M41_1Is connected with a thirteenth microstrip line L1_3The other end of the first port 1-1 is connected with the first port 1-1, and the first port 1-1 is used as an input port of the filter; the thirteenth microstrip line L1_3The other end of the first and second metal layers is connected with a twelfth through hole Via of a fourth metal layer M41_2Is connected with the second end1-2 of mouth; the twelfth microstrip line L1_2One end of the upper part close to the center of the octagonal spiral structure is connected with a fourteenth through hole Via of the fifth layer metal M5 and the fourth layer metal M41_4Is connected with a fourteenth microstrip line L1_4And the other end of the second metal layer passes through a fifteenth Via hole Via connecting the top layer metal TM and the fifth layer metal M51_5Connecting a third port 1-3; the fourteenth microstrip line L1_4The other end of the second Via is connected to a thirteenth Via of the top metal TM and the fourth metal M41_3Fourth ports 1-4 are connected, the fourth ports 1-4 being output ports of the first on-chip transformer 1.
Preferably, the octagonal spiral structures are each a two-turn octagonal spiral structure.
Further, in one embodiment, with reference to fig. 4, the on-chip inductor 2 includes a twenty-first microstrip line L disposed on the top metal TM2_1A twenty-second microstrip line L arranged on the fifth layer metal M52_2And a first port 2-1 and a second port 2-2 arranged on the top layer metal TM; the twenty-first microstrip line L2_1Is an octagonal spiral structure, one end of which near the center of the octagonal spiral structure is provided with a twenty-first through hole Via connecting the top layer metal TM and the fifth layer metal M52_1Is connected with a twenty-second microstrip line L2_2And the other end is connected with a second port 2-2; the twenty-second microstrip line L2_2The other end of the first layer is connected with a second twelve through hole Via of a top layer metal TM and a fifth layer metal M52_2The first port 2-1 is connected.
Further preferably, in one embodiment, the first port 2-1 and the second port 2-2 of the on-chip inductor 2 are located on the same straight line.
Further, in one embodiment, with reference to fig. 5, the bias circuit 3 includes a dc blocking capacitor C4, a dc bias resistor R, and a dc voltage source; one end of the blocking capacitor C4 is used as a first port 3-1 of the bias circuit 3, and the other end is grounded through the direct current bias resistor R and the direct current voltage source in sequence; and the common end of the DC blocking capacitor C4 and the DC bias resistor R is used as a second port 3-2 of the bias circuit 3.
Further, in one embodiment, with reference to fig. 6, the second on-chip transformer 4 includes a forty-first microstrip line L disposed on the top metal TM4_1A forty-second microstrip line L arranged on the fifth layer metal M54_2A forty-third microstrip line L disposed on the fourth layer of metal M44_3And a forty-fourth microstrip line L4_4The first port 4-1, the second port 4-2, the third port 4-3 and the fourth port 4-4 are arranged on the top layer metal TM; the forty-first microstrip line L4_1And a forty-second microstrip line L4_2The metal layer stacking structures are all octagonal spiral structures and are coaxially arranged along the vertical axial direction of the metal layer stacking structure, and the tail ends of the two octagonal spiral structures are in the same direction and are symmetrical about the centers of the octagonal spiral structures; the forty-first microstrip line L4_1One end of the upper part close to the center of the octagonal spiral structure is provided with a forty-first through hole Via which is used for connecting the top layer metal TM with the fourth layer metal M44_1Connecting the forty-third microstrip line L4_3The other end of the first on-chip transformer 4 is connected with a first port 4-1, and the first port 4-1 is used as an input end of the second on-chip transformer 4; the forty-third microstrip line L4_3The other end of the first metal layer is connected with a fourth twelve through hole Via of a fourth metal layer M4 through a top layer metal TM4_2Connecting the second port 4-2; the forty second microstrip line L4_2One end of the upper part close to the center of the octagonal spiral structure is connected with a fourteen through hole Via of a fifth layer metal M5 and a fourth layer metal M44_4Is connected with a forty-fourth microstrip line L4_4And the other end of the second metal layer passes through a fifteenth Via hole Via connecting the top layer metal TM and the fifth layer metal M54_5Connecting a third port 4-3; the forty-fourth microstrip line L4_4The other end of the first and second metal layers passes through a forty-three through hole Via connecting the top layer metal TM and the fourth layer metal M44_3The fourth port 4-4 is connected and the fourth port 4-4 is used as the output port of the filter.
Preferably, the octagonal spiral structures are each a two-turn octagonal spiral structure.
As a specific example, in one of the embodiments, the invention is further described. The specific parameter setting of the system comprises the following steps: first capacitor C1 and third capacitorThe capacitance values of the capacitor C3, the fifth capacitor C5 and the seventh capacitor C7 are 836.8pf, the capacitance values of the second capacitor C2 and the sixth capacitor C6 are 827.6pf, the variation curve of the capacitance value of the MOS varactor along with the applied voltage is shown in FIG. 7, and it can be seen from FIG. 7 that the capacitance value of the MOS varactor increases from 1.3pf to 5.3pf in the process of changing the applied voltage from-2V to 2V; the stack structure of the lower metal layer of the 0.18-mum Bi-CMOS process is schematically shown in FIG. 2, wherein the thicknesses of the first metal layer M1, the second metal layer M2, the third metal layer M3, the fourth metal layer M4, the fifth metal layer M5 and the top metal layer TM are hm1＝0.5um，hm2＝0.5um，hm3＝0.5um，hm4＝0.5um，hm5＝0.9um，htm2.92um, the distance between the top layer metal TM and the fifth layer metal M5 is S12um, the distance between the fifth layer metal M5 and the fourth layer metal M4 is S20.71um, the distance between the fourth layer metal M4 and the third layer metal M3 is S30.71um, the distance between the third layer metal M3 and the second layer metal M2 is S40.71um, the distance between the second layer metal M2 and the first layer metal M1 is S50.71 um. First on-chip transformer structure figure is shown in fig. 3, the dimensions of the first on-chip transformer are as follows: eleventh microstrip line L1_1Radius r1_150um, twelfth microstrip line L1_2Radius r of1_250um, eleventh microstrip line L1_1Line width W of1_112um, twelfth microstrip line L1_2Line width W of1_212um, eleventh microstrip line L1_1A twelfth microstrip line L1_2The spacing S between the two coils 1_15 um. On-chip inductor structure fig. 4 shows the dimensions of the on-chip inductor as follows: twenty-first microstrip line L2_1Radius r of213um, twenty-first microstrip line L2_1Line width W of223um, twenty-first microstrip line L2_1Spacing S between two coils215 um. As shown in fig. 5, the capacitance of the fourth capacitor C4 is 418.4pf, and the bias resistor R is 1K Ω. The structure of the second on-chip transformer is shown in fig. 6, and the dimensions of the second on-chip transformer are as follows: forty-first microstrip line L4_1Half ofDiameter r4_150um, the forty-second microstrip line L4_2Radius r of4_250um, the forty-first microstrip line L4_1Line width W of4_112um, the forty-second microstrip line L4_2Line width W of4_212um, the forty-first microstrip line L4_1And a forty-second microstrip line L4_2The spacing S between the two coils4_1＝5um。
Fig. 8 is a graph showing the frequency response result of the on-chip transformer-based transmission-zero-tunable filter in this embodiment, and the graph shows the frequency response of the filter in three states of-1V, -0.5V and 0V applied voltage of the MOS varactor. As can be seen from the figure, the transmission zero point gradually moves toward the low frequency end (left) as the voltage changes from-2V to 2V. Under the condition that the applied voltage of the MOS varactor is 0V, the center frequency of the filter is 5.3GHz, the bandwidth is 66%, and the transmission zero point is 11.6 GHz.
The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments, and any other changes, simplifications, substitutions, and combinations that do not depart from the spirit and principle of the present invention should be construed as being included in the scope of the present invention.
Claims (8)
1. The on-chip transformer-based transmission zero adjustable filter is characterized by comprising a first on-chip transformer (1), an on-chip inductor (2), a bias circuit (3), a second on-chip transformer (4), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fifth capacitor (C5), a sixth capacitor (C6), a seventh capacitor (C7) and a MOS varactor;
a first port (1-1) of the first on-chip transformer (1) is used as an input port of the filter, a second port (1-2) is grounded through a first capacitor (C1), a third port (1-3) is grounded through a third capacitor (C3), a second capacitor (C2) is connected between the second port (1-2) and the third port (1-3) in a bridging manner, and a fourth port (1-4) is connected with a first port (2-1) of the on-chip inductor (2) and a first port (4-1) of the second on-chip transformer (4);
a second port (2-2) of the on-chip inductor (2) is connected with a first port (3-1) of the bias circuit, a second port (3-2) of the bias circuit is connected with the anode of the MOS varactor, and the cathode of the MOS varactor is grounded;
the second port (4-2) of the second on-chip transformer (4) is grounded through a fifth capacitor (C5), the third port (4-3) is grounded through a seventh capacitor (C7), a sixth capacitor (C6) is connected between the second port (4-2) and the third port (4-3), and the fourth port (4-4) serves as an output port of the filter.
2. The on-chip transformer-based transmission-zero-tunable filter of claim 1, wherein the filter employs a 0.18- μm Bi-CMOS process.
3. The on-chip transformer-based transmission-zero-tunable filter of claim 2, wherein the 0.18- μ M Bi-CMOS process lower metal layer stack structure comprises a silicon substrate, a first layer metal (M1), a second layer metal (M2), a third layer metal (M3), a fourth layer metal (M4), a fifth layer metal (M5) and a top layer metal (TM) from bottom to top.
4. The on-chip transformer-based transmission-zero-tunable filter according to claim 3, characterized in that the first on-chip transformer (1) comprises an eleventh microstrip line (LxW) disposed on top-level metal (TM)1_1) A twelfth microstrip line (L) arranged on the fifth layer metal (M5)1_2) A thirteenth microstrip line (L) disposed on the fourth layer of metal (M4)1_3) And a fourteenth microstrip line (L)1_4) And a first port (1-1), a second port (1-2), a third port (1-3) and a fourth port (1-4) arranged on the top layer metal (TM); the eleventh microstrip line (L)1_1) A twelfth microstrip line (L)1_2) The metal layer stacking structures are all octagonal spiral structures and are coaxially arranged along the vertical axial direction of the metal layer stacking structure, and the tail ends of the two octagonal spiral structures are in the same direction and are symmetrical about the centers of the octagonal spiral structures; the eleventh microstrip line (L)1_1) One end of the upper part close to the center of the octagonal spiral structure is connected with an eleventh through hole (Via) of a fourth layer metal (M4) through a top layer metal (TM)1_1) Connecting a thirteenth microstrip line (L)1_3) The other end of the first port (1-1) is connected with the first port (1-1), and the first port (1-1) is used as an input port of the filter; the thirteenth microstrip line (L)1_3) The other end of the first and second electrodes is connected with a twelfth through hole (Via) for connecting the Top Metal (TM) and the fourth metal (M4)1_2) Connecting a second port (1-2); the twelfth microstrip line (L)1_2) One end of the upper part close to the center of the octagonal spiral structure is connected with a fourteenth through hole (Via) of a fifth layer metal (M5) and a fourth layer metal (M4)1_4) Is connected with a fourteenth microstrip line (L)1_4) And the other end of the first and second metal layers (M5) through a fifteenth Via (Via) connecting the Top Metal (TM) and the fifth metal (M5)1_5) Connecting a third port (1-3); the fourteenth microstrip line (L)1_4) Is connected to the fourth layer metal (M4) through a thirteenth Via hole (Via) connecting the top layer metal (TM) and the fourth layer metal (M4)1_3) And the fourth ports (1-4) are connected, and the fourth ports (1-4) are used as output ports of the first on-chip transformer (1).
5. The on-chip transformer-based transmission-zero-tunable filter according to claim 3, characterized in that the on-chip inductor (2) comprises a twenty-first microstrip line (Lw) disposed on Top Metal (TM)2_1) A twenty-second microstrip line (L) arranged on the fifth layer metal (M5)2_2) And a first port (2-1) and a second port (2-2) arranged on the top layer metal (TM); the twenty-first microstrip line (L)2_1) Is an octagonal spiral structure, and one end of the octagonal spiral structure near the center is provided with a twenty-first through hole (Via) for connecting the top layer metal (TM) and the fifth layer metal (M5)2_1) Is connected with a twenty-second microstrip line (L)2_2) And the other end is connected with the second port (2-2); the twenty-second microstrip line (L)2_2) The other end of the first and second metal layers is connected with a second twelve through hole (Via) of a top layer metal (TM) and a fifth layer metal (M5)2_2) The first port (2-1) is connected.
6. The on-chip transformer-based transmission-zero-tunable filter according to claim 5, wherein the first port (2-1) and the second port (2-2) of the on-chip inductor (2) are located on the same straight line.
7. The on-chip transformer-based transmission-zero-tunable filter according to claim 1 or 3, wherein the bias circuit (3) comprises a dc blocking capacitor (C4), a dc bias resistor (R), and a dc voltage source; one end of the direct current blocking capacitor (C4) is used as a first port (3-1) of the bias circuit (3), and the other end of the direct current blocking capacitor (C4) is grounded through the direct current bias resistor (R) and the direct current voltage source in sequence; and the common end of the DC blocking capacitor (C4) and the DC bias resistor (R) is used as a second port (3-2) of the bias circuit (3).
8. The on-chip transformer-based transmission-zero-tunable filter according to claim 3, characterized in that the second on-chip transformer (4) comprises a forty-first microstrip line (L) disposed on a top-level metal (TM)4_1) A forty-second microstrip line (L) arranged on the fifth layer metal (M5)4_2) A forty-third microstrip line (L) disposed on the fourth layer of metal (M4)4_3) And a forty-fourth microstrip line (L)4_4) And a first port (4-1), a second port (4-2), a third port (4-3) and a fourth port (4-4) arranged on the top layer metal (TM); the forty-first microstrip line (L)4_1) And a forty-second microstrip line (L)4_2) The metal layer stacking structures are all octagonal spiral structures and are coaxially arranged along the vertical axial direction of the metal layer stacking structure, and the tail ends of the two octagonal spiral structures are in the same direction and are symmetrical about the centers of the octagonal spiral structures; the forty-first microstrip line (L)4_1) One end of the upper part close to the center of the octagonal spiral structure is connected with a forty-first through hole (Via) of a fourth layer metal (M4) through a top layer metal (TM)4_1) Connecting a forty-third microstrip line (L)4_3) The other end of the first on-chip transformer (4) is connected with a first port (4-1), and the first port (4-1) is used as the input end of the second on-chip transformer (4); the forty-third microstrip line (L)4_3) The other end of the first and second electrodes is connected with a fourth twelve through hole (Via) of a top layer metal (TM) and a fourth layer metal (M4)4_2) Connecting a second port (4-2); the forty-second microstrip line (L)4_2) One end of the upper part near the center of the octagonal spiral structure is connected with the fifth layer metal (M5) and the fourth layer metal (M4) through a fourth layerFourteen through holes (Via)4_4) Is connected with a forty-fourth microstrip line (L)4_4) And the other end of the first and second metal layers (M5) through a fifteenth Via (Via) connecting the Top Metal (TM) and the fifth metal (M5)4_5) Connecting a third port (4-3); the forty-fourth microstrip line (L)4_4) Is connected to the fourth layer metal (M4) through a forty-third through hole (Via) connecting the top layer metal (TM) and the fourth layer metal (M4)4_3) The fourth port (4-4) is connected, and the fourth port (4-4) is used as an output port of the filter.
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| WO2003073550A1 (en) * | 2002-02-22 | 2003-09-04 | Arizona Board Of Regents | Integration of filters using on-chip transformers for rf and wireless applications |
| CN101741326A (en) * | 2008-11-13 | 2010-06-16 | 株式会社瑞萨科技 | Rf power amplifier |
| CN106992762A (en) * | 2017-02-22 | 2017-07-28 | 加特兰微电子科技(上海)有限公司 | Amplifier and its control method and signal processing system |
| CN110380707A (en) * | 2019-06-14 | 2019-10-25 | 浙江大学 | A kind of on piece Vector Modulation phase shifter |
Family Cites Families (4)
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| US9362883B2 (en) * | 2013-03-13 | 2016-06-07 | Tdk Corporation | Passive radio frequency signal handler |
| US9779868B2 (en) * | 2014-04-30 | 2017-10-03 | Qorvo Us, Inc. | Compact impedance transformer |
| JP6549451B2 (en) * | 2015-09-02 | 2019-07-24 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and electronic device |
| US10749499B2 (en) * | 2018-08-28 | 2020-08-18 | Qualcomm Incorporated | Wideband filter including an acoustic resonator chip integrated with 3D inductors and a 3D transformer |
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| WO2003073550A1 (en) * | 2002-02-22 | 2003-09-04 | Arizona Board Of Regents | Integration of filters using on-chip transformers for rf and wireless applications |
| CN101741326A (en) * | 2008-11-13 | 2010-06-16 | 株式会社瑞萨科技 | Rf power amplifier |
| CN106992762A (en) * | 2017-02-22 | 2017-07-28 | 加特兰微电子科技(上海)有限公司 | Amplifier and its control method and signal processing system |
| CN110380707A (en) * | 2019-06-14 | 2019-10-25 | 浙江大学 | A kind of on piece Vector Modulation phase shifter |
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