CN111653538A - Routing method for improving surface current uniformity of power chip - Google Patents

Routing method for improving surface current uniformity of power chip Download PDF

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Publication number
CN111653538A
CN111653538A CN202010557344.8A CN202010557344A CN111653538A CN 111653538 A CN111653538 A CN 111653538A CN 202010557344 A CN202010557344 A CN 202010557344A CN 111653538 A CN111653538 A CN 111653538A
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Prior art keywords
metal
power chip
source
power
current bridge
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CN202010557344.8A
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Chinese (zh)
Inventor
朱袁正
周锦程
朱久桃
丛微微
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Wuxi Dianji Integrated Technology Co ltd
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Wuxi Dianji Integrated Technology Co ltd
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Priority to CN202010557344.8A priority Critical patent/CN111653538A/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a routing method for improving the surface current uniformity of a power chip, which can effectively inhibit the temperature rise of the edge position of a source electrode of the power chip and avoid the generation of the local overheating problem during avalanche breakdown.

Description

Routing method for improving surface current uniformity of power chip
Technical Field
The invention relates to a packaging method of a semiconductor device, in particular to a routing method capable of improving the surface current uniformity of a power chip.
Background
The power device is one of core components of a power integrated circuit, is widely used in a power module of an electronic system and plays a role in power conversion; especially plays an important role in the fields of emerging 5G, extra-high voltage, rail transit, large data centers, artificial intelligence and the like.
Power chips such as MOSFET and IGBT are the most common power devices on the market, and they usually adopt a vertical structure, i.e. the source (emitter) and the drain (collector) are distributed on two opposite planes of the wafer, and can flow large current and have high voltage. In order to solve the problem of large-current, high-power and high-frequency conversion failure or fatigue effect in the terminal application process, reduce the local heat of a power chip and prevent the occurrence of the device thermal breakdown phenomenon, designers usually only pay attention to the cell structure, Gatebus and terminal adjustment of the power chip, neglect the weak link of lead routing in the packaging process, and find that the lead bonding failure mechanism has extremely important significance for improving the reliability of the power device through research.
At present, in the packaging of a power chip, wire bonding materials mainly comprise an aluminum wire and a copper wire, and the connection of the power chip and a metal frame can be realized only by adopting a small amount of copper wires and aluminum wires under the condition of small conduction current; however, with the continuous increase of the current density of the power device, in the actual production, a plurality of bonding leads are needed to connect the power chip electrode and the metal pin, so as to reduce the thermo-electronic effect and the resistance value of the on-resistance, reduce the power loss, improve the product characteristics, and further prolong the service life of the product; however, due to the limitation of the surface layout of the power chip, the bonding wires cannot be uniformly distributed on the surface of the chip, and the gate material of the power chip is made of polysilicon, so that the power chip has large distributed resistance, under the gate bias condition, due to the existence of the distributed resistance, the cell region far away from the gate pressure welding point cannot be completely and effectively turned on, if the turn-on is insufficient, the turn-on voltage is too high, so that the current distribution on the surface of the chip is not uniform, especially at the corner positions of some chips, if the turn-on is slow and the current is not uniform, the problem that the chip is easily burned out due to avalanche breakdown in the regions occurs.
Therefore, the invention provides a wire bonding method capable of improving the uniformity of current at the wire bonding position of the power chip, ensuring that all areas of a cellular area are effectively opened, and alleviating the heat concentration phenomenon, and the wire bonding method becomes a problem to be solved by the technical staff.
Disclosure of Invention
The invention provides a routing method for improving the surface current uniformity of a power chip, which aims to solve the problem that the prior routing method cannot ensure the surface current uniformity of the chip due to the limitation of the surface layout of the power chip in the prior art, so that a cell area of the chip, particularly the problem that the chip is damaged due to overhigh temperature at a corner position, can effectively inhibit the temperature rise at the edge position of a source electrode of the power chip and avoid the problem of local overheating during avalanche breakdown.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a routing method for improving surface current uniformity of a power chip comprises the steps of arranging a drain electrode, a grid electrode and a source electrode on the surface of the power chip, wherein the drain electrode is arranged on the surface of the power chip; the drain electrode is arranged at the bottom end of the power chip, and the grid electrode and the source electrode are arranged at the top end of the power chip;
the drain electrode at the bottom end of the power chip is welded with the center of the drain electrode metal gasket, the drain electrode metal pin is led out from the drain electrode metal gasket, the source electrode of the power chip is connected with the source electrode metal pin through the source electrode metal wire, the grid electrode of the power chip is connected with the grid electrode metal pin through the grid electrode metal wire, one end of the source electrode metal wire is welded with the source electrode at the top end of the power chip, the other end of the source electrode metal wire is welded with the source electrode metal pin, one end of the grid electrode metal wire is welded with the grid electrode at the top end of the power chip, and the other end of the grid electrode metal wire is welded with the grid electrode: the surface of the source electrode at the top end of the power chip is provided with a metal current bridge, the metal current bridge is in a point shape or a linear shape, and the metal current bridge is not positioned in an area where the source electrode metal wire is connected with the source electrode.
It is further characterized in that the method further comprises the steps of,
when the metal current bridge is linear, the routing direction is any direction, and the length of the metal current bridge is not less than 10 um;
when the metal current bridge is in a point shape, the diameter of the metal current bridge is not less than 10 um;
a plurality of power chips are arranged on the base island in parallel;
the power chip is a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor or a fast recovery diode;
the metal current bridge is any metal suitable for ultrasonic welding;
the metal current bridge is made of gold, silver, copper, aluminum, silver or alloy materials thereof.
Compared with the prior art, the invention has the following advantages:
the metal current bridge is arranged on the source metal on the surface of the power chip, so that the parasitic resistance of the edge position of the source can be reduced, the current flowing to the source metal wire at the edge position of the source is adjusted, and the temperature rise of the edge position of the source is restrained.
When the power chip is in an avalanche large current state, the current at the edge of the source electrode is rapidly transmitted to the central position of the source electrode through the metal current bridge, so that the local overheating phenomenon caused by the gathering of the current on the source electrode metal is avoided, and the reliability of the power device is improved.
Drawings
FIG. 1 is a schematic top view of a first embodiment of the present invention;
FIG. 2 is a schematic top view of a second embodiment of the present invention;
FIG. 3 is an enlarged view of portion A of FIG. 2;
FIG. 4 is a schematic view of the AA-oriented cross-sectional front view of FIG. 3;
FIG. 5 is a schematic top view of a third embodiment of the present invention;
description of reference numerals: 1. a power chip; 2. a source metal line; 3. a source metal pin; 4. a drain metal pin; 5. a drain metal pad; 6. a gate metal line; 7. a gate metal pin; 8. a metal current bridge; 9. a source metal plate; 10. a drain metal; 11. a substrate; 12. an epitaxial layer; 13. a trench; 14. Shielding grid polysilicon; 15. a field oxide layer; 16. grid polysilicon; 17. a gate oxide layer; 18. -a body region; 19. A source region; 20. and a source metal.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1, in a first embodiment, a wire bonding method for improving surface current uniformity of a power chip includes two power chips 1 placed in parallel in a transverse direction, two source metal wires 2, a source metal pin 3, a drain metal pin 4, a drain metal pad 5, a gate metal wire 6, a gate metal pin 7, a drain at the bottom of the power chip 1 is welded at the center of the drain metal pad 5, the drain metal pin 4 is led out from the drain metal pad 5, one end of the source metal wire 2 is welded with a source at the top of the power chip 1, the other end of the source metal wire is welded with the source metal pin 3, one end of the gate metal wire 6 is welded with a gate on the surface of the power chip 1, and the other end of the gate metal wire is welded with the gate metal pin;
because the length of the gate lines of the two power chips 1 is different, the opening time is sequential, and the lengths of the two source metal lines 2 are different, the current on the two power chips 1 is easily different; the linear metal current bridge 8 is arranged at the corner position of the source electrode of the power chip 1 and is not arranged in the area where the source electrode metal wire 2 is connected with the source electrode, the arrangement of the linear metal current bridge 8 can enable the parasitic resistances of the source electrodes of the two power chips 1 to be close, so that the currents flowing on the two source electrode metal wires 2 tend to be consistent, one end of the metal current bridge 8 is welded with the corner position of the source electrode at the top end of the power chip 1, the other end of the metal current bridge 8 is arranged towards the center of the source electrode and is welded with the source electrode, the length of the metal current bridge 8 is 30 micrometers, and the shortest distance from the metal current bridge 8 to the edge of; one end of the grid metal wire 6 is welded with the grid on the surface of the power chip 1, and the other end is welded with the grid metal pin 7.
As shown in fig. 2, in the second embodiment, a wire bonding method for improving surface current uniformity of a power chip includes a power chip 1, ten source metal wires 2, a source metal pin 3, a drain metal pin 4, a drain metal pad 5 (here, a DBC structure), a gate metal wire 6, a gate metal pin 7, a dotted metal current bridge 8, and a source metal sheet 9, a drain at the bottom of the power chip 1 is soldered on the drain metal pad 5, the drain metal pin 4 is led out from the drain metal pad 5, one end of the source metal wire 2 is soldered to a source on the surface of the power chip 1, and the other end is soldered to the source metal sheet 9, because the size of the power chip 1 is large, and the source metal pin is located at one side of one power chip 1, the lengths of the ten source metal wires 2 are different, and a parasitic resistance close to a source edge position far from the source metal wire 2 is large, therefore, the dotted metal current bridges are arranged in the non-source metal line connection area on the upper surface of the source electrode of the power chip 1, the number of the dotted metal current bridges 8 in the embodiment is six, the diameter of each dotted metal current bridge 8 is 120um, the six dotted metal current bridges 8 are uniformly arranged at intervals, the distance between every two adjacent metal current bridges 8 is 5um, the shortest distance between each metal current bridge 8 and the edge of the source electrode on the surface of the power chip 1 is 5um, and the dotted metal current bridges 8 can enable the parasitic resistance of the source electrode of the power chip 1 to be close, so that the currents flowing through the source metal lines 2 tend to be consistent, and the currents of the power chip 1 are more uniform; one end of the grid metal wire 6 is welded with the grid on the surface of the power chip 1, and the other end of the grid metal wire is welded with the grid metal pin 7.
As shown in fig. 3 and 4, the power chip 1 includes a drain 10, a substrate 11, an epitaxial layer 12, a body region 18, and a source region 19, which are sequentially disposed from bottom to top, wherein a trench 13 is disposed on a surface of the epitaxial layer 12, one end of the trench 13 is disposed in the epitaxial layer 12, and the other end of the trench 13 sequentially penetrates through an upper surface of the epitaxial layer 12, the body region 18, and the source region 19 from bottom to top, and then enters the epitaxial layer 12; the polycrystalline silicon 14 is arranged in the groove 13, the outer surface of the polycrystalline silicon 14 wraps the shielding gate 15, the upper portion of the shielding gate 15 is provided with gate polycrystalline silicon 16 which is circumferentially arranged along the upper portion of the polycrystalline silicon 14, gaps between the gate polycrystalline silicon 16 and the source region 19, the body region 18 and the epitaxial layer 12 are respectively filled with a gate oxide layer 17, the gate oxide layers 17 are used for realizing isolation of the gate polycrystalline silicon 16 from the source region 19, the body region 18 and the epitaxial layer 12, the top of the epitaxial layer 12 and the top of the groove 13 are provided with insulating medium layers, source metal 20 is arranged above the insulating medium layers, the bottom end of the source metal 20 is in contact with the body region 18 and the source region 19 through a through hole.
Referring to fig. 5 and the third embodiment, a wire bonding method for improving the surface current uniformity of a power chip includes a power chip 1, the power chip 1 includes an FRD chip 1-1, an IGBT chip 1-2, a source metal line 2, a source metal strip 4-1, the source metal strip 4-1 is made of aluminum, a source metal pin 3, a drain metal pin 4, a drain metal pad 5, a gate metal pin 7, a gate metal line 6, a linear metal current bridge 8, drains on the back of the FRD chip 1-1 and the IGBT chip 2-1 are all welded to the drain metal pad 5, the drain metal pin 4 is led out from the drain metal pad 5, the gate metal pin 7 is connected to the gate of the IGBT chip 1-2 through the gate metal line 6, one end of the source metal line 2 is welded to the source on the surface of the FRD chip 1-1, and the other end is welded to the source metal pin 3, one end of a source metal strap 4-1 is welded with a source electrode on the surface of the IGBT chip 1-2, the other end is welded with a source metal pin 3, a linear metal current bridge 8 is arranged between the FRD chip 1-1 and the IGBT chip 1-2 and connects the two power chips, one end of the linear metal current bridge 8 is welded with the FRD chip 1-1, the other end is welded with the IGBT chip 1-2, namely the linear metal current bridge 8 is positioned on the source electrode equipotential between the source metal strap 4-1 and the source metal wire 2, the widths of the source metal strap 4-1 and the source metal wire 2 are inconsistent, therefore, the flowing currents are different in magnitude, so that the parasitic resistance of the adjacent regions of the FRD chip 1-1 and the IGBT chip 1-2 is larger, and the linear metal current bridge 8 is lapped between the FRD chip 1-1 and the IGBT chip 1-2 (in the embodiment, a plurality of the linear metal current bridges 8 can be simultaneously arranged on the The metal current bridge 8 can reduce the parasitic resistance of weak position round cells of the FRD chip 1-1 and the IGBT chip 2-1, so that the current flowing through each source electrode metal wire 2 tends to be consistent, and the current of the power chip 1 is more uniform.
In the first, second, and third embodiments, the shape of the metal current bridge 8 is determined according to the layout requirement of the source on the surface of the power chip 1, and when the non-source metal line connection area of the source on the surface of the power chip 1 is large, a linear metal current bridge may be selected, for example, in the first embodiment; when the non-source metal connection line region of the source on the surface of the power chip 1 is small, a dotted metal current bridge may be selected, for example, in embodiment two; when the edge areas of two adjacent power chips are large, in order to reduce the parasitic resistance of the adjacent areas, a linear metal current bridge is adopted to be connected between the two power chips in an overlapping mode, so that current can flow through the linear metal current bridge, and the parasitic resistance of the adjacent areas is reduced.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (6)

1. A routing method for improving surface current uniformity of a power chip comprises the power chip, a source metal pin, a grid metal wire, a source metal wire, a drain metal pin and a drain metal gasket, wherein the surface of the power chip is provided with a source electrode, a grid electrode and a drain electrode, the source electrode of the power chip is connected with the source metal pin through the source metal wire, the grid electrode of the power chip is connected with the grid metal pin through the grid metal wire, the drain electrode at the bottom end of the power chip is welded on the drain metal gasket, and the drain metal pin is led out of the drain metal gasket, and the routing method is characterized in that: and a metal current bridge is arranged on the source electrode of the power chip and is in a point shape or a linear shape.
2. The wire bonding method for improving the uniformity of the surface current of the power chip according to claim 1, wherein: the power chip is characterized in that a linear metal current bridge is arranged on a source electrode of the power chip, and when the metal current bridge is linear, the length of the metal current bridge is not less than 10 um.
3. The wire bonding method for improving the uniformity of the surface current of the power chip according to claim 1, wherein: the source electrode of the power chip is provided with a punctiform metal current bridge, and when the metal current bridge is punctiform, the diameter of the metal current bridge is not less than 10 um.
4. The wire bonding method for improving the uniformity of the surface current of the power chip according to claim 1, wherein: and simultaneously arranging a point-shaped and linear metal current bridge on the source electrode of the power chip, wherein the point-shaped metal current bridge is arranged in a routing area of the non-source electrode metal wire.
5. The wire bonding method for improving the surface current uniformity of the power chips according to any one of claims 1 to 4, wherein a plurality of power chips are arranged on the base island of the power module in parallel; the power chip is a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor or a fast recovery diode.
6. The bonding method according to claim 5, wherein the metal current bridge is made of gold, silver, copper, aluminum, silver or an alloy thereof.
CN202010557344.8A 2020-06-18 2020-06-18 Routing method for improving surface current uniformity of power chip Pending CN111653538A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114496965A (en) * 2022-04-18 2022-05-13 江苏长晶浦联功率半导体有限公司 Semiconductor packaging routing structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114496965A (en) * 2022-04-18 2022-05-13 江苏长晶浦联功率半导体有限公司 Semiconductor packaging routing structure
CN114496965B (en) * 2022-04-18 2022-09-20 江苏长晶浦联功率半导体有限公司 Semiconductor packaging routing structure

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