CN111651957B

CN111651957B - Integrated circuit Miller factor offset wiring method

Info

Publication number: CN111651957B
Application number: CN202010775354.9A
Authority: CN
Inventors: 韩志刚
Original assignee: Fugu Technology Nanjing Co ltd
Current assignee: Fugu Technology Nanjing Co ltd
Priority date: 2020-08-05
Filing date: 2020-08-05
Publication date: 2020-11-06
Anticipated expiration: 2040-08-05
Also published as: CN111651957A

Abstract

The invention discloses a Miller factor offset wiring method of an integrated circuit, which comprises the steps of firstly determining a line as an interfered line, then taking two adjacent lines as interference source lines, and replacing one or two buffers in the interference source lines with inverters on the basis of arranging buffers in each network so as to enable adjacent signals to switch polarities, thereby reducing coupling capacitance generated by the adjacent signals and realizing reduction of total delay. No matter which direction is switched by the interfered line, the method does not provide a large change window as before, the speed is better than the delay condition in the worst case in the previous method, the coupling capacitance is reduced by 50%, the holding time check is better, and the optimal balance of the speed and the holding time is realized. With the same wiring type, wiring length, and repeater, the interconnect line delay improves by 20% without the area and power consumption impact.

Description

Integrated circuit Miller factor offset wiring method

Technical Field

The invention relates to the technical field of microelectronic processes, in particular to a wiring method of an integrated circuit, and particularly relates to a very large scale integrated circuit (VLSI).

Background

In current deep submicron VLSI (very large scale integrated circuit) designs, interconnect delay dominates. This trend will continue as technology develops and circuit complexity increases. In current System On Chip (SOC) designs, interconnect latency accounts for over 60% of the total latency on some critical paths. Therefore, how to reduce the interconnect delay is a key issue to increase the speed of the SOC chip. As technology develops, the line spacing becomes smaller and smaller, and crosstalk between adjacent signals affects the speed through coupling capacitance, which is the miller effect. For example, if the wiring is on a metal4 layer with a width of 0.72um and a space of 1.02um (which is typical in a 130nm technology SOC chip design), the coupling capacitance may account for 50% of the bus capacitance. Therefore, how to reduce the Miller coupling capacitance of the wiring is of great significance in the design of high-speed VLSI circuits.

In current SOC chip designs, a buffer is used for the extra long traces to improve speed and signal integrity. If a certain line in the middle is called an interference source line, two lines adjacent to the interference source line are called interfered lines, and the capacitance between the interfered lines and the interference source line is called Ccp. In the worst case, the victim line on both sides will switch to the opposite direction of the aggressor line, the coupling capacitance will double to 2Ccp, and the signal propagation will slow down because more time is needed to charge the coupling capacitance. This is a particular manifestation of the miller effect, as shown in fig. 1. For the best case of speed, the two victim lines will switch to the same direction as the aggressor line and the coupling capacitance will decrease to 0. But this will be the worst case for the hold time check, as shown in fig. 2. Thus, in current approaches, it is necessary to design for both worst case delay and worst case hold time scenarios to balance speed and hold time checks.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides the integrated circuit Miller factor offset wiring method which has simple implementation structure scheme, utilizes the matching of the phase inverter and the buffer, can reduce the coupling capacitance by 50 percent and realizes the balance of speed and holding time.

In order to solve the technical problems, the invention adopts the following technical scheme: a miller factor cancellation routing method for an integrated circuit, comprising a plurality of nets connected between devices on the integrated circuit, the method comprising: the method is realized by the following steps of,

s1, selecting at least one network as the interfered line, using two adjacent networks at two sides of the interfered line as the interference source line, respectively, the coupling capacitance between the interfered line and the interference source line is Ccp;

s2, arranging M (such as 3) buffers on the interfered line in a spaced mode, and dividing the interfered line into M +1 conducting wire segments by the M buffers;

s3, setting N buffers and 1 or 2 inverters on the two interference source lines, where the inverters and the buffers are set at intervals, and the number of the buffers and the inverters on the two interference source lines is the same (for example, 2 buffers +1 inverter, or 1 buffer +2 inverters), where N is 1 or 2 smaller than M, so that the total number of the buffers and the inverters on any interference source line is the same as the number of the buffers on the interfered line, and the positions of the buffers and the inverters on the interference source line and the buffers on the interfered line are aligned one by one to form a non-staggered arrangement structure;

wherein M is more than or equal to 3, N is more than or equal to 1, and M, N are all natural numbers.

Preferably, N buffers and 2 inverters are arranged on the two interference source lines, 1 buffer is arranged between the 2 inverters, and N +2 buffers are arranged on the interfered line, so that the interfered line and the interference source line are respectively divided into N +3 conductor segments.

Or, N buffers and 1 inverter are respectively arranged on the two interference source lines, the 1 inverter is arranged between the buffers, and the interfered line is provided with N +1 buffers, so that the interfered line and the interference source line are respectively divided into N +2 conductor segments.

In an application scenario, when the signal direction of the interfered line and the signal directions of the two interference source lines are switched in opposite directions, the average coupling capacitance between the interference source line and the interfered line is reduced from 2Ccp to 1Ccp by the method.

In another application scenario, the signal direction of the interference source line and the signal directions of the two interfered lines are switched towards the same direction, so that the coupling capacitance between the interfered line and the interference source line is increased from 0 to 1 Ccp.

The lengths of the aggressor and victim lines can be typically on the order of millimeters or centimeters in deep sub-micron integrated circuit processes.

According to the invention, after a line is determined as an interfered line, two adjacent lines are taken as interference source lines, and one or two buffers in the interference source lines are replaced by the phase inverter on the basis that the buffers are arranged in each network, so that the polarities of adjacent signals are switched, the coupling capacitance generated by the adjacent signals can be reduced, and the total delay is reduced. If the interfered line signal and the interfering source line signal are in the same conversion, the Miller effect Miller factor is 0, and no coupling capacitance is generated. If the victim line signal and the aggressor line signal are in opposite transition states, the Miller effect Miller factor is 2, which is the worst case for routing. However, since there is always half of the wires without miller effect, the total wire miller factor will be reduced by half, thus having an 1/2 capacitance advantage, which in the worst case will significantly improve the RC dominated path timing in the SOC chip. Therefore, no matter which direction the interfered line is switched, the method does not provide a large change window as before, the speed is better than the delay condition in the worst case in the previous method, the coupling capacitance is reduced by 50%, the holding time check is better, and the optimal balance of the speed and the holding time is realized. With the same wiring type, wiring length, and repeater, the interconnect line delay improves by 20% without the area and power consumption impact.

Drawings

FIG. 1 is a worst-case delay scenario for a prior art buffer scheme, in which the signal direction of two aggressor lines is opposite to the signal direction of a victim line (e.g., both aggressor lines are in a level-up direction, and the victim line is in a level-down direction);

fig. 2 is a fastest delay scenario and a worst case circuit holding scenario in a conventional buffer scheme, where the signal directions of two aggressor lines and the victim line are the same (for example, both the aggressor lines and the victim line are in a level-up direction);

both fig. 3 and fig. 4 are the case where two inverters are inserted, and the total Ccp is reduced to half of the worst case regardless of whether the signal direction of the victim line is the same or opposite to the switching direction of the disturber line; in fig. 3, both the interfering source lines are in the level-up direction, and the interfered line is in the level-down direction; in FIG. 4, both the victim network and the two interfering source lines are in the rising direction of the level;

fig. 5 and 6 show that in the case of inserting an inverter, the total Ccp is reduced to half of the worst case, regardless of whether the signal direction of the victim line is the same or opposite to the switching direction of the disturber line; in fig. 5, both the interfering source lines are in the level-up direction, and the interfered line is in the level-down direction;

in FIG. 6, the victim network and the two disturber lines are both in the rising direction.

Detailed Description

The method for realizing the scheme has various methods, and the elimination of the coupling capacitance of the whole path can be realized only by balancing the rising and the falling of the signal level of each segment, and the polarity is kept consistent. For buses with even number of segments, such as 3 buffers and 4 conductor segments, 2 inverters may be used on each aggressor source line without using an inverter on the victim line between the two nets to keep the polarity unchanged as shown in fig. 3 and 4. With the advantage of polarity inversion, more time can be saved, and an inverter can be used in the middle, as shown in fig. 5 and 6. The same can be done for buses with odd segments, e.g. 4 buffers and 5 conductor segments, but due to the number of odd conductor segments only a 40% cancellation of the coupling capacitance can be achieved in the end.

The scheme of arranging two inverters on the buffer chain can keep the output polarity unchanged. Whether the victim line is switched in the same direction or in the opposite direction as the aggressor line, the coupling capacitance can be reduced by 50% from the worst case, as shown in fig. 3 and 4. The scheme of using one inverter is implemented in the case that the lower-stage circuit can be further optimized to accept the inverted signal, and only one inverter can be implemented to reduce the coupling capacitance by 50%, as shown in fig. 5 and 6.

The present invention has been described in detail, and it should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Claims

1. A miller factor cancellation routing method for an integrated circuit, comprising a plurality of nets connected between devices on the integrated circuit, the method comprising: the method is realized by the following steps of,

s2, arranging M buffers on the interfered line in a mode of having intervals, and dividing the interfered line into M +1 conducting wire segments by the M buffers;

s3, arranging N buffers and 1 or 2 inverters on two interference source lines, wherein the inverters and the buffers are arranged at intervals, the number of the buffers and the number of the inverters on the two interference source lines are respectively the same, N is 1 or 2 less than M, so that the total number of the buffers and the inverters on any interference source line is the same as the number of the buffers on an interfered line, and the positions of the buffers and the inverters on the interference source line and the buffers on the interfered line are aligned one by one to form a non-staggered arrangement structure;

2. The integrated circuit miller factor cancellation routing method of claim 1, wherein: n buffers and 2 inverters are arranged on two interference source lines, 1 buffer is arranged between 2 inverters, and N +2 buffers are arranged on an interfered line, so that the interfered line and the interference source line are respectively divided into N +3 conductor segments.

3. The integrated circuit miller factor cancellation routing method of claim 1, wherein: n buffers and 1 inverter are arranged on the two interference source lines, the 1 inverter is arranged between the buffers, and the interfered line is provided with N +1 buffers, so that the interfered line and the interference source line are respectively divided into N +2 conductor segments.

4. The integrated circuit miller factor cancellation routing method of claim 2, wherein: when the signal direction of the interfered line and the signal direction of the two interference source lines are switched in the opposite direction, the average coupling capacitance between the interference source line and the interfered line is reduced from 2Ccp to 1 Ccp.

5. The integrated circuit miller factor cancellation routing method of claim 2, wherein: the signal direction of the interference source line and the signal directions of the two interfered lines are switched in the same direction, so that the coupling capacitance between the interfered lines and the interference source line is increased from 0 to 1 Ccp.

6. The integrated circuit miller factor cancellation routing method of claim 3, wherein: the signal direction of the interference source line and the signal directions of the two interfered lines are switched in opposite directions, so that the coupling capacitance between the interfered lines and the interference source line is reduced from 2Ccp to 1 Ccp.

7. The integrated circuit miller factor cancellation routing method of claim 3, wherein: the signal direction of the interference source line and the signal directions of the two interfered lines are switched in the same direction, so that the coupling capacitance between the interfered lines and the interference source line is increased from 0 to 1 Ccp.

8. The integrated circuit miller factor cancellation routing method of claim 1, wherein: the lengths of the interference source line and the interfered line are both millimeter magnitude or centimeter magnitude in the deep submicron integrated circuit process.