CN111651282B - Message processing method, message processing device and electronic equipment - Google Patents
Message processing method, message processing device and electronic equipment Download PDFInfo
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- CN111651282B CN111651282B CN202010381742.9A CN202010381742A CN111651282B CN 111651282 B CN111651282 B CN 111651282B CN 202010381742 A CN202010381742 A CN 202010381742A CN 111651282 B CN111651282 B CN 111651282B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
Abstract
The invention discloses a message processing method, a message processing device and electronic equipment, wherein the message processing method is applied to the electronic equipment, the electronic equipment is provided with a multi-core processor and an Ethernet controller, and the message processing method comprises the following steps: acquiring a first message or a second message through a first core in a multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the Ethernet controller; when the first message is obtained, transmitting the first message to the Ethernet controller through the first kernel, and triggering the Ethernet controller to send the first message to a receiving device corresponding to the first message; and when the second message is acquired, distributing the second message to one of all kernels of the multi-core processor through the first kernel for receiving processing.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a message processing method, a message processing apparatus, and an electronic device.
Background
The use of a single ethernet controller by a multi-core processor may cause multi-core contention, and multiple cores in the multi-core processor cannot simultaneously access the ethernet controller, which may result in failure to process ethernet packets in parallel, and may even cause system crash.
Disclosure of Invention
In view of this, embodiments of the present invention are intended to provide a message processing method, a message processing apparatus, and an electronic device, so as to solve the problem in the related art that multiple cores in a multi-core processor cannot access an ethernet controller simultaneously, so that ethernet messages cannot be processed in parallel.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a message processing method, which is applied to electronic equipment; the electronic device is provided with a multi-core processor and an Ethernet controller; the message processing method comprises the following steps:
acquiring a first message or a second message through a first core in the multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the ethernet controller;
when the first message is obtained, transmitting the first message to the Ethernet controller through the first kernel, and triggering the Ethernet controller to send the first message to a receiving device corresponding to the first message;
and when the second message is acquired, distributing the second message to one of all kernels of the multi-core processor through the first kernel for receiving processing.
In the foregoing solution, when the first packet is acquired by the first core in the multi-core processor, the packet processing method further includes:
the first kernel acquires a first inter-kernel interrupt signal; the first inter-core interrupt signal is sent out by a second core which generates the first message;
the first kernel reads the first message from a first shared memory area based on the first inter-kernel interrupt signal; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
In the foregoing solution, when the first packet is obtained by the first core in the multi-core processor, the packet processing method further includes:
the first kernel scans the shared memory of the multi-core processor based on a set scanning period;
under the condition that a first message is scanned to be stored in a first shared memory area of the shared memory, reading the first message from the first shared memory area; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
In the foregoing solution, the allocating, by the first core, the second packet to one of all cores of the multicore processor for reception processing includes:
determining a second kernel corresponding to the data type of the message data in the second message through the first kernel based on the set corresponding relation between the data type and the kernel;
and writing the second message into the determined shared memory area corresponding to the second kernel.
In the foregoing solution, when the second packet is written into the shared memory area corresponding to the second core, the packet processing method further includes:
sending a second inter-core interrupt signal to the determined second core through the first core; and the second inter-core interrupt signal is used for informing the determined second core to read a second message from the corresponding shared memory area.
In the foregoing solution, when the first core determines the second core corresponding to the data type of the packet data in the second packet, the packet processing method further includes:
and reading the data type of the message data in the second message from a preset field in the second message through the first kernel.
In the above scheme, the shared memory region corresponding to each second core includes a message receiving buffer and a message sending buffer, where the message receiving buffer is used to store a second message written by the first core, and the message sending buffer is used to store a first message to be sent written by the second core.
An embodiment of the present invention further provides a packet processing apparatus, including:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a first message or a second message through a first kernel in the multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the ethernet controller;
a first packet processing unit, configured to transmit the first packet to the ethernet controller through the first kernel when the first packet is obtained, and trigger the ethernet controller to send the first packet to a receiving device corresponding to the first packet;
and the second message processing unit is used for distributing the second message to one of all the cores of the multi-core processor for receiving processing through the first core when the second message is acquired.
An embodiment of the present invention further provides an electronic device, including: a multi-core processor and a memory for storing a computer program capable of running on the processor,
the multi-core processor is used for executing any one of the steps of the message processing method when the computer program is run.
An embodiment of the present invention further provides a storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of any one of the message processing methods described above.
In the embodiment of the invention, a first message and a second message are obtained through a first kernel in a multi-core processor, wherein the first message is a message to be sent generated by any second kernel in at least one second kernel in the multi-core processor; the second message is a message which is received by the Ethernet controller and is sent to the electronic equipment; when a first message is acquired, transmitting the first message to an Ethernet controller through a first kernel, and triggering the Ethernet controller to send the first message to a receiving device corresponding to the first message; and when the second message is acquired, the second message is distributed to one of all kernels of the multi-core processor for receiving processing through the first kernel. Because only the first core in the multi-core processor has the authority of accessing the Ethernet controller, the first core is responsible for forwarding the first messages generated by all the second cores to the Ethernet controller and distributing the second messages to the second cores, so that the problem that the messages cannot be processed in parallel due to the fact that the multiple cores in the multi-core processor access the Ethernet controller simultaneously and cause multi-core competition can be avoided.
Drawings
Fig. 1 is a schematic flow chart of a message processing method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a component structure of a multi-core processor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a composition structure of a message processing apparatus according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a hardware component structure of an electronic device according to an embodiment of the present invention.
Detailed Description
A Multi-core processor refers to the integration of two or more complete compute engines (cores) in one processor. Multi-core processors typically improve program performance in the multi-core processor by parallelizing the program. For example, a plurality of cores in the multi-core processor can run the message processing program in parallel, so that the performance of the message processing program can be improved, and the message processing efficiency is improved.
In the process of running the message processing program in parallel by the multi-core processor, each core may access the ethernet controller (i.e., the network card), so that multi-core contention may be caused by using a single ethernet controller by the multi-core processor, and the ethernet messages cannot be processed in parallel because a plurality of cores in the multi-core processor cannot access the ethernet controller at the same time, and even a system crash may be caused.
In order to solve the above problem, the present invention provides a message processing method, where a first core obtains a first message and a second message, and when the first message is obtained, the first core transmits the first message to an ethernet controller, and triggers the ethernet controller to send the first message to a receiving device corresponding to the first message; and when the second message is acquired, distributing the second message to one of all the cores of the multi-core processor for receiving processing through the first core. Because only the first core in the multi-core processor has the authority of accessing the Ethernet controller, the first core is responsible for forwarding the first messages generated by all the second cores to the Ethernet controller and distributing the second messages to all the second cores, the problem that the messages cannot be processed in parallel due to the fact that multiple cores in the multi-core processor access the Ethernet controller simultaneously and multi-core competition is caused can be avoided.
The technical solution of the present invention is further described in detail with reference to the drawings and the specific embodiments of the specification.
Fig. 1 is a flowchart illustrating a message processing method according to an embodiment of the present invention. The message processing method provided by the embodiment is applied to electronic equipment. An electronic device is configured with a multi-core processor and an ethernet controller. The number of the multi-core processors may be one or more. Electronic devices include, but are not limited to, electrical devices. Referring to fig. 1, the message processing method in this embodiment includes the following steps:
s101: acquiring a first message or a second message through a first core in the multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the ethernet controller.
The electronic equipment acquires an Ethernet configuration request triggered by a user, performs network information configuration on the Ethernet controller through a first core of the multi-core processor, and establishes communication connection between the first core of the multi-core processor and the Ethernet controller. The network information includes an Internet Protocol Address (IP Address) of the ethernet controller, a subnet mask, a gateway Address, and the like. The first core is any one of a plurality of cores in a multi-core processor.
The electronic device acquires a first message to be sent through a first core of the multi-core processor or receives a second message sent by other electronic devices through the Ethernet controller under the condition that the communication connection between the first core of the multi-core processor and the Ethernet controller is successfully established. Here, the first message is a message to be sent, which is generated by any one of at least one second core in a multi-core processor of the electronic device. The second core is any one of the cores of the multi-core processor except the first core.
It should be noted that, among the multiple cores of the multi-core processor, only the first core has an authority to directly access the ethernet controller, and the second core needs to perform data interaction with the ethernet controller through the first core, so as to forward, through the first core, the first packet generated by the second core, and allocate, by the first core, the second packet sent to the electronic device by the other device to the second core.
It should be noted that the message processing method in the present application may be applicable to electronic devices in peer-to-peer communication, and also applicable to electronic devices in non-peer-to-peer communication. In an application scenario of peer-to-peer communication, the electronic device may not include device identification information of the sending end and the receiving end in a message transmitted between the electronic devices, and in an application scenario of non-peer-to-peer communication, the electronic device needs to include the device identification information of the sending end and the receiving end in a message transmitted between the electronic devices. The device identification information may be a Media Access Control (MAC) address, or may be unique identification information of the electronic device.
S102: when the first message is obtained, the first message is transmitted to the ethernet controller through the first kernel, and the ethernet controller is triggered to send the first message to a receiving device corresponding to the first message.
The electronic device obtains a first message generated by a second kernel through a first kernel in the multi-core processor, forwards the first message to the Ethernet controller through the first kernel in the multi-core processor, and triggers the Ethernet controller to send the first message to a receiving device corresponding to the first message when receiving the first message. The receiving device is another electronic device. The first message may be generated by the second kernel and then sent to the first kernel, or may be obtained by the first kernel from a shared memory of the multicore processor.
S103: and when the second message is acquired, distributing the second message to one of all the cores of the multi-core processor for receiving processing through the first core.
After the electronic device obtains the second message through the first kernel in the multi-core processor, the second message is distributed to the first kernel or the second kernel through the first kernel, so that the first kernel or the second kernel can analyze the second message, message data contained in the second message is obtained, and the message data is processed based on a processing flow corresponding to the message data to obtain a message processing result.
In one embodiment, the electronic device counts the resource occupancy rate of each core through a first core of the multi-core processor, and allocates the second packet to one of all the cores of the multi-core processor for receiving processing based on the resource occupancy rate of each core. For example, the second packet is preferentially allocated to the kernel with a low resource occupancy rate for processing.
In one embodiment, the electronic device counts the number of unprocessed messages corresponding to each core through a first core of the multi-core processor, and preferentially selects a core with a smaller number of unprocessed messages from the plurality of cores as a target core for processing the first message based on the number.
In one embodiment, the electronic device extracts, from the second packet, information describing a kernel for processing the second packet through the first kernel of the multi-core processor, and determines, according to the information describing the kernel for processing the second packet, a target kernel for processing the second packet. The information describing the kernel for processing the first packet may be a kernel identifier, or a data type to which the packet data belongs. The target core is one of all cores in the multi-core processor.
For example, when the determined target kernel is the first kernel, the electronic device parses the first message through the first kernel, obtains message data included in the first message, and processes the message data based on a preset operation corresponding to the message data. In practical application, when the message data is sampling data, the first kernel may store the sampling data, or classify, analyze, and the like the sampling data according to a processing flow corresponding to the sampling data.
When the determined target kernel is the second kernel, the electronic equipment sends a second message to the determined second kernel through the first kernel so that the second kernel can process the second message; or, the electronic device stores the second message to the shared memory through the first kernel, notifies the determined second kernel to process to obtain the second message from the shared memory, and processes the second message.
In this embodiment, a first message and a second message are obtained through a first core in a multi-core processor, where the first message is a to-be-sent message generated by any one of at least one second core in the multi-core processor; the second message is a message which is received by the Ethernet controller and is sent to the electronic equipment; when a first message is obtained, transmitting the first message to an Ethernet controller through a first kernel, and triggering the Ethernet controller to send the first message to a receiving device corresponding to the first message; and when the second message is acquired, the second message is distributed to one of all kernels of the multi-core processor for receiving processing through the first kernel. Because only the first core in the multi-core processor has the authority of accessing the Ethernet controller, the first core is responsible for forwarding the first messages generated by all the second cores to the Ethernet controller and distributing the second messages for all the second cores, the problem that the messages cannot be processed in parallel due to the fact that multiple cores in the multi-core processor access the Ethernet controller simultaneously and multi-core competition is caused can be avoided, and through the mode, the multiple cores in the multi-core processor can process the messages in parallel, and message processing efficiency is improved.
In an embodiment, in order to obtain the first packet in time, correspondingly, when the first packet is obtained by the first core in the multi-core processor, the packet processing method further includes:
the first kernel acquires a first inter-kernel interrupt signal; the first inter-core interrupt signal is sent out by a second core which generates the first message;
the first kernel reads the first message from a first shared memory area based on the first inter-kernel interrupt signal; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
In practical application, a second core of a multi-core processor of the electronic device generates a first message, and the first message is stored in a first shared memory area corresponding to the second core. The second core then sends a first inter-core interrupt signal to the first core. The first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
The electronic equipment acquires a first inter-core interrupt signal triggered by a second core through a first core of the multi-core processor, responds to the first inter-core interrupt signal through the first core of the multi-core processor, and reads a first message from a first shared memory area corresponding to the second core triggering the first inter-core interrupt signal.
It should be noted that, before the electronic device processes the message, a shared memory area may be allocated in the shared memory for each second core, and the shared memory area corresponding to each second core is used to store the message to be processed and the message to be sent that are received via the ethernet controller. Because the first kernel can directly access the ethernet controller, the received to-be-processed message and the message to be sent corresponding to the first kernel can be stored in the first kernel without being stored in the shared memory, so that the shared memory area corresponding to the first kernel may not be set. Fig. 2 is a schematic diagram of a composition structure of a multicore processor according to an embodiment of the present invention. As shown in fig. 2, the multi-core processor has N cores, where the core 1 is a first core, the cores 2 to N are second cores, and in the shared memory, a corresponding shared memory area is set for each second core.
It should be noted that, in order to facilitate the first kernel to obtain the first packet to be sent from the shared memory or facilitate the second kernel to obtain the second packet to be processed from the shared memory, so as to accelerate the packet processing speed, the shared memory region corresponding to each second kernel may include at least one packet receiving buffer region and at least one packet sending buffer region, where the packet sending buffer region is used to store the first packet to be sent written into the shared memory region by the second kernel, and the packet receiving buffer region is used to store the second packet written into the first kernel.
In practical application, after a second core of a multi-core processor of an electronic device generates a first message, a message sending buffer area corresponding to the second core which generates the first message is determined in a shared memory of the multi-core processor, and the first message is written into the determined message sending buffer area. Then, a first kernel in a multi-core processor of the electronic device acquires a first inter-kernel interrupt signal triggered by a second kernel, and the first kernel reads a first message from a message sending buffer corresponding to the second kernel which triggers the first inter-kernel interrupt signal.
It can be understood that, when the second core of the multi-core processor stores the first packet in the corresponding packet sending buffer, the sending frame number may be allocated to the first packet based on a predetermined frame number coding rule, and the sending frame number corresponding to the first packet and the first packet (or the storage address of the first packet) are written in the determined packet sending buffer in an associated manner, so that when the first core of the multi-core processor of the electronic device obtains the first packet from the packet sending buffer, the first packet corresponding to the sending frame number may be obtained in the order from small to large based on the sending frame number in the packet sending buffer corresponding to the second core, so as to avoid the first packet from being missed by the first core. For the same second core, the sending frame sequence numbers allocated by the second core at different times are different, and the newly allocated sending frame sequence number is the largest. For different second cores, the transmission frame numbers respectively allocated at the same time may be the same or different.
It should be noted that the second core of the multi-core processor may also write information for describing the data length of the packet data of the first packet into the packet sending buffer in association with the first packet or the storage address of the first packet, so that when the first core of the multi-core processor obtains the first packet from the packet sending buffer, it is checked whether the complete first packet has been obtained by using the information for describing the data length of the packet data of the first packet.
In one embodiment, when the first packet is acquired by the first core in the multi-core processor, the packet processing method further includes:
the first kernel scans the shared memory of the multi-core processor based on a set scanning period;
under the condition that a first message is scanned to be stored in a first shared memory area of the shared memory, reading the first message from the first shared memory area; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
Here, a first core of a multi-core processor of the electronic device scans a shared memory of the multi-core processor according to a predetermined scanning period to detect whether a first packet exists in the shared memory of the multi-core processor. The preset scanning period can be set according to actual requirements; under the condition that a first message is stored in a first shared memory area of the shared memory in a scanning mode, the first message is read from the first shared memory area.
When the shared memory area corresponding to each second core may include a message receiving buffer and a message sending buffer, the first core of the multi-core processor of the electronic device scans the message sending buffer corresponding to each second core one by one according to a predetermined scanning period to detect whether the first message exists in the shared memory of the multi-core processor.
In an embodiment, in order to quickly and accurately allocate a packet, when the second packet is allocated to one of all cores of the multicore processor by the first core for receiving and processing, the packet processing method further includes:
determining a second kernel corresponding to the data type of the message data in the second message through the first kernel based on the set corresponding relation between the data type and the kernel; and writing the second message into the determined shared memory area corresponding to the second kernel.
When the electronic device acquires the second message, extracting information for describing the data type of the message data from the second message through the first kernel, and determining the data type of the message data in the second message according to the information for describing the data type of the message data; and acquiring a set corresponding relationship between the data type and the kernel, determining a second kernel corresponding to the data type of the message data included in the second message based on the set corresponding relationship between the data type and the kernel, and writing the second message into the determined shared memory area corresponding to the second kernel.
The second cores of the multi-core processor in the electronic device may scan the shared memory region (or the message receiving buffer) corresponding to each second core according to a predetermined scanning period, and any one of the second cores acquires the second message from the corresponding shared memory region (or the message receiving buffer) when the corresponding shared memory region (or the message receiving buffer) stores the second message.
The electronic device stores a set corresponding relationship between the data type and the kernel, and the set corresponding relationship between the data type and the kernel can be stored in the first kernel or a shared memory of the multi-core processor. The data types include, but are not limited to, sampled data, control information, measured data, and the like. One kernel may be used to process message data of one data type, and may also be used to process message data of different data types.
It can be understood that, when the first core of the multi-core processor writes the second packet into the corresponding packet sending buffer, the first core may allocate a receiving frame number to the second packet based on a predetermined frame number coding rule, and write the receiving frame number corresponding to the second packet and the second packet (or the storage address of the second packet) into the determined packet receiving buffer in an associated manner, so that when the second core of the multi-core processor of the electronic device obtains the second packet from the packet receiving buffer, the second core may obtain the second packets corresponding to the receiving frame numbers in the packet receiving buffer in the order from small to large based on the receiving frame number corresponding to the second core, so as to avoid the second core from processing the second packet. The first kernel distributes different receiving frame serial numbers for the same second kernel at different time, and the newly distributed receiving frame serial number is the largest. The sending frame sequence numbers allocated by the first kernel to the different second kernels may be the same or different.
In an embodiment, the information describing the data type of the message data in the first message and the second message may exist in the setting field. When the second core corresponding to the data type of the message data in the second message is determined by the first core, the message processing method further includes:
and reading the data type of the message data in the second message from the set field in the second message through the first kernel.
Here, the first packet and the second packet are obtained by encapsulating packet data based on a private protocol, and a setting field for describing a data type to which the packet data belongs is defined in the private protocol. In practical applications, because the fields in the ethernet packet usually include: a destination address, a source address, a TYPE field (TYPE), a Length field (Length), and message data; therefore, the predetermined field for describing the data type to which the message data belongs is a "type field" or a "length field". That is, the data type to which the message data belongs is described by using a "type field" or a "length field".
In an embodiment, when the second packet is written into the shared memory area corresponding to the second kernel, the packet processing method further includes:
and sending a second inter-core interrupt signal to the determined second core through the first core, wherein the second inter-core interrupt signal is used for informing the determined second core to read a second message from the corresponding shared memory area.
Here, when the electronic device writes the second packet into the shared memory region corresponding to the second core through the first core of the multi-core processor, the electronic device may further send the second inter-core interrupt signal to the second core through the first core, so that when the second core of the multi-core processor of the electronic device obtains the second inter-core interrupt signal, the second packet is read from the shared memory region corresponding to the second core that sends the second inter-core interrupt signal and is processed.
It should be noted that, in this embodiment, because the first core needs to analyze the information corresponding to the set field to determine the data type of the packet data in the first packet, after determining the target core that processes the first packet, the first core may store the packet data in the first packet to the packet sending buffer corresponding to the target core, so that the target core directly processes the packet data, and the target core does not need to analyze the predetermined field of the first packet, which may save time consumed by the target core for analyzing the predetermined field.
In order to implement the method according to the embodiment of the present invention, an embodiment of the present invention further provides a message processing apparatus, which is disposed on an electronic device, and as shown in fig. 3, the message processing apparatus includes:
an obtaining unit 301, configured to obtain a first packet or a second packet through a first core in the multicore processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message received by the ethernet controller and sent to the first core electronic device of the electronic device;
a first packet processing unit 302, configured to transmit the first packet to the ethernet controller through the first core when the first packet is obtained, and trigger the ethernet controller to send the first packet to a receiving device corresponding to the first packet;
a second packet processing unit 303, configured to, when the second packet is obtained, allocate the second packet to one of all cores of the multi-core processor through the first core to perform receiving processing.
In an embodiment, when acquiring the first packet by the first core in the multicore processor, the acquiring unit 301 is further configured to:
the first kernel acquires a first inter-kernel interrupt signal; the first inter-core interrupt signal is sent out by a second core which generates the first message;
the first kernel reads the first message from a first shared memory area based on the first inter-kernel interrupt signal; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
In an embodiment, when acquiring the first packet by the first core in the multicore processor, the acquiring unit 301 is further configured to:
the first kernel scans the shared memory of the multi-core processor based on a set scanning period;
under the condition that the first message is scanned to be stored in a first shared memory area of the shared memory, reading the first message from the first shared memory area; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
In an embodiment, the second packet processing unit 303 is configured to:
determining a second kernel corresponding to the data type of the message data in the second message through the first kernel based on the set corresponding relation between the data type and the kernel;
and writing the second message into the determined shared memory area corresponding to the second kernel.
In an embodiment, the second packet processing unit 303 is further configured to: and sending a second inter-core interrupt signal to the determined second core through the first core, wherein the second inter-core interrupt signal is used for informing the determined second core to read a second message from the corresponding shared memory area.
In an embodiment, when determining, by the first core, a second core corresponding to a data type of message data in the second message, the second message processing unit 303 is further configured to: and reading the data type of the message data in the second message from a preset field in the second message through the first kernel.
In an embodiment, the shared memory region corresponding to each second core includes a message receiving buffer and a message sending buffer, where the message receiving buffer is configured to store a second message written by the first core, and the message sending buffer is configured to store a first message to be sent written by the second core.
It should be noted that: in the message processing apparatus provided in the foregoing embodiment, when processing a message, the division of each program module is merely used as an example, and in practical applications, the processing may be allocated to be completed by different program modules according to needs, that is, the internal structure of the message processing apparatus is divided into different program modules, so as to complete all or part of the above-described processing. In addition, the message processing apparatus and the message processing method provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in detail in the method embodiments and are not described herein again.
Based on the hardware implementation of the program module, in order to implement the method according to the embodiment of the present invention, an embodiment of the present invention further provides an electronic device. Fig. 4 is a schematic diagram of a hardware composition structure of an electronic device according to an embodiment of the present invention, and as shown in fig. 4, the electronic device includes:
the Ethernet controller 1 can perform information interaction with other devices such as other electronic devices and the like;
and the processor 2 is connected with the ethernet controller 1 to realize information interaction with other devices, and is used for executing the message processing method provided by one or more technical schemes when running a computer program. And the computer program is stored on the memory 3. The processor 2 is a multi-core processor.
In practice, of course, the various components in the electronic device are coupled together by the bus system 4. It will be appreciated that the bus system 4 is used to enable connection communication between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. For clarity of illustration, however, the various buses are labeled as bus system 4 in fig. 4.
The memory 3 in the embodiment of the present invention is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.
It will be appreciated that the memory 3 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The memory 2 described in the embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The method disclosed by the above embodiment of the present invention may be applied to the processor 2, or may be implemented by the processor 2. The processor 2 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by instructions in the form of hardware integrated logic circuits or software in the processor 2. The processor 2 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, or the like. The processor 2 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed by the embodiment of the invention can be directly implemented by a hardware decoding processor, or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium located in the memory 3, and the processor 2 reads the program in the memory 3 and in combination with its hardware performs the steps of the aforementioned method.
When the processor 2 executes the program, the process corresponding to the multi-core processor in each method according to the embodiment of the present invention is realized, and for brevity, no further description is given here.
In an exemplary embodiment, the embodiment of the present invention further provides a storage medium, specifically a computer-readable storage medium, for example, including a memory 3 storing a computer program, where the computer program is executable by a processor 2 to perform the steps in the foregoing embodiment corresponding to fig. 1. The computer readable storage medium may be Memory such as FRAM, ROM, PROM, EPROM, EEPROM, Flash Memory, magnetic surface Memory, optical disk, or CD-ROM.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The features disclosed in the several product embodiments presented in this application can be combined arbitrarily, without conflict, to arrive at new product embodiments.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A message processing method is characterized in that the method is applied to electronic equipment; the electronic device is provided with a multi-core processor and an Ethernet controller; the message processing method comprises the following steps:
acquiring a first message or a second message through a first core in the multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the ethernet controller;
when the first message is obtained, transmitting the first message to the Ethernet controller through the first kernel, and triggering the Ethernet controller to send the first message to a receiving device corresponding to the first message;
when the second message is obtained, the first kernel distributes the second message to one kernel of all kernels of the multi-core processor for receiving processing;
when the first message is acquired by the first core in the multi-core processor, the message processing method further comprises the following steps:
the first kernel acquires a first inter-kernel interrupt signal; the first inter-core interrupt signal is sent out by a second core which generates the first message;
the first kernel reads the first message from a first shared memory area based on the first inter-kernel interrupt signal; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
2. The message processing method according to claim 1, wherein when the first message is obtained by a first core in the multi-core processor, the message processing method further comprises:
the first kernel scans the shared memory of the multi-core processor based on a set scanning period;
under the condition that the first message is scanned to be stored in a first shared memory area of the shared memory, reading the first message from the first shared memory area; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
3. The message processing method according to claim 1, wherein the allocating, by the first core, the second message to one of all cores of the multicore processor for reception processing comprises:
determining a second kernel corresponding to the data type of the message data in the second message through the first kernel based on the set corresponding relation between the data type and the kernel;
and writing the second message into the determined shared memory area corresponding to the second kernel.
4. The message processing method according to claim 3, wherein when the second message is written into the shared memory region corresponding to the second kernel, the message processing method further comprises:
sending a second inter-core interrupt signal to the determined second core through the first core; and the second inter-core interrupt signal is used for informing the determined second core to read a second message from the corresponding shared memory area.
5. The packet processing method according to claim 3, wherein when the first core determines a second core corresponding to a data type of packet data in the second packet, the packet processing method further includes:
and reading the data type of the message data in the second message from the set field in the second message through the first kernel.
6. The message processing method according to any of claims 2 to 3, wherein the shared memory region corresponding to each of the second cores includes a message receiving buffer and a message sending buffer, the message receiving buffer is configured to store the second message written by the first core, and the message sending buffer is configured to store the first message to be sent written by the second core.
7. A message processing apparatus, comprising:
the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a first message or a second message through a first kernel in a multi-core processor; the first message is a message to be sent generated by any one of at least one second kernel in the multi-core processor; the second message is a message sent to the electronic device and received by the Ethernet controller, and the message is a first core electronic device;
a first packet processing unit, configured to transmit the first packet to the ethernet controller through the first kernel when the first packet is obtained, and trigger the ethernet controller to send the first packet to a receiving device corresponding to the first packet;
the second message processing unit is used for distributing the second message to one of all kernels of the multi-core processor through the first kernel to receive and process when the second message is obtained;
the obtaining unit is further configured to, when obtaining the first packet through the first core in the multi-core processor:
the first kernel acquires a first inter-kernel interrupt signal; the first inter-core interrupt signal is sent out by a second core which generates the first message;
the first kernel reads the first message from a first shared memory area based on the first inter-kernel interrupt signal; the first shared memory area is an area corresponding to the second kernel generating the first message in the shared memory of the multi-core processor.
8. An electronic device, comprising: a multi-core processor and a memory for storing a computer program capable of running on the processor,
wherein the multi-core processor is configured to execute the steps of the message processing method according to any one of claims 1 to 6 when running the computer program.
9. A storage medium on which a computer program is stored, characterized in that the computer program, when being executed by a processor, carries out the steps of the message processing method according to any one of claims 1 to 6.
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| CN105893320A (en) * | 2016-03-29 | 2016-08-24 | 浙江大学 | Remote task function calling method oriented at multi-core processor |
| CN107046508A (en) * | 2016-02-05 | 2017-08-15 | 华为技术有限公司 | Message method of reseptance and the network equipment |
| CN107547508A (en) * | 2017-06-29 | 2018-01-05 | 新华三信息安全技术有限公司 | A kind of message sending, receiving method, device and the network equipment |
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| CN107046508A (en) * | 2016-02-05 | 2017-08-15 | 华为技术有限公司 | Message method of reseptance and the network equipment |
| CN105893320A (en) * | 2016-03-29 | 2016-08-24 | 浙江大学 | Remote task function calling method oriented at multi-core processor |
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