CN111647866A

CN111647866A - Edge electric field improving structure, carrier plate monomer and carrier plate

Info

Publication number: CN111647866A
Application number: CN202010691071.6A
Authority: CN
Inventors: 肖俊峰; 王锦乐; 张玉前; 庞三凤; 萧圣义
Original assignee: Tongwei Solar Hefei Co Ltd
Current assignee: Tongwei Solar Anhui Co Ltd
Priority date: 2020-07-17
Filing date: 2020-07-17
Publication date: 2020-09-11

Abstract

The invention discloses a fringe electric field improving structure, a carrier plate monomer and a carrier plate, and belongs to the technical field of vacuum coating on the surface of a silicon wafer. The fringe electric field improving structure comprises a plurality of convex parts arranged on the inner side wall of a carrying frame for carrying the silicon wafer. The carrier plate unit comprises a fringe electric field improving structure and a carrying platform arranged below the carrying frame. The carrier plate comprises a plurality of carrier plate monomers, and the carrier plate monomers are distributed on the carrier plate in an array manner. The invention effectively improves the uniformity of the edge electric field of the carrier plate monomer in the coating process and improves the uniformity of the coating thickness of the silicon wafer. The appearance color difference caused by different coating thicknesses is improved. The invention only arranges the convex part on the inner side wall of the carrier plate monomer of the original carrying frame, and has simple integral improved structure and low improved cost. Is beneficial to large-scale production and application.

Description

Edge electric field improving structure, carrier plate monomer and carrier plate

Technical Field

The invention belongs to the technical field of vacuum coating on the surface of a silicon wafer, and particularly relates to an edge electric field improving structure, a carrier plate monomer and a carrier plate.

Background

The vacuum coating technology for the surface of the silicon wafer is widely applied to the production and the manufacture of almost all semiconductor products such as semiconductor devices, integrated circuits, display illumination, photovoltaics, semiconductor photodetectors, semiconductor lasers and the like. For example, the method adopts vacuum coating equipment such as chemical vapor deposition, physical vapor deposition, electron cyclotron resonance plasma deposition, radio frequency sputtering, direct current sputtering and the like, and is used for producing dielectric films such as amorphous silicon films, polycrystalline silicon films, silicon nitride films, silicon oxynitride films, silicon oxide films, TCO transparent conductive films and the like. With the continuous development of the technology, the size of the silicon wafer becomes larger, the integration degree becomes higher, and during film coating, the thickness of the film coating on the edge of the silicon wafer with a larger size is smaller than that of other parts due to the non-uniformity of the edge electric field distribution, and in order to maintain the uniformity of the thickness of the film coating on the edge of the silicon wafer and the appearance thereof, the uniformity of the edge electric field distribution of the carrier plate used by the film coating equipment needs to be improved.

In order to solve the problem of uniformity of electric field distribution at the edge of the carrier plate, chinese patent publication No. CN103811247A discloses a focus ring for plasma etching and a plasma etching apparatus having the same. The focusing ring for plasma etching comprises: a lower ring, a middle ring and an upper ring; wherein the lower ring is made of an insulator resistant to plasma corrosion, such as aluminum oxide and the like; the middle ring is positioned above the lower ring and is made of conductors, such as aluminum and the like; the upper ring is positioned above the middle ring and is made of a semiconductor or an insulator, such as silicon, silicon carbide or quartz. A plasma etching apparatus includes: a stage and a focus ring. The wafer carrying table is used for supporting a wafer to be etched. The stage also acts as a bottom electrode and is connected to the rf source through a dc blocking capacitor C1. In order to prevent the stage from being corroded, the stage is generally in a stepped cylindrical shape, and the diameter of the small-end cylinder of the stage is slightly smaller than that of the wafer. The focusing ring is arranged around the wafer carrier, and the focusing ring is not in contact with the wafer. Typically, due to manufacturing tolerances and thermal expansion requirements, there is a gap of width c between the outer edge of the wafer and the inner side of the focus ring, typically about 1 mm. Optionally, an edge ring is disposed around the large end cylinder of the stage and the focus ring. The edge ring is mainly used for shielding a free electric field generated at the edge of the slide holder and improving the uniformity of plasma on the lower polar plate and the upper polar plate.

According to the scheme, the mode of independently controlling the voltage is adopted by additionally arranging the focusing ring, so that various factors on technical efficiency are unavailable, both the yield and the coating quality cannot be considered, and the multilayer structure additionally arranged with the focusing ring has higher cost expenditure on the structure of a support plate used by coating equipment, particularly a graphite support plate. Therefore, a novel carrier plate suitable for batch production needs to be designed to meet the requirement of coating equipment on the uniformity of the edge electric field of the used carrier plate so as to improve the film forming uniformity of large-size silicon wafers during film coating.

Disclosure of Invention

1. Problems to be solved

The problems that the coating thickness of a silicon wafer is not uniform in the coating process due to the fact that the edge electric field of a carrier plate adopted by existing coating equipment is not uniform, and a focusing ring adopting plasma etching is high in cost and difficult to produce in quantity are solved. The invention provides a fringe electric field improving structure, a carrier plate monomer and a carrier plate. The plurality of the protruding parts are arranged on the inner side wall of the carrying frame, so that the uniformity of an electric field at the edge of the carrying plate is improved, and the non-uniformity of the coating thickness in the coating process is improved.

2. Technical scheme

In order to achieve the purpose, the invention adopts the following technical scheme:

a fringe field improving structure comprises a plurality of protrusions arranged on the inner side wall of a carrying frame for carrying silicon wafers.

Preferably, the protruding parts are in a strip-shaped structure, and the protruding parts are arranged in parallel.

Preferably, the protruding part is arranged along the horizontal direction of the inner side wall, or is arranged along the vertical direction of the inner side wall, or is arranged along the horizontal direction of the inclined inner side wall.

Preferably, the convex parts are arranged in a point array along the inner side wall.

Preferably, the cross-sectional shape of the convex part includes, but is not limited to, a circular arc surface, an isosceles trapezoid.

Preferably, the arc of the arc surface is less than or equal to 180 °.

Preferably, the cross-sectional shape of the convex part includes, but is not limited to, a circular arc surface, an isosceles trapezoid;

preferably, the arc of the arc surface is less than or equal to 180 °.

Preferably, the distance between the side edge of the silicon wafer and the inner side wall of the carrying frame is D1; the distance from the top end of the convex part to the inner side wall is H1; wherein D1 is more than or equal to 2 XH 1.

Preferably, the width or diameter of the contact surface of the convex part and the inner side wall is D2, D1 ≥ 1-1.5 x D2.

Preferably, an arc chamfer is arranged between the inner side wall and the upper top surface of the carrying frame.

A carrier plate monomer, comprising the fringe electric field improving structure of any one of the above.

Preferably, a placing table is arranged below the placing frame, the placing table is used for placing a silicon wafer, and the placing table and the placing frame are in an integrated or split structure.

A carrier plate comprises a plurality of carrier plate monomers, wherein the carrier plate monomers are distributed on the carrier plate in an array manner.

3. Advantageous effects

Compared with the prior art, the invention has the beneficial effects that:

(1) the invention effectively improves the uniformity of the fringe electric field in the film coating process of the carrying frame and the carrying plate and improves the uniformity of the film coating thickness of the silicon wafer by arranging the bulges on the inner side wall of the carrying frame.

(2) The invention improves the inconsistency of the appearance of the coated silicon wafer caused by larger difference of the coating thickness of the silicon wafer by improving the uniformity of the coating thickness of the silicon wafer, namely, the appearance color difference generated by different coating thicknesses of the coated silicon wafer is reduced.

(3) The invention does not make any structural change to the original carrying frame and the carrier plate, only the inner side wall of the original carrying frame is provided with the lug boss, the integral improvement structure is simple, the improvement cost is low, and the invention is beneficial to large-scale production and application.

(4) The bulge part for improving the edge electric field uniformity has a simple structure and is beneficial to production and manufacturing.

(5) The parallel long-strip-shaped or point-shaped array-arranged convex parts can improve the uniformity of the fringe electric field and the stability of the fringe electric field.

(6) The invention limits the distance between the edge of the silicon wafer and the inner side wall of the carrying frame and the height and width of the bulge part, and further improves the uniformity of the edge electric field.

Drawings

FIG. 1 is a schematic structural diagram of a carrier according to the present invention;

FIG. 2 is an enlarged view of the structure of the carrier plate monomer at the A position on the carrier plate according to the present invention;

FIG. 3 is a schematic cross-sectional view of the carrier plate of the present invention along the C-C direction;

FIG. 4 is a partially enlarged view of a portion B of the carrier plate shown in FIG. 3 according to the present invention;

FIG. 5 is a side view of the boss of FIG. 4 of the present invention;

FIGS. 6 (A) - (D) are schematic cross-sectional views of 4 kinds of protrusions in the present invention;

FIG. 7 is a schematic cross-sectional view of the carrier plate in the C-C direction of the vertical bar protrusion at the protrusion part of the present invention;

FIG. 8 is a side view of the boss of FIG. 7 in accordance with the present invention;

FIG. 9 is a top view of the boss of FIG. 7 in accordance with the present invention;

FIG. 10 is a schematic cross-sectional view of a carrier plate in a C-C direction when protrusions are arranged in a dot array according to an embodiment of the present invention;

FIG. 11 is a side view of the boss of FIG. 10 in accordance with the present invention;

reference numbers in the drawings illustrate:

1. a support plate monomer; 11. a mounting frame; 111. an upper top surface; 112. an inner sidewall; 12. a mounting table; 2. a boss portion; 211. the transverse strips are convex; 212 vertical bar projection; 22 point-shaped arc bulges; 3. a silicon wafer; 4. rounding off; 5. and (5) reinforcing ribs.

Detailed Description

The invention is further described with reference to specific examples.

Example 1

As shown in fig. 1, fig. 2 and fig. 3, the present invention provides a fringe electric field improving structure, wherein a plurality of protrusions 2 are disposed on an inner sidewall 112 of a carrier frame 11 for carrying a silicon wafer 3, and the number of the plurality of protrusions 2 may be one or more; in the embodiment, the number of the protrusions 2 is N, wherein N is more than or equal to 1. The convex parts 2 change the smooth structure of the inner side wall 112, according to the principle of point discharge of the conductive material, the distribution mode of electric field lines on the inner side wall 112 of the original carrying frame 11 can be changed by the plurality of convex parts 2, the electric field lines are concentrated on the top ends of the plurality of convex parts 2, the effect of improving the uniformity of the electric field at the edge of the carrying frame 11 and the electric field at the central area of the carrying frame 11 in the plasma discharge coating process is achieved, and therefore the uniformity of the coating thickness of the silicon wafer 3 is improved.

The shapes of the silicon wafer 3 and the carrying frame 11 are not limited in this embodiment, and if the silicon wafer 3 is circular, the carrying frame 11 is a circular ring shape surrounding the silicon wafer 3; if the silicon wafer 3 is a square, the placing frame 11 is a square surrounding the silicon wafer 3; if the silicon wafer 3 has another shape, the placement frame 11 is adjusted according to the shape of the silicon wafer 3 and is disposed around the silicon wafer 3.

If the carrying frame 11 is circular, the inner side wall 112 of the carrying frame 11 is a circular ring surface, and the plurality of convex parts 2 are arranged on the circular ring surface of the inner side wall 112 of the carrying frame 11; if the placing frame 11 is a quadrangle, the inner side wall of the placing frame 11 has four faces, and a plurality of protrusions 2 may be provided on one, two, three, or four of the faces.

Example 2

As shown in fig. 3, 5 and 8, this embodiment is substantially the same as embodiment 1, and in addition to embodiment 1, the protruding portions 2 disposed on the inner side wall 112 of the placing frame 11 are in a strip-shaped structure, and the protruding portions 2 are disposed in parallel. The mutually parallel arranged convex parts 2 can ensure that the electric field lines are distributed more uniformly, thereby achieving better uniformity of the thickness of the plating film. The plurality of parallel arranged convex parts 2 can also facilitate the design and processing of the fringe electric field improving structure, improve the production and manufacturing efficiency of the fringe electric field improving mechanism and reduce the production and manufacturing cost of the fringe electric field improving mechanism.

Example 3

As shown in fig. 3 to 5 and fig. 7 to 9, in the present embodiment, the protrusion 2 is a horizontal protrusion 211 disposed along the horizontal direction of the inner sidewall 112, or the protrusion 2 is a vertical protrusion 212 disposed along the vertical direction of the inner sidewall 112, or another strip-shaped structure disposed obliquely to the horizontal direction of the inner sidewall 112.

If the carrying frame 11 is circular, the protruding portion 2 is a circular ring or arc parallel to each other and disposed on the inner sidewall 112 of the circular carrying frame 11, or may be a strip-shaped structure disposed on the inner sidewall 112 of the circular carrying frame 11 and parallel to the axial direction of the circular carrying frame 11. If the placing frame 11 is a quadrangle or other shapes, the placing frame 11 has a plurality of inner side walls 112, in this embodiment, taking the placing frame 11 as a quadrangle as an example, a plurality of mutually parallel convex parts 2 are arranged in the horizontal direction of one or more inner side walls 11 of the placing frame 11; or a plurality of mutually parallel convex parts 2 which are arranged along the vertical direction of the inner side wall 112; or a plurality of mutually parallel protrusions 2 arranged obliquely to the horizontal direction of the inner side wall 112.

Example 4

As shown in fig. 3 and fig. 11, in the present embodiment, the protrusions 2 are arranged in a dot-matrix manner along the inner sidewall 112 of the carrying frame 11. The convex part 2 can be a point-shaped circular arc bulge 22, more convex points can be formed on the convex part 2 arranged in a point-shaped array manner relative to the inner side wall 112 of the carrying frame 11, the convex parts 2 arranged in a point-shaped array manner can be distributed in an array manner at equal intervals or distributed in a non-array manner at unequal intervals, the convex parts 2 arranged in an array manner at equal intervals are preferably distributed in an array manner at equal intervals, the convex parts 2 distributed in an even manner can guide electric field lines to be distributed more evenly, and the uniformity of a fringe electric field is further improved.

Example 5

As shown in fig. 6, in the present embodiment, the cross-sectional area of the protrusion 2 on the disposing surface in the direction away from the inner sidewall 112 of the placing frame 11 gradually decreases, the top surface is formed at the top end of the protrusion 2, and the tip discharge effect is formed on the top surfaces of the plurality of protrusions 2. Thereby changing the uniformity of the fringe electric field. The cross section of the convex part 2 perpendicular to the length direction thereof in the preferred embodiment is in the shape of a circular arc surface, an isosceles trapezoid, or a boss. If the cross section of the boss 2 is isosceles trapezoid, the boss 2 is truncated cone-shaped, and an arc chamfer 4 can be arranged between the upper bottom surface and the side surface of the truncated cone, namely the cross section is isosceles trapezoid with the arc chamfer arranged at the upper bottom. The arc surface, the isosceles trapezoid that sets up circular arc chamfer 4, the boss shape all can let the top of bellying 2 form the rounding off face, and the rounding off face can prevent because the electric field line that 2 tops of bellying are too sharp-pointed and lead to is too concentrated, can further improve the homogeneity of whole top edge electric field.

Example 6

As shown in fig. 3, 7 and 10, in this embodiment, the arc of the arc surface formed by the convex portion 2 is less than or equal to 180 °, so that an included angle formed between the inner side walls 112 of the convex portion 2 and the carrying frame 11 is greater than or equal to 90 °, and the influence of the inner side walls 112 of the carrying frame 11 on the electric field lines is reduced.

Example 7

As shown in FIG. 4 and FIGS. 7 to 10, in this embodiment, basically the same as the above embodiment, it is preferable that the distance between the side edge of the silicon wafer 3 and the inner side wall 112 of the placing frame 11 is D1; the farthest point of the projection 2 in the direction perpendicular to the inner side wall 112 is at a distance H1 from the inner side wall 112, i.e. the top end of the projection 2 is at a distance H1 from the inner side wall 112. Wherein D1 is more than or equal to 2 XH 1, this arrangement is advantageous in preventing the edge of the silicon wafer 3 from being too close to the tip of the convex portion 2, which affects the uniformity of the fringe field lines. In the present embodiment, the preferable value of H1 is 1 to 4 mm.

In this embodiment, the width of the protruding portion 2 may be further limited, and specifically, if the protruding portion 2 is a circular arc protrusion with a long strip shape, the contact surface of the protruding portion with the inner side wall 112 is a rectangle, and the width of the shorter side of the rectangle is D2, that is, the width of the contact surface of the protruding portion 2 with the inner side wall 112 is D2; if the protrusions 2 are arranged in a dot-like array, the contact surface with the inner sidewall 112 is a circular surface having a diameter D2. D1 is not less than (1-1.5) multiplied by D2, and the preferable numerical range of D2 is 0.1-6 mm, so that the point discharge effect at the top end of the convex part 2 can be prevented from being reduced due to the fact that the arc line at the top end of the convex part 2 is too flat, and the improvement effect of the convex part 2 on the edge electric field uniformity is reduced.

Example 8

As shown in fig. 1, fig. 2 and fig. 3, this embodiment is substantially the same as the above embodiments, an arc chamfer 4 is disposed between an inner sidewall 112 of the carrying frame 11 and a top surface 111 of the carrying frame 11, the arc chamfer 4 can form a smooth transition surface at a junction of the inner sidewall 112 and the top surface 111, so as to prevent two planes from being directly intersected, an edge angle is formed at the junction between the two directly intersected planes, and the edge angle can form a tip discharge effect, thereby affecting uniformity of an edge electric field.

Example 9

The present embodiment provides a carrier plate monomer, including the fringe field improving structure described in any one of embodiments 1 to 9. Further, a stage 12 is provided below the mounting frame 11, the stage 12 is configured to carry the silicon wafer 3, and the stage 12 and the mounting frame 11 are configured to be integrated or separated. The outer side surface of the mounting table 12 is flush with the outer side surface of the mounting frame 11, and the width of the top surface of the mounting table 12 is larger than the width of the top surface 112 of the mounting frame 11.

Example 10

The embodiment provides a carrier plate, which includes the carrier plate monomers 1 described in embodiment 9, wherein the carrier plate monomers 1 are distributed on the carrier plate in an array. In order to increase the strength of the carrier plate, a reinforcement 5 may also be provided in the middle part of the carrier plate. The carrier plate provided by the embodiment can improve the distribution uniformity of the fringe electric field near the carrier frame 11, and can reduce the difference between the thickness of the coating film at the edge of the silicon wafer 3 and the thickness of the coating film at the middle part when the silicon wafer 3 is coated due to the improvement of the distribution uniformity of the fringe electric field. Taking the requirement of the coating thickness of 70-80 nm as an example, the edge coating or the thickness of the silicon wafer 3 which is not adopted by the scheme is 6-15 nm thinner than that of the middle part, and the difference between the coating thickness of the edge part and the coating thickness of the middle part of the silicon wafer 3 is reduced to 2-4 nm when the silicon wafer 3 is coated by the scheme. Meanwhile, the reduction of the difference of the coating thickness on the surface of the silicon wafer 3 improves the consistency of the overall appearance color of the silicon wafer 3 after coating.

Claims

1. A fringe electric field improving structure is characterized in that: a plurality of projections (2) are provided on the inner side wall (112) of a mounting frame (11) for mounting a silicon wafer (3).

2. The fringe electric field improving structure of claim 1, wherein: the convex parts (2) are in a strip-shaped structure, and the convex parts (2) are arranged in parallel.

3. The fringe electric field improving structure of claim 1, wherein: the bulge (2) is arranged along the horizontal direction of the inner side wall (112), or is arranged along the vertical direction of the inner side wall (112), or is arranged along the horizontal direction of the inclined inner side wall (112).

4. The fringe electric field improving structure of claim 2, wherein: the bulge (2) is arranged along the horizontal direction of the inner side wall (112), or is arranged along the vertical direction of the inner side wall (112), or is arranged along the horizontal direction of the inclined inner side wall (112).

5. The fringe electric field improving structure of claim 1, wherein: the convex parts (2) are arranged in a point array along the inner side wall (112).

6. The fringe electric field improving structure of any one of claims 1 to 5, wherein: the cross section of the convex part (2) includes but is not limited to a circular arc surface and an isosceles trapezoid.

7. The fringe electric field improving structure of claim 6, wherein: the radian of the arc surface is less than or equal to 180 degrees.

8. The fringe electric field improving structure of any one of claims 1 to 5, wherein: the distance between the side edge of the silicon wafer (3) and the inner side wall (112) of the carrying frame (11) is D1; the distance between the top end of the convex part (2) and the inner side wall (112) is H1; wherein D1 is more than or equal to 2 XH 1.

9. The fringe electric field improving structure of claim 8, wherein: the width or the diameter of the contact surface of the convex part (2) and the inner side wall (112) is D2, D1 is not less than (1-1.5) multiplied by D2.

10. The fringe electric field improving structure of claim 7, wherein: the distance between the side edge of the silicon wafer (3) and the inner side wall (112) of the carrying frame (11) is D1; the distance between the top end of the convex part (2) and the inner side wall (112) is H1; wherein D1 is more than or equal to 2 XH 1.

11. The fringe electric field improving structure of claim 10, wherein: the width or the diameter of the contact surface of the convex part (2) and the inner side wall (112) is D2, D1 is not less than (1-1.5) multiplied by D2.

12. The fringe electric field improving structure of claim 9, wherein: an arc chamfer (4) is arranged between the inner side wall (112) and the upper top surface (111) of the carrying frame (11).

13. The fringe electric field improving structure of claim 11, wherein: an arc chamfer (4) is arranged between the inner side wall (112) and the upper top surface (111) of the carrying frame (11).

14. A support plate monomer is characterized in that: comprising the fringing electric field improving structure according to any one of claims 1 to 13.

15. The carrier plate cell of claim 14, wherein: the lower side of the carrying frame (11) is provided with a carrying table (12), the carrying table (12) is used for carrying the silicon wafer (3), and the carrying table (12) and the carrying frame (11) are of an integrated or split structure.

16. A carrier plate, its characterized in that: comprising a plurality of carrier plate monomers (1) according to claim 14 or 15, wherein the carrier plate monomers (1) are distributed on the carrier plate in an array.