CN111641090B

CN111641090B - An active 1: n branch cable

Info

Publication number: CN111641090B
Application number: CN201910155916.7A
Authority: CN
Inventors: Y·拉姆; B·陈; 戴逸飞; W·J·布伦南
Original assignee: Credo Technology Group Ltd
Current assignee: Credo Technology Group Ltd
Priority date: 2019-03-01
Filing date: 2019-03-01
Publication date: 2022-05-03
Anticipated expiration: 2039-03-01
Also published as: US11018709B2; US20210234567A1; US20200280329A1; US11581913B2; CN111641090A

Abstract

Accordingly, active cables and methods are disclosed herein that enable direct connection between different generations of network interface ports or ports that support different standards. One illustrative embodiment is an active 1: an N-drop cable including a unitary end connector connected to each of a plurality of split end connectors by electrical conductors. The unigram connector is adapted to fit to a network interface port of a primary host device to provide an output PAM4 electrical signal and accept an input PAM4 electrical signal, the output PAM4 electrical signal carrying a multi-channel outbound data stream to the primary host device, the input PAM4 electrical signal carrying a multi-channel inbound data stream from the primary host device. Each of the split-end connectors is adapted to fit to a network interface port of a secondary host device to provide an outgoing NRZ electrical signal conveying a split portion of an inbound data stream to the secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of an outbound data stream from the secondary host device.

Description

An active 1: n branch cable

Background

The Institute of Electrical and Electronics Engineers (IEEE) standards institute published the ethernet IEEE standard IEEE Std 802.3-2015, which will be familiar to those of ordinary skill in the art to which this application pertains. The ethernet standard is a universal media access control specification for Local Area Network (LAN) operation that provides selected speeds of 1Mbps to 100Gbps with various channel signal constellations over coaxial cable, twinaxial cable, twisted pair cable, fiber optic cable, and electronic backplane. This standard is expanding as the demand for higher data rates continues. Even if the equalizer is forced to operate at faster symbol rates, this extension to the standard must account for increased channel attenuation and dispersion. However, as the standard expands, it may not be able to interoperate directly with the current generation. For example, there is no way to directly couple the current 100Gbps ethernet port to the proposed next generation 400Gbps ethernet port.

Disclosure of Invention

Accordingly, active cables and methods are disclosed herein that enable direct connection between different generations of network interface ports or ports that support different standards. One illustrative embodiment is an active 1: an N-drop cable including a unitary end connector connected to each of a plurality of split end connectors by electrical conductors. The unigram connector is adapted to fit to a network interface port of a primary (primary) host device to provide an output PAM4 electrical signal and to accept an input PAM4 electrical signal, the output PAM4 electrical signal carrying a multi-channel outbound data stream to the primary host device, the input PAM4 electrical signal carrying a multi-channel inbound data stream from the primary host device. Each of the split-end connectors is adapted to fit to a network interface port of a secondary host device to provide an outgoing NRZ electrical signal conveying a split portion of an inbound data stream to the secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of an outbound data stream from the secondary host device.

Another illustrative embodiment is a cable manufacturing method, comprising: encapsulating the transceiver into a unions connector adapted to mate with a network interface port of a primary host device; and connecting each of the plurality of split end connectors to the unary end connector using an electrical conductor. Each of the splitter connector is adapted to mate with a network interface port of a secondary host device to provide an outgoing NRZ electrical signal conveying a split portion of a multi-channel inbound data stream to the secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of a multi-channel outbound data stream from the secondary host device. The transceiver is configured to provide an output PAM4 electrical signal that conveys the outbound data stream to the primary host device and accept an input PAM4 electrical signal that conveys the inbound data stream from the primary host device. The transceiver is further configured to perform clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transmission signal that transmits a split portion of the inbound data stream to the split-end connector via the electrical conductor, and the transceiver is configured to perform clock and data recovery on the convergent transmission signal to extract and remodulate the outbound data stream as said output PAM4 electrical signal.

Yet another illustrative embodiment is a cable manufacturing method, comprising: encapsulating the transceiver into each of a plurality of split-end connectors adapted to mate with network interface ports of a secondary host device; and connecting each of the split end connectors to the unary end connector via an electrical conductor. The unigram connector is adapted to mate with a network interface port of the primary host device to provide an output PAM4 electrical signal and accept an input PAM4 electrical signal, the output PAM4 electrical signal carrying the multi-channel outbound data stream to the primary host device, and the input PAM4 electrical signal carrying the multi-channel inbound data stream from the primary host device. Each of the transceivers in the split-end connector is configured to provide an outgoing NRZ electrical signal conveying a split portion of an inbound data stream to the secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of an outbound data stream from the secondary host device. The transceiver in each split-end connector is further configured to perform clock and data recovery on the incoming NRZ electrical signal to extract and remodulate the split portion of the outbound data stream as a converged transmit signal that transmits the split portion of the outbound data stream to the unary-end connector via the electrical conductor, and the transceiver in each split-end connector is configured to perform clock and data recovery on the divergent transmit signal to extract and remodulate the split portion of the inbound data stream as the outgoing NRZ electrical signal.

Yet another illustrative embodiment is an active 1: an N drop cable comprising a unitary end connector connected by electrical conductors to each of N split end connectors, N being an integer greater than 1. The one-port connector is adapted to fit to a network interface port of the primary host device to provide a first output electrical signal conveying the multi-channel outbound data stream at the first symbol rate to the primary host device and to accept a first input electrical signal conveying the multi-channel inbound data stream from the primary host device at the first symbol rate. Each of the split-end connectors is adapted to fit to a network interface port of a secondary host device to provide a second output electrical signal conveying the split portion of the inbound data stream to the second host device at a second symbol rate and to accept a second input electrical signal conveying the split portion of the outbound data stream from the second host device at the second symbol rate, the second symbol rate being half the first symbol rate.

Yet another illustrative embodiment is a cable manufacturing method, comprising: encapsulating the transceiver into a unions connector adapted to mate with a network interface port of a primary host device; and connecting each of the N split end connectors to the unary end connector with an electrical conductor, where N is an integer greater than 1. Each of the split-end connectors is adapted to mate with a network interface port of a secondary host device to provide a second output electrical signal conveying a split portion of an inbound data stream to the secondary host device at a second symbol rate and to accept a second input electrical signal conveying a split portion of an outbound data stream from the secondary host device at the second symbol rate. The transceiver is configured to provide a first output electrical signal that conveys the multi-channel outbound data stream to the primary host device at a first symbol rate and receive a first input electrical signal that conveys the multi-channel inbound data stream from the primary host device at the first symbol rate, the first symbol rate being twice the second symbol rate. The transceiver is further configured to perform clock and data recovery on the first input electrical signal to extract and remodulate the inbound data stream as a divergent transmission signal that transmits a split portion of the inbound data stream to the split-end connector via the electrical conductor, and the transceiver is configured to perform clock and data recovery on the convergent transmission signal to extract and remodulate the outbound data stream as the first output electrical signal.

Yet another illustrative embodiment is a cable manufacturing method, comprising: encapsulating the transceiver into each of N split-end connectors adapted to mate with network interface ports of a secondary host device, where N is an integer greater than 1; and connecting each of the split end connectors to the unary end connector via an electrical conductor. The meta-terminal connector is adapted to mate with a network interface port of the primary host device to provide a meta-terminal output electrical signal that conveys the outbound data stream to the primary host device at a first symbol rate and to accept a meta-terminal input electrical signal that conveys the inbound data stream from the primary host device at the first symbol rate. Each of the transceivers in the splitting connector is configured to provide a split-end output electrical signal that conveys split portions of the multi-channel inbound data stream to the secondary host device at a second symbol rate that is half the first symbol rate and to accept a split-end input electrical signal that conveys split portions of the multi-channel outbound data stream from the secondary host device at the second symbol rate. Each of the transceivers is further configured to perform clock and data recovery on the split-end input electrical signal to extract and remodulate the split portion of the outbound data stream as a converged transmit signal that transmits the split portion of the outbound data stream to the unary-end connector via the electrical conductor, and each of the transceivers is further configured to perform clock and data recovery on the divergent transmit signal to extract and remodulate the split portion of the inbound data stream as the split-end output electrical signal.

Each of the foregoing embodiments may be implemented alone or in combination, and may be implemented with one or more of the following features in any suitable combination: 1. the uniport connector includes a transceiver that performs clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transport signal that transports a split portion of the inbound data stream to the split-port connector via the electrical conductor. 2. The transceiver in the unary terminator performs clock and data recovery on the converged transmission signal to extract and remodulate the outbound data stream as the outgoing PAM4 electrical signal. 3. The divergent transmission signal and the convergent transmission signal are NRZ electrical signals. 4. The divergent transmission signal and the convergent transmission signal are PAM4 electrical signals. 5. Each of the split-end connectors includes a redriver circuit that provides an output NRZ electrical signal by amplifying the divergent transport signal it receives. 6. The redriver circuit provides at least one of the converged transmission signals by amplifying the input NRZ electrical signal it receives. 7. Each of the split-end connectors includes a transceiver that performs clock and data recovery on its received divergent transmission signal to extract and remodulate the split portion of the inbound data stream. 8. The transceiver in each split-end connector performs clock and data recovery on the incoming NRZ electrical signal to extract and remodulate the split portion of the outbound data stream. 9. The transceiver in each split-end connector further performs forward error correction when extracting the split portion of the inbound data stream. 10. The transceiver in the meta-terminal connector further performs forward error correction when extracting the outbound data stream. 11. Heavy driver circuits are packaged into each of the split end connectors. 12. The transceivers are packaged into each of the split-end connectors. 13. The transceiver is packaged into a meta-terminal connector.

Drawings

Fig. 1 is an illustrative active 1: a perspective view of an N drop cable.

Fig. 2A is a schematic diagram of one illustrative drop cable embodiment.

Fig. 2B is a schematic view of a second illustrative drop cable embodiment.

FIG. 3A is a functional block diagram of an illustrative gearbox transceiver embodiment.

Fig. 3B is a functional block diagram of an illustrative CDR transceiver embodiment.

Fig. 4 is a block diagram of an illustrative receiver.

Fig. 5 is a block diagram of an illustrative transmitter.

Fig. 6 is an architecture diagram of an active cable connector.

Fig. 7 is a flow chart of an illustrative cable manufacturing method.

Detailed Description

While specific embodiments are set forth in the drawings and the following description, it should be borne in mind that they do not limit the disclosure. On the contrary, they provide the basis for the ordinary skilled person to discern the alternatives, equivalents and modifications that are included within the scope of the appended claims.

Fig. 1 is illustrative 1: a perspective view of a 4 drop cable that may be used to provide a high bandwidth communication link between devices in a routing network. The routing network may be or include, for example, the internet, a wide area network, or a local area network. The linking device may be a computer, switch, router, hub, etc. The drop cable includes a unitary end connector 100 electrically connected to a plurality of furcation end connectors 101-104 via conductors 106. The unigram end may also be referred to as the public end, the undivided end, or the primary host end, etc., and it is designed to communicate with the network interface of the host at N times the data rate of the split-end connectors, where N is the number of split-end connectors. The split-end connector may be referred to as a branch end, a split end, a legacy end, or a secondary host end, etc., and it is designed to communicate with the network interface of the host at 1/N times the data rate of the unary-end connector.

The electrical conductors may be provided in pairs, such as with a twinaxial conductor. A twinaxial conductor may be likened to a coaxial conductor but with two inner conductors instead of one. The inner conductors may be driven with differential signals and their common shield may reduce crosstalk with other twinax conductors in the cable. Other paired or single ended conductor implementations may be employed, depending on performance criteria. The pairs of conductors may provide unidirectional transmission of differential signals.

In one contemplated 1: in the 4-drop cable embodiment, the unitary end connector is a quad small form-factor pluggable dual density (QSFP-DD) connector or an eight-channel small form-factor pluggable (OSFP) connector configured to provide and accept 400Gbps in the form of 8 50Gbps PAM4 electrical signal channels. The four split-end connectors are quad small form-factor pluggable rate up to 28 Gbps/channel (QSFP28) connectors, each configured to provide and accept 100Gbps in the form of 4 25Gbps NRZ electrical signal channels. Thus, the contemplated embodiment includes a "gearbox" module that converts between 50Gbps PAM4 electrical signals and 25Gbps NRZ electrical signals. However, any connector conforming to the ethernet standard or other network communication standard may be used.

In another contemplated 1: in a 2 drop cable embodiment, the unidrop connector is configured to provide and accept 400Gbps in the form of 4 100Gbps PAM4 electrical signal channels. The two split-end connectors are each configured to provide and accept 200Gbps in the form of 4 50Gbps PAM4 electrical signal channels. Thus, the contemplated embodiment includes a gearbox module that converts between a 50Gbps PAM4 electrical signal channel pair and a 100Gbps PAM4 electrical signal single channel.

In another contemplated 1: in a 2 drop cable embodiment, the unidrop connector is configured to provide and accept 80Gbps in the form of 4 20Gbps NRZ electrical signal channels. The two split-end connectors are each configured to provide and accept 40Gbps in the form of 410 Gbps NRZ electrical signal channels. Thus, the contemplated embodiment includes a gearbox module that converts between a 10Gbps NRZ electrical signal channel pair and a 20Gbps NRZ electrical signal single channel.

To provide PAM4-NRZ and/or 2-1 channel + rate conversion while achieving robust performance, the unary end connector and/or split end connector may include an active transceiver that performs Clock and Data Recovery (CDR) and remodulation of the data stream in each direction. It is noted that the transceiver not only performs CDR and remodulation when the outbound data stream exits the cable, but also remodulates the inbound data stream as it enters the cable. (although used herein for unary and split-end connectors, the terms "inbound" and "outbound" as used in the claims are to be defined with respect to the unary connector 100 such that an "inbound" data stream is a data stream entering the cable at the unary connector and split between split-end connectors, with the split portion of the inbound data stream exiting the cable

It is recognized herein that the data streams entering the cable can be expected to conform to the relevant standards, and that they can be expected to experience substantially no degradation from the socket pins of the network interface port and the plug pins of the connector. However, the modulation quality and equalization strategy employed by the electronics manufacturer of the transmitting network interface is generally unknown, and the minimum requirements of the standard may not be sufficient for transmission over extended cable lengths, particularly if the electronics manufacturer of the receiving network interface is different from the transmitting network interface. As with the transmit network interface, the equalization and demodulation strategies employed by the electronics manufacturer of the receive network interface are generally unknown and may not be able to cope with the attenuation and interference caused by signal transmission over extended cable lengths. At least some contemplated embodiments perform CDR and remodulation of incoming and outgoing data streams at each end to ensure robust data transmission throughout more extended cable lengths, regardless of the electronic manufacturer of the network interface.

Fig. 2A is a contemplated active 1: schematic illustration of a 4 drop cable embodiment. The integrated circuit TR0 is packaged in a one-up connector 100, and each split-end connector 101-104 includes a corresponding integrated circuit TR1-TR 4. The integrated circuit TR0 may be soldered to a printed circuit board that connects the host-facing side of the integrated circuit to the pins of the unitary end connector 100 and the cable-facing side of the integrated circuit to the electrical conductors 106. Similarly, each of the integrated circuits TR1-TR4 may be soldered to a printed circuit board that connects the host-facing side of the integrated circuit to the pins of the split end connectors 101-104 and the cable-facing side of the integrated circuit to the electrical conductors 106. In at least some embodiments, all integrated circuits TR0-TR4 are transceivers that perform CDR and re-modulation of data streams traveling in both directions. In other embodiments, integrated circuit TR0 or integrated circuits TR1-TR4 are re-drivers (analog linear amplifiers) that operate on signals that have attenuated during transmission on conductor 106 and may further operate on signals to be transmitted over the conductor to pre-compensate for at least some of the attenuation. In other embodiments, integrated circuit TR0 or integrated circuits TR1-TR4 are omitted to facilitate a direct connection between conductor 106 and a connector pin.

Fig. 2A shows a contemplated cable embodiment in which the unitary end connector 100 includes a transceiver TR0 with a gear box module. The host-facing side of transceiver TR0 provides and accepts 8 50Gbps PAM4 electrical signal channels. The cable facing side of transceiver TR0 provides and accepts 16 25Gbps NRZ electrical signal channels. Four channels are allocated to the split end connectors 101-104, respectively, by 16 channels. A potential advantage of this embodiment is that the 25Gbps NRZ electrical signal can withstand attenuation and interference better than the 50Gbps PAM4 signal, providing more robust performance and potentially allowing the use of heavy drivers or direct connections in the split end connectors 101-104. Alternatively, integrated circuit TR1-TR4 may be a receiver that accepts and provides 4 25Gbps NRZ electrical signal channels on both the host-facing side and the cable-facing side.

Fig. 2B shows an alternative cable embodiment in which the split end connectors 101-104 each include a transceiver (TR1'-TR4') with a gear box module. The host-facing side of transceivers TR1-TR4 provides and accepts 4 25Gbps NRZ electrical signal channels. The cable facing sides of these transceivers provide and accept 2 50Gbps PAM4 electrical signal channels, which in combination provide 8 50Gbps PAM4 electrical signal channels for a unigram connector. A potential advantage of this embodiment is that it requires fewer conductors 106. Further cost savings can be realized by using heavy drivers or direct connections in the unitary end connector 100. Alternatively, integrated circuit TR0' may be a receiver that accepts and provides 8 50Gbps NRZ electrical signal channels on both the host-facing side and the cable-facing side.

Fig. 3A is a functional block diagram of an illustrative transceiver that includes gearbox functionality. The transceiver includes a first set of transmitters and receivers 302 and a second set of transmitters and receivers 304. In FIG. 3A, a first set 302 is for high-rate channels (e.g., 50Gbps PAM4) and a second set 304 is for low-rate channels (e.g., 25Gbps NRZ). The gearbox function is provided by a bank of format converters 306. In fig. 3A, group 306 is shown to include PAM4-NRZ converters and NRZ-PAM4 converters. PAM4-NRZ converters each accept a data stream of PAM4 symbols, producing two NRZ bit streams. In at least some embodiments, the PAM4-NRZ converter decodes the PAM4 symbols using Gray codes (Gray codes) to obtain corresponding data bits, and allocates one bit from each symbol to each NRZ bit stream. In contrast, NRZ-PAM4 converters each take two NRZ bit streams and convert them into a data stream of PAM4 symbols. The NRZ-PAM4 converter takes one bit from each bit stream and applies gray code to obtain each PAM4 symbol.

In other contemplated embodiments, the set of format converters 306 may be multiplexers and demultiplexers that provide 2-1 lane + rate conversion. For example, a channel multiplexer may accept two channels (i.e., two data streams) of PAM4 symbols and produce one channel (i.e., one data stream) of PAM4 symbols at twice the symbol rate of the input channel. The corresponding channel demultiplexer will accept one input channel of PAM4 symbols and produce two PAM4 symbol channels with half the symbol rate of the input channel. As another example, a channel multiplexer may accept two channels of NRZ bits (i.e., two bit streams) and produce one channel of NRZ bits (i.e., one bit stream) with twice the bit rate of the input channel. The corresponding channel demultiplexer will accept one input channel of NRZ bits and produce two channels of NRZ bits with half the symbol rate of the input channel.

The conversion of PAM4-NRZ may also be combined with channel + rate conversion such that, for example, one input channel of PAM4 symbols is converted to four output channels of NRZ bits having half the input channel symbol rate, and four input channels of NRZ bits are converted to one output channel of PAM4 symbols.

The memory 308 provides FIFO buffering between the transmitter and

receiver groups

302, 304. Note that the order of the converter 306 and memory 308 may be switched between the transmitter and

receiver groups

302, 304. The controller 310 coordinates the operation of the transmitter and receiver by, for example, setting initial equalization parameters and ensuring that a training phase is completed across all channels and links before the transmitter and receiver are put into a data transmission phase.

Referring briefly to fig. 6, PAM4-NRZ and/or 2-1 lane + rate conversion may be conceptually performed at the data link layer 640, i.e., sandwiched between optional FEC and PCS sublayer processing by the

physical layers

622A, 622. In some variations, the transceiver may omit processing associated with some or all of the MAC, mediation, PCS, and FEC sublayers, performing bit-to-channel remapping to bridge between lower sublayers such as FEC or even PMA. In some embodiments, the FEC sublayer is implemented only on the host-facing side or only on the cable-facing side. In other embodiments, bit-to-channel remapping is performed to bridge between FEC sublayers on both sides.

Fig. 3B is a functional block diagram of an illustrative transceiver that omits the gearbox function but includes other components described above. The transceiver embodiment of fig. 3B has the same number of channels in each direction (host-facing and cable-facing), using the same signaling formation (PAM4 or NRZ), while the embodiment of fig. 3A changes the signaling formation and provides twice as many channels in one direction as the other.

In at least some contemplated embodiments, the host-facing groups of transmitters and receivers employ fixed equalization parameters that are independent of the cable, i.e., they are not customized on a cable-by-cable basis. The cable-oriented groups of transmitters and receivers preferably employ cable-dependent equalization parameters that are customized on a cable-by-cable basis. The cable-related equalization parameters may be adaptive or fixed, and the initial values of these parameters may be determined during manufacturer testing of the cable. The equalization parameters may include filter coefficient values for a pre-equalizer filter in the transmitter, and gain and filter coefficient values for the receiver.

Fig. 4 and 5 are block diagrams of an illustrative receiver and an illustrative transmitter that may be used to implement the

sets

302, 304. IN fig. 4, a receiver 400 receives an analog electrical signal (CH _ IN) and provides it to a Low Noise Amplifier (LNA) 402. LNA 402 provides a high input impedance to minimize channel loading and amplifies the received electrical signal to drive the input of a continuous-time linear equalizer (CTLE) filter 404. The CTLE 404 provides continuous-time filtering to shape the signal spectrum to reduce the length of the channel impulse response while minimizing preamble inter-symbol interference (ISI). A Decision Feedback Equalizer (DFE)406 operates on the filtered signal to correct for trailing ISI and to detect each transmitted channel bit or symbol, thereby producing a demodulated digital data stream. Some embodiments employ oversampling. Clock and Data Recovery (CDR) circuit 408 extracts a clock signal from the filtered signal and/or the digital data stream and provides it to DFE 406 to control sample and symbol detection timing. Serial-to-parallel conversion circuit 410 groups the digital data stream bits or symbols into blocks to enable the use of a lower clock rate for subsequent on-chip operations. The symbols or data blocks are placed on a digital receive bus (RXD) for retransmission by a transmitter to a remote end node.

While some contemplated cable embodiments do not support auto-negotiation, other contemplated embodiments do support auto-negotiation according to the ethernet standard. When supported, auto-negotiation may be implemented as described by the inventors Yifei Dai, Haoli Qian and Jeff Twombly in international patent application PCT/CN2017/075961 entitled "ethernet link extension method and apparatus" and filed on 3, 8, 2017. The detector or packet information extractor 442 monitors the received signal to detect the end of the auto-negotiation phase and/or the beginning of the training phase frame.

During the training phase, filter adaptation circuit 440 measures the error between the input and output of the decision element in DFE 406, uses the error to determine adjustments to the coefficients in CTLE filter 404, DFE 406, and transmit filter 506 (discussed further below) according to well-known techniques in the literature regarding adaptive filtering, and determines whether convergence has been achieved. Locally generated information (LOCAL _ INFO) including transmit filter coefficient adjustments and convergence status is provided to a LOCAL transmitter 500 in reverse communication over the data channel. As discussed below, the local transmitter communicates transmit filter adjustment and convergence status to the source of the CH _ IN signal via the back channel. IN that case, the received signal includes reverse channel information from the source of the CH _ IN signal. The packet information extractor 442 detects and delivers reverse channel information (BACK _ INFO) to the local transmitter. Once convergence is achieved, the receiver 400 is ready to begin normal operation.

IN fig. 5, a transmitter 500 receives a block of channel bits or symbols for transmission to a source of a CH _ IN signal (fig. 4). During normal operation, the multiplexer 502 provides a block of channel bits or symbols from a remote source (received on the TXD bus) to the parallel-to-serial (P2S) circuit 504. The P2S circuit converts the blocks into a digital data stream. The transmit filter 506, also referred to as a pre-emphasis filter, converts the digital data stream into an analog electrical signal with spectral shaping to combat channel degradation. The driver 508 amplifies the analog electrical signal to drive the channel output (CH _ OUT) node.

If supported, the auto-negotiation phase may be implemented as described in Y.Dai et al. During the training phase, the multiplexer 502 blocks information from the TXD bus and instead provides training frames from the training controller 540 to the P2S circuit 504. The training controller 540 generates a training frame based on the convergence status and transmit filter coefficient adjustment (LOCAL _ INFO) received from the LOCAL receiver 400. That is, in addition to the training pattern, the training frame also includes reverse channel information to be used by the far end of the channel. It should be noted that even after the local receiver indicates that filter convergence has occurred, the training controller 540 may extend the training phase to coordinate the training phase timing across the lanes and each link along the channel. The training frame includes a training sequence specified by the relevant portion of the current ethernet standard (IEEE std 802.3).

The training controller 540 also accepts reverse channel information (BACK _ INFO) extracted by the local receiver from received training frames sent by the local end node. The training controller applies the corresponding adjustments to the coefficients of transmit filter 506. At the end of the training phase, the multiplexer 502 begins forwarding the TXD block to the P2S circuit 504.

Fig. 6 is an architecture diagram of a network interface of a host device 602 and a cable connector 102, the cable connector 102 having one of the illustrative transceivers discussed above. The architecture is represented in accordance with the ISO/IEC model of open systems interconnection (see ISO/IEC 7498-1: 1994.1) for communication over a physical medium such as conductor 106. The interconnection reference model employs a hierarchy of layers with defined functions and interfaces to facilitate the design and implementation of compatible systems by different teams or vendors. Although this is not a requirement, it is contemplated that higher layers in the hierarchy are implemented primarily by software or firmware operating on a programmable processor, while lower layers may be implemented as application specific integrated circuits or similar dedicated hardware.

The application layer 608 is the uppermost layer in the model, and it represents user applications or other software operating on different systems that require facilities for communicating messages or data. Presentation layer 610 provides a set of Application Programming Interfaces (APIs) to applications that provide formal syntax and services for data conversion (e.g., compression), establish communication sessions, connectionless communication modes, and negotiations to enable application software to identify and select from available service options. Session layer 612 provides services for coordinating data exchanges, including: session synchronization, token management, full-duplex or half-duplex mode implementation, and establishment, management, and release of session connections. In connectionless mode, the session layer may only map between session addresses and transport addresses.

Transport layer 614 provides services for multiplexing, end-to-end sequence control, error detection, segmentation, blocking, concatenation, flow control over individual connections (including suspension/restoration), and implementation of end-to-end quality of service specifications. The transport layer 614 focuses on end-to-end performance/behavior. Network layer 616 provides routing services, determines links for end-to-end connections, and acts as a relay service to couple these links together if necessary. The data link layer 618 serves as an interface to the physical connection, providing delimitation, synchronization, sequencing, and flow control across the physical connection. It may also detect and optionally correct errors that occur across the physical connection. Physical layer 622 provides the mechanical, electrical, functional, and procedural means to activate, maintain, and deactivate channels and use the channels for bit transmission across physical medium 106.

Data link layer 618 and physical layer 622 are slightly subdivided and modified by IEEE standard 802.3-2015, which provides a Medium Access Control (MAC) sublayer 622 in data link layer 618 to define an interface with physical layer 622, including frame structure and transmission syntax. Within the physical layer 622, the standard provides various possible subdivisions, such as that shown in fig. 6, including AN optional mediation sublayer 624, a Physical Coding Sublayer (PCS)626, a Forward Error Correction (FEC) sublayer 628, a Physical Medium Attachment (PMA) sublayer 630, a Physical Medium Dependent (PMD) sublayer 632, and AN auto-negotiation (AN) sublayer 634.

The optional mediation sublayer 624 only maps between the interfaces defined for the MAC sublayer 620 and the PCS sublayer 626. The PCS sublayer 626 provides scrambling/descrambling, data encoding/decoding (with transport codes that enable clock recovery and bit error detection), block and symbol reallocation, PCS alignment mark insertion/removal, and block level channel synchronization and deskew (deskew). To achieve bit error rate estimation by components of the physical layer 622, the PCS alignment marks typically include bit cross parity (BIP) values derived from previous bits in the channel up to and including a previous PCS alignment mark.

The FEC sublayer 628 provides, for example, Reed-Solomon encoding/decoding that allocates blocks of data with controlled redundancy across channels to achieve error correction. In some embodiments (e.g., according to clause 91 or clause 134 of ieee std802.3), the FEC sublayer 628 modifies the number of channels (clause 91 provides 20-to-4 channel conversion).

The PMA sublayer 630 provides channel remapping, symbol encoding/decoding, framing (framing), and octet/symbol synchronization. PMD sublayer 632 specifies transceiver conversion between transmitted/received channel signals and corresponding bit (or digital symbol) streams. The optional AN sublayer 634 is shown here as AN internal element of the PMD sublayer 632 and it enables initial startup of the communication channel to perform AN auto-negotiation phase and a link training phase before entering a normal operation phase. The auto-negotiation phase enables the end nodes to exchange information about their capabilities, and the training phase enables the end nodes to adapt both transmit-side and receive-side equalization filters in a manner that counters channel imperfections.

Socket 636 is also shown as part of PMD sublayer 632 to represent a physical network interface port. The connector 102 has a plug that mates with a receptacle 636 of the host device 602. Within the connector, the transceiver may implement a host-facing physical layer 622A, a cable-facing physical layer 622B, and a data link layer 640 that bridges the two physical layers together.

The MAC, mediation, PCS, FEC, PMA and PMD sublayers may be implemented as application specific integrated circuits to achieve high rate processing and data transmission. The receiver and

transmitter groups

302, 304 may implement PMA and PMD sublayers. More information on the operation of the various layers and sub-layers, as well as the electrical and physical specifications of the connections between the nodes and the communication medium (e.g., pin layout, line impedance, signal voltage and timing) and the communication medium itself (e.g., conductor arrangement in copper cables, attenuation limits, propagation delays, signal skew) may be found in and updated on current ethernet standards, and any such details should be considered well within the knowledge of one of ordinary skill in the art.

Fig. 7 is a flow chart of an illustrative cable manufacturing method. It begins in block 702 with the following steps: the electrical conductors are typically connected between the unitary end connector and the split end connector by soldering the wire ends to pads of a circuit board attached to the connector plug. Traces (trace) on the circuit board may directly connect the pads to the pins of the connector plug. Alternatively, traces may connect the chip with an integrated circuit transceiver or re-driver between the pads and pins of the connector plug. This and subsequent steps may be performed by automated manufacturing/testing equipment. In block 704, the apparatus packages a circuit board (including any integrated circuit components) in a corresponding end connector for a network cable. The connector is adapted to mate with a network interface port of a host device and includes a plug that electrically connects with a mating receptacle in the port.

In block 706, the device tests the cable to verify compliance with the performance specifications and determines cable-related equalization parameters for use by the cable-facing transmitter and receiver groups. In block 708, the apparatus causes the transceiver to store equalization parameters (including cable-related parameters and cable-independent parameters) in a non-volatile memory. The cable may then be packaged and sold to customers.

Although the foregoing description has focused primarily on 1: 4 drop cable design, the disclosed principles are also applicable to other cable designs, including 1: 2. 1: 8 and 1:16 drop cable designs. Each 100Gbps PAM4 channel may transmit a PAM4 symbol at 53.125 Gbaud. Each 50Gbps PAM4 may transmit PAM4 symbols at 26.5625Gbaud, while each 25Gbps NRZ channel may transmit NRZ symbols at 26.5625 Gbaud. These channels may be grouped together according to the Ethernet standard to provide 25Gbps, 50Gbps, 100Gbps, 200Gbps, 400Gbps, or 800 Gbps. Other standards may also be supported in which the connector transceiver provides in-line format conversion and channel multiplexing/demultiplexing.

Numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the claims be interpreted to embrace all such alternatives, equivalents and modifications as fall within the scope of the appended claims.

Claims

1. An active 1: an N drop cable comprising:

a unions connector connected by an electrical conductor to each of N split-end connectors, N being an integer greater than 1,

the unigram connector is adapted to fit to a network interface port of a primary host device to provide an output PAM4 electrical signal and accept an input PAM4 electrical signal, the output PAM4 electrical signal carries a multi-channel outbound data stream to the primary host device, the input PAM4 electrical signal carries a multi-channel inbound data stream from the primary host device, and

each of said splitter-end connectors being adapted to fit to a network interface port of a secondary host device to provide an outgoing NRZ electrical signal conveying a split portion of an inbound data stream to said secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of an outbound data stream from said secondary host device, each of said splitter-end connectors comprising a transceiver that performs clock and data recovery on said incoming NRZ electrical signal to extract and remodulate said split portion of said outbound data stream as one or more converged transport signals that convey split portions of said inbound data stream to said meta-end connector via said electrical conductors, and wherein said transceiver performs clock and data recovery on the divergently transmitted signals, to extract and remodulate a divided portion of the inbound data stream as the output NRZ electrical signal.

2. The active 1: an N drop cable, wherein the meta-terminal connector comprises a transceiver that performs clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transmission signal that transmits split portions of the inbound data stream to the split-terminal connector via the electrical conductor, and wherein the transceiver performs clock and data recovery on a convergent transmission signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal.

3. The active 1: an N-drop cable, wherein the divergent transmission signal and the convergent transmission signal are NRZ electrical signals.

4. The active 1: an N drop cable, wherein the transceiver in the meta-end connector further performs forward error correction when extracting the outbound data stream.

5. The active 1: an N drop cable, wherein the transceiver in each split-end connector further performs forward error correction when extracting split portions of the inbound data stream.

6. The active 1: an N-drop cable, wherein the divergent transmission signal and the convergent transmission signal are PAM4 electrical signals.

7. The active 1: an N drop cable, wherein the meta-terminal connector comprises a transceiver that performs clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as the divergent transport signal that transports the split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and wherein the transceiver in the meta-terminal connector performs clock and data recovery on the convergent transport signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal.

8. The active 1: an N drop cable, wherein the transceiver in the meta-end connector further performs forward error correction when extracting the outbound data stream.

9. An active 1: an N drop cable comprising:

each of the split-end connectors being adapted to fit to a network interface port of a secondary host device to provide an outgoing NRZ electrical signal conveying a split portion of an inbound data stream to the secondary host device and to accept an incoming NRZ electrical signal conveying a split portion of an outbound data stream from the secondary host device,

wherein the meta-terminal connector comprises a transceiver that performs clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transmission signal that transmits a split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and wherein the transceiver performs clock and data recovery on a convergent transmission signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal, wherein the divergent transmission signal and the convergent transmission signal are NRZ electrical signals,

wherein each of the split end connectors includes a redriver circuit that provides the output NRZ electrical signal by amplifying the divergent transport signals it receives, and wherein the redriver circuit provides at least one of the convergent transport signals by amplifying the input NRZ electrical signal it receives.

10. A method of manufacturing a cable, the method comprising:

packaging a transceiver into a uniset connector adapted to mate with a network interface port of a primary host device, the transceiver configured to provide an outgoing PAM4 electrical signal and accept an incoming PAM4 electrical signal, the outgoing PAM4 electrical signal carrying a multi-channel outbound data stream to the primary host device, the incoming PAM4 electrical signal carrying a multi-channel inbound data stream from the primary host device;

connecting each of N split-end connectors to the meta-end connector using an electrical conductor, wherein N is an integer greater than 1, and wherein each of the split-end connectors is adapted to mate with a network interface port of a secondary host device to provide an output NRZ electrical signal that conveys a split portion of the inbound data stream to the secondary host device and to accept an input NRZ electrical signal that conveys a split portion of the outbound data stream from the secondary host device,

the transceiver in the meta-terminal connector is configured to perform clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transport signal that transports a split portion of the inbound data stream over the electrical conductor to the split-terminal connector, and the transceiver in the meta-terminal connector is further configured to perform clock and data recovery on a convergent transport signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal; and

encapsulating a transceiver in each of the split-end connectors, the transceiver in each split-end connector configured to perform clock and data recovery on the divergent transmission signal it receives to extract and remodulate a split portion of the inbound data stream, and further configured to perform clock and data recovery on an incoming NRZ electrical signal to extract and remodulate a split portion of the outbound data stream,

wherein the divergent transmission signal and the convergent transmission signal are PAM4 electrical signals.

11. A method of manufacturing a cable, the method comprising: packaging a transceiver into a uniset connector adapted to mate with a network interface port of a primary host device, the transceiver configured to provide an outgoing PAM4 electrical signal and accept an incoming PAM4 electrical signal, the outgoing PAM4 electrical signal carrying a multi-channel outbound data stream to the primary host device, the incoming PAM4 electrical signal carrying a multi-channel inbound data stream from the primary host device;

connecting each of N split-end connectors to the meta-end connector using an electrical conductor, wherein N is an integer greater than 1, and wherein each of the split-end connectors is adapted to mate with a network interface port of a secondary host device to provide an output NRZ electrical signal that conveys a split portion of the inbound data stream to the secondary host device and to accept an input NRZ electrical signal that conveys a split portion of the outbound data stream from the secondary host device; and

encapsulating a heavy driver circuit into each of the split end connectors, the heavy driver circuit configured to provide the output NRZ electrical signal by amplifying the divergent transport signals it receives and further configured to provide at least one of the convergent transport signals by amplifying the input NRZ electrical signal it receives,

the transceiver in the meta-terminal connector is configured to perform clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as the divergent transport signal that transports the split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and the transceiver in the meta-terminal connector is further configured to perform clock and data recovery on the convergent transport signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal, the divergent transport signal and the convergent transport signal being NRZ electrical signals.

12. A method of manufacturing a cable, the method comprising:

encapsulating a transceiver into each of the split-end connectors, the transceiver in each split-end connector configured to perform clock and data recovery on its received divergent transport signal to extract and remodulate a split portion of the inbound data stream, and further configured to perform clock and data recovery on an incoming NRZ electrical signal to extract and remodulate a split portion of the outbound data stream,

the transceiver in the meta-terminal connector is configured to perform clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as the divergent transport signal that transports the split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and the transceiver in the meta-terminal connector is further configured to perform clock and data recovery on a convergent transport signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal, the divergent transport signal and the convergent transport signal being NRZ electrical signals.

13. A method of manufacturing a cable, the method comprising:

encapsulating transceivers into each of N split-end connectors adapted to mate with network interface ports of a secondary host device, where N is an integer greater than 1, and wherein each of the transceivers in the split-end connectors is configured to provide an outgoing NRZ electrical signal that conveys a split portion of a multi-channel inbound data stream to the secondary host device and accept an incoming NRZ electrical signal that conveys a split portion of a multi-channel outbound data stream from the secondary host device; and

connecting each of the split-end connectors to a unidrop connector via electrical conductors, the unidrop connector adapted to mate with a network interface port of a primary host device to provide an output PAM4 electrical signal and accept an input PAM4 electrical signal, the output PAM4 electrical signal conveying the outbound data stream to the primary host device, the input PAM4 electrical signal conveying the inbound data stream from the primary host device,

the transceiver in each split-end connector is configured to perform clock and data recovery on the incoming NRZ electrical signal to extract and remodulate a split portion of the outbound data stream as a converged transmit signal that transmits the split portion of the outbound data stream to the unary-end connector via the electrical conductor, and the transceiver in each split-end connector is further configured to perform clock and data recovery on a divergent transmit signal to extract and remodulate a split portion of the inbound data stream as the outgoing NRZ electrical signal.

14. The method of claim 13, wherein the divergent transmission signal and the convergent transmission signal are PAM4 electrical signals.

15. The method of claim 14, further comprising encapsulating transceivers in the one-terminal connectors, wherein the transceivers in the one-terminal connectors are configured to perform clock and data recovery on the input PAM4 electrical signal to extract and remodulate the inbound data stream as a divergent transport signal that transports a split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and the transceivers in the one-terminal connectors are further configured to perform clock and data recovery on the convergent transport signal to extract and remodulate the outbound data stream as the output PAM4 electrical signal.

16. An active 1: an N drop cable comprising:

the meta-connector is adapted to fit to a network interface port of a primary host device to provide a first output electrical signal conveying a multi-channel outbound data stream to the primary host device at a first symbol rate and accept a first input electrical signal conveying a multi-channel inbound data stream from the primary host device at the first symbol rate, an

Each of the split-end connectors being adapted to fit to a network interface port of a secondary host device to provide a second output electrical signal conveying a split portion of the inbound data stream to the secondary host device at a second symbol rate and to accept a second input electrical signal conveying a split portion of the outbound data stream from the secondary host device at the second symbol rate,

the second symbol rate is half of the first symbol rate.

17. The cable of claim 16, wherein the first output electrical signal, the first input electrical signal, the second output electrical signal, and the second input electrical signal are each PAM4 electrical signals.

18. The cable of claim 16, wherein the first output electrical signal, the first input electrical signal, the second output electrical signal, and the second input electrical signal are each NRZ electrical signals.

19. The cable of claim 16, wherein the meta-connector comprises a transceiver that performs clock and data recovery on the first input electrical signal to extract and remodulate an inbound data stream as a divergent transmission signal that transmits a split portion of the inbound data stream to the split-end connector via the electrical conductor, and wherein the transceiver performs clock and data recovery on a convergent transmission signal to extract and remodulate the outbound data stream as the first output electrical signal.

20. The cable of claim 19, wherein the divergent transmission signals and the convergent transmission signals use the second symbol rate.

21. The active 1: an N drop cable, wherein the transceiver in the meta-end connector further performs forward error correction when extracting the outbound data stream.

22. The cable of claim 20 wherein each of the split end connectors includes a redriver circuit that provides the second output electrical signal by amplifying the divergent transmission signals it receives, and wherein the redriver circuit provides at least one of the convergent transmission signals by amplifying the second input electrical signals it receives.

23. The cable of claim 20 wherein each of the split-end connectors includes a transceiver that performs clock and data recovery on the divergent transmission signal it receives to extract and remodulate a split portion of the inbound data stream, and wherein the transceiver in each split-end connector performs clock and data recovery on the second input electrical signal to extract and remodulate a split portion of the outbound data stream.

24. The cable of claim 23, wherein the transceiver in each split-end connector further performs forward error correction when extracting split portions of the inbound data stream.

25. The cable of claim 19 wherein the divergent transmission signal and the convergent transmission signal use the first symbol rate, wherein each of the split-end connectors includes a transceiver that performs clock and data recovery on the divergent transmission signal it receives to extract and remodulate a split portion of the inbound data stream, and wherein the transceiver in each split-end connector performs clock and data recovery on the second input electrical signal to extract and remodulate a split portion of the outbound data stream.

26. The cable of claim 25, wherein the transceiver in each split-end connector further performs forward error correction when extracting split portions of the inbound data stream.

27. The cable of claim 16, wherein each of the split-end connectors includes a transceiver that performs clock and data recovery on the second input electrical signal to extract and remodulate the split portion of the outbound data stream as one or more converged transmission signals that transmit the split portion of the inbound data stream to the meta-end connector via the electrical conductor, and wherein the transceiver performs clock and data recovery on the divergent transmission signals to extract and remodulate the split portion of the inbound data stream as the second output electrical signal.

28. The cable of claim 27, wherein the divergent transmission signal and the convergent transmission signal use the first symbol rate.

29. The cable of claim 28 wherein the meta-terminal connector comprises a transceiver that performs clock and data recovery on the first input electrical signal to extract and remodulate the inbound data stream as the divergent transport signal that transports the split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and wherein the transceiver in the meta-terminal connector performs clock and data recovery on the convergent transport signal to extract and remodulate the outbound data stream as the first output electrical signal.

30. The cable of claim 29 wherein the transceiver in the meta-port connector further performs forward error correction in extracting the outbound data stream.

31. A method of manufacturing a cable, comprising:

packaging a transceiver into a meta-terminal connector adapted to mate with a network interface port of a primary host device, the transceiver configured to provide a first output electrical signal conveying a multi-channel outbound data stream to the primary host device at a first symbol rate and accept a first input electrical signal conveying a multi-channel inbound data stream from the primary host device at the first symbol rate; and

connecting each of N split-end connectors to the meta-end connector using an electrical conductor, wherein N is an integer greater than 1, and wherein each of the split-end connectors is adapted to mate with a network interface port of a secondary host device to provide a second output electrical signal conveying split portions of the inbound data stream to the secondary host device at a second symbol rate and to accept a second input electrical signal conveying split portions of the outbound data stream from the secondary host device at the second symbol rate,

the transceiver in the meta-terminal connector is configured to perform clock and data recovery on the first input electrical signal to extract and remodulate the inbound data stream as a divergent transport signal that transports a split portion of the inbound data stream to the split-terminal connector via the electrical conductor, and the transceiver in the meta-terminal connector is further configured to perform clock and data recovery on a convergent transport signal to extract and remodulate the outbound data stream as the first output electrical signal, and

the second symbol rate is half of the first symbol rate.

32. A method of manufacturing a cable, comprising:

encapsulating transceivers into each of N split-end connectors adapted to mate with network interface ports of a secondary host device, where N is an integer greater than 1, and wherein each of the transceivers in the split-end connectors is configured to provide a split-end output electrical signal that conveys a split portion of a multi-channel inbound data stream at a second symbol rate to the secondary host device and to accept a split-end input electrical signal that conveys a split portion of a multi-channel outbound data stream from the secondary host device at the second symbol rate; and

connecting each of the split-end connectors to a meta-end connector via an electrical conductor, the meta-end connector adapted to mate with a network interface port of a primary host device to provide a meta-end output electrical signal conveying the outbound data stream to the primary host device at a first symbol rate and to accept a meta-end input electrical signal conveying the inbound data stream from the primary host device at the first symbol rate,

the transceiver in each split-end connector is configured to perform clock and data recovery on the split-end input electrical signal to extract and remodulate a split portion of the outbound data stream as a converged transmit signal that transmits the split portion of the outbound data stream to the unary-end connector via the electrical conductor, and the transceiver in each split-end connector is further configured to perform clock and data recovery on a divergent transmit signal to extract and remodulate a split portion of the inbound data stream as the split-end output electrical signal, and

the second symbol rate is half of the first symbol rate.