CN111640798A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN111640798A
CN111640798A CN201910155626.2A CN201910155626A CN111640798A CN 111640798 A CN111640798 A CN 111640798A CN 201910155626 A CN201910155626 A CN 201910155626A CN 111640798 A CN111640798 A CN 111640798A
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doped regions
semiconductor device
layer
absorbing structure
charge absorbing
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CN111640798B (en
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张睿钧
苏泊沅
廖健男
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising a charge absorption structure arranged above a substrate; an insulating layer disposed over the charge absorbing structure; a semiconductor layer disposed over the insulating layer; a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and the second doped regions extend along a first direction and are staggered along a second direction, the second direction is different from the first direction, and the first doped regions and the second doped regions have different conductivity types; the source electrode and the drain electrode are respectively arranged on two sides of the first doped regions and the second doped regions which are arranged in a staggered mode and extend along a second direction; and the grid electrode is arranged on the first doping regions and the second doping regions which are arranged in a staggered mode and extends along the second direction. When the semiconductor device is applied to high-frequency operation, the parasitic scattering phenomenon of carriers can be reduced, and the reliability of the semiconductor device is improved.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device having a super junction structure and a method for manufacturing the same.
Background
Semiconductor devices include a substrate and a circuit element disposed over the substrate, and have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras, and other electronic devices. The evolution of semiconductor devices is continuously affecting and improving human lifestyles.
Since a Metal-Oxide-Semiconductor Field-effect transistor (MOSFET) has the advantages of high switching speed, high input impedance, small driving power, excellent high-frequency characteristics, a large Safe Operating range (Safe Operating Area), and the like, the application range is wider as the manufacturing technology is more mature.
Subsequently, a mosfet having a super junction structure, such as a Vertical Diffused Metal Oxide Semiconductor (VDMOS) device, has been developed, which changes the physical limitations of the withstand voltage and the depletion region of the conventional mosfet, and achieves the advantages of reducing on-resistance (Ron). However, the complexity of the vertical channel design and fabrication process for the vertical diffused metal oxide semiconductor device also limits its applications.
Disclosure of Invention
According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device comprises a charge absorption structure arranged above a substrate; an insulating layer disposed over the charge absorbing structure; a semiconductor layer disposed over the insulating layer; a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and the second doped regions extend along a first direction and are staggered along a second direction, the second direction is different from the first direction, and the first doped regions and the second doped regions have different conductivity types; the source electrode and the drain electrode are respectively arranged on two sides of the first doped regions and the second doped regions which are arranged in a staggered mode and extend along a second direction; and the grid electrode is arranged on the first doping regions and the second doping regions which are arranged in a staggered mode and extends along the second direction.
In some embodiments, the charge absorbing structure comprises polysilicon.
In some embodiments, the thickness of the charge absorbing structure is in the range of 100 nanometers to 1000 nanometers.
In some embodiments, the semiconductor device further comprises a buffer layer covering the entire substrate.
In some embodiments, the buffer layer comprises an oxide, a nitride, or a combination of the foregoing.
In some embodiments, the charge absorbing structure covers the entire substrate, and the buffer layer covers the charge absorbing structure.
In some embodiments, the charge absorbing structure wraps around the entire substrate, and the buffer layer is located between the substrate and the charge absorbing structure.
In some embodiments, the semiconductor device further comprises an additional buffer layer encapsulating the charge absorbing structure.
In some embodiments, the semiconductor device further comprises a pair of additional charge absorbing structures through the insulating layer to contact the charge absorbing structures.
In some embodiments, the width of the pair of additional charge absorbing structures is each independently in the range of 0.5 microns to 2 microns.
According to other embodiments of the present invention, methods of fabricating semiconductor devices are provided. The method includes forming a charge absorbing structure on a substrate; forming an insulating layer over the charge absorbing structure and a semiconductor layer over the insulating layer; forming a mask layer having a plurality of openings over the semiconductor layer; implanting a portion of the semiconductor layer through the openings to form a plurality of first doped regions having the first conductivity type, wherein the first doped regions extend along a first direction; forming a plurality of field oxides through the openings to respectively cover the first doped regions; after forming the field oxides, removing the mask layer; implanting another portion of the semiconductor layer using the field oxides as a mask to form a plurality of second doped regions having a second conductivity type, wherein the second conductivity type is different from the first conductivity type, and wherein the second doped regions extend along a first direction and are staggered with the first doped regions along a second direction, wherein the second direction is different from the first direction; and removing the field oxides after forming the second doped regions.
In some embodiments, the field oxide and the mask layers are different materials.
In some embodiments, the ratio of the thickness of the masking layer to the thickness of the field oxides is in the range of 5: 1 to 10: 1, in the above range.
In some embodiments, the method further includes forming a source and a drain along a second direction on two sides of the first doped regions and the second doped regions, respectively; and forming a gate electrode on the semiconductor layer and along the second direction.
In some embodiments, the method further comprises forming a buffer layer covering the entire substrate.
In some embodiments, the forming of the buffer layer comprises depositing an oxide, a nitride, or a combination of the foregoing.
In some embodiments, the charge absorbing structure covers the entire substrate, and the buffer layer covers the entire charge absorbing structure.
In some embodiments, the charge absorbing structure wraps around the entire substrate, and the buffer layer is located between the charge absorbing structure and the substrate.
In some embodiments, the method further comprises forming an additional buffer layer to cover the entire charge absorbing structure.
In some embodiments, the method further comprises forming an additional pair of charge absorbing structures through the insulating layer to contact the charge absorbing structure.
The invention arranges the charge absorption structure on the semiconductor device to reduce the parasitic scattering phenomenon of the current carrier and improve the reliability of the semiconductor device when the semiconductor substrate covered on the insulator is applied to high-frequency operation.
Drawings
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily increased or reduced to clearly illustrate the features of the present disclosure.
Fig. 1A-1E are schematic cross-sectional views illustrating various stages in the manufacture of a semiconductor device, according to some embodiments.
Fig. 2 is a perspective schematic diagram depicting a semiconductor device according to some embodiments.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to some embodiments.
Reference numerals:
100. 200, 300, 400, 500-semiconductor device
102-substrate
104 insulating layer
106 semiconductor layer
108 sacrificial layer
110-mask
112-first doping region
113 to opening
114-first implantation process
116-field oxide layer
118-second implantation process
120 to the second doped region
122 source electrode
124-drain electrode
126 gate dielectric
128-gate electrode
130. 136-Charge absorbing Structure
132. 134 buffer layer
138-isolation structure
140 to dielectric layer
142. 144, 146-interconnect structure
A-A, B-B line segment
D1 first Direction
D2 second direction
D3 third Direction
Detailed Description
The following outlines some embodiments so that those skilled in the art may more easily understand the present invention. However, these examples are only examples and are not intended to limit the present invention. It is understood that one skilled in the art may modify the embodiments described below as desired, such as by changing the order of fabrication processes and/or including more or less steps than those described herein.
In addition, other elements may be added to the embodiments described below. For example, a description of "forming a second element on a first element" may include embodiments in which the first element is in direct contact with the second element, and may also include embodiments in which there are additional elements between the first element and the second element such that the first element and the second element are not in direct contact, and the relationship between the first element and the second element may change as the device is operated or used in different orientations. In addition, the present invention may repeat reference numerals and/or letters in the various embodiments, such repetition is for the purpose of simplicity and clarity and has not been used to indicate a relationship between the various embodiments discussed.
Semiconductor devices and methods of fabricating the same are described below, and are particularly suitable for Semiconductor devices having Semiconductor On Insulator (SOI) substrates, according to some embodiments of the present invention. The invention provides a novel manufacturing method of a super junction structure, which can precisely control an ion implantation (implantation) area, so that a semiconductor device with an insulator-on-semiconductor substrate has a novel super junction structure, thereby improving the breakdown voltage and the on-resistance while reducing the channel length. In addition, the invention provides a charge absorption structure which can reduce the parasitic effect (parasitic effect) of the semiconductor substrate on the insulator.
Fig. 1A-1E are schematic cross-sectional views illustrating various stages in the fabrication of a semiconductor device 100, according to some embodiments. As shown in fig. 1A, the semiconductor device 100 includes a substrate 102. The substrate 102 may comprise any substrate material suitable for use in the semiconductor device 100. For example, the substrate 102 may be a bulk (bulk) semiconductor substrate or comprise a composite substrate formed of different materials, and the substrate 102 may be doped (e.g., using p-type or n-type dopants) or undoped. In some embodiments, the substrate 102 may comprise an elemental semiconductor substrate, a compound semiconductor substrate, or an alloy semiconductor substrate. For example, the substrate 102 may include a silicon substrate, a germanium substrate, a silicon carbide (silicon carbide) substrate, an aluminum nitride (aluminum nitride) substrate, an aluminum oxide (aluminum oxide) substrate, a gallium nitride (gallium nitride) substrate, similar materials, or a combination thereof.
A charge absorbing structure 130 is then disposed over the substrate 102, according to some embodiments. The provision of the charge absorbing structure 130 in the semiconductor device 100 reduces parasitic effects during high frequency operation, and is therefore particularly suitable for use in semiconductor devices 100 having semiconductor-on-insulator substrates operating at high voltages (e.g., greater than 30 volts).
In some embodiments, the material of the charge absorbing structure 130 may comprise polysilicon (polysilicon), and the thickness of the charge absorbing structure 130 may be in a range of about 100 nanometers to about 1000 nanometers, such as about 300 nanometers to about 500 nanometers. In some embodiments, the charge absorbing structure 130 may be formed by a Deposition process, such as a Low Pressure Chemical Vapor Deposition (LPCVD) process or other suitable Deposition process.
Then, according to some embodiments, an insulating layer 104 is disposed over the charge absorbing structure 130 and a semiconductor layer 106 over the insulating layer 104. In some embodiments, the insulating layer 104 may comprise a buried dielectric layer, such as a Buried Oxide (BOX), a buried silicon oxide (SiO), or the like2) Silicon nitride (SiN), similar materials, or combinations of the foregoing. In some embodiments, the thickness of the insulating layer 104 may be in the range of about 3 microns to about 10 micronsAnd about, for example, about 4 microns to about 6 microns.
In some embodiments, the material of the semiconductor layer 106 may comprise silicon, and the thickness of the semiconductor layer 106 may range from about 0.5 microns to about 4 microns, such as from about 1 micron to about 1.5 microns.
In some embodiments, the insulating Layer 104 and the semiconductor Layer 106 may be formed by a wafer bonding (wafer bonding) fabrication process, an Epitaxial Layer Transfer (ELTRAN) fabrication process, a similar fabrication process, or a combination of the foregoing.
In some embodiments using a wafer bonding process, the insulating layer 104 is directly bonded to the semiconductor layer 106, both of which are then bonded to the substrate 102 over which the charge absorbing structure 130 has been formed, and the semiconductor layer 106 may be thinned prior to bonding to the substrate 102.
In some embodiments using an Epitaxial Layer Transfer (ELTRAN) process, the semiconductor layer 106 is epitaxially grown on a seed layer (not shown), and the semiconductor layer 106 is oxidized to form the insulating layer 104. After the insulating layer 104 is soldered to the substrate 102 over which the charge absorbing structure 130 has been formed, the seed layer is removed.
Then, according to some embodiments, a sacrificial layer 108 is formed over the semiconductor layer 106. The sacrificial layer 108 can prevent the surface of the semiconductor layer 106 from being contaminated, reduce damage to the semiconductor layer 106 caused by a subsequent ion implantation process, and help control the depth of the dopant into the semiconductor layer 106. In some embodiments, the formation of the sacrificial layer 108 may include a thermal oxidation (thermal oxide) fabrication process or other suitable fabrication process, and the material of the sacrificial layer 108 may include an oxide, such as silicon oxide. In some embodiments, the sacrificial layer 108 may be about 10 angstroms thick
Figure BDA0001982810380000061
To about 300 angstroms, such as about 150 angstroms to about 200 angstroms. At this thickness range, the sacrificial layer 108 may protect the surface of the semiconductor layer 106 without interfering with the subsequent ion implantation manufacturing process.
A masking layer 110 is then formed over the sacrificial layer 108, according to some embodiments. In some embodiments, the masking layer 110 may comprise a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride (silicon oxynitride), silicon carbide (silicon carbide), silicon carbide nitride (silicon carbide nitride), similar materials, or combinations thereof. In some embodiments, the formation of the masking Layer 110 may include a Deposition process, such as a Chemical Vapor Deposition (CVD) process, a spin-On-Glass (SOG) process, an Atomic Layer Deposition (ALD) process, a combination of the foregoing, or any suitable Deposition process.
Then, according to some embodiments, as shown in fig. 1B, the mask layer 110 is patterned to form a plurality of openings 113 exposing the underlying film, wherein the openings 113 correspond to the subsequent doped regions. In some embodiments, the width of each opening 113 may be in a range from about 0.1 microns to about 1 micron, such as from about 0.4 microns to about 0.6 microns. In some embodiments, the pitch of each opening 113 may be in the range of about 0.1 microns to about 1 micron, such as about 0.4 microns to about 0.6 microns.
A first implantation process 114 is then performed on the semiconductor layer 106 through the openings 113 to form a plurality of first doped regions 112 in a portion of the semiconductor layer 106, wherein the first doped regions 112 have a first conductivity type. In some embodiments, the first implantation process 114 may be performed using p-type dopants or n-type dopants. For example, the p-type dopant may be boron, aluminum, gallium, BF2And the like, and the n-type dopant may be nitrogen, phosphorus, arsenic, antimony, the like, or combinations thereof in some embodiments, the first implantation process 114 has an ion implantation concentration of about 1 × 1014cm-2To about 1 × 1017cm-2E.g. about 5 × 1015cm-2To about 1 × 1016cm-2。
Then, according to some embodiments, as shown in fig. 1C, a plurality of field oxides (field oxides) 116 are formed on the exposed portions of the sacrificial layer 108 through the openings 113 of the mask layer 110. In some embodiments, the formation of field oxide 116 may be accomplished by oxidizing a portion of semiconductor layer 106 through a thermal oxidation fabrication process or other suitable fabrication process. The thickness of field oxide 116 may range from about 100 angstroms to about 500 angstroms, such as from about 300 angstroms to about 400 angstroms. In this thickness range, the dopant of the ion implantation performed subsequently can be blocked from entering the first doping region 112 under the field oxide 116 without consuming too much of the semiconductor layer 106, so as to precisely control the range of the subsequent ion implantation.
According to some embodiments, the ratio of the thickness of masking layer 110 to the thickness of field oxide 116 is between about 5: 1 to about 10: 1, for example about 7: 1 to about 8: 1. the formation of the field oxide 116 may generate bird's beak structure at the edge of the field oxide 116, and within the thickness ratio range, the stress for forming the field oxide 116 may be reduced, the area for forming the bird's beak structure may be reduced, and the uniformity of the ion implantation concentration may be improved.
Then, according to some embodiments, as shown in FIG. 1D, the masking layer 110 is removed. A second implantation process 118 is then performed on the semiconductor layer 106 to form a plurality of second doped regions 120 in a portion of the semiconductor layer 106, wherein the second doped regions 120 have a second conductivity type, and the first conductivity type is different from the second conductivity type. In some embodiments, the first doped region 112 is p-type and the second doped region 120 is n-type. In other embodiments, the first doped region 112 is n-type and the second doped region 120 is p-type. The second implantation process 118 may be selected from the p-type dopants or the n-type dopants and implantation concentrations described above with respect to the first implantation process 114, and will not be described further.
As described above, the field oxide 116 may protect the first doped region 112 during the second implant process 118, and prevent dopants from the second implant process 118 from being implanted into the first doped region 112, so that the first doped region 112 and the second doped region 120 may be formed in a staggered arrangement, and sidewalls of the second doped region 120 may be substantially aligned with sidewalls of the field oxide 116.
Then, according to some embodiments, as shown in fig. 1E, the sacrificial layer 108 and the field oxide 116 are removed to expose the first doped region 112 and the second doped region 120. In some embodiments, the removal of sacrificial layer 108 and field oxide 116 may use an etching process, such as a wet etch process, using, for example, hydrofluoric acid (HF) or any suitable etchant.
The present invention can precisely control the ion implantation region by using the mask layer 110 and the field oxide 116 in conjunction with the first implantation process 114 and the second implantation process 118 to form the self-aligned first doped region 112 and the self-aligned second doped region 120, thereby preventing the offset (offset) region from being generated due to the shift of lithography, and thus forming the first doped region 112 and the second doped region 120 in a staggered arrangement in the semiconductor device 100.
In addition, due to the accuracy achieved by this method, the channel length of the semiconductor device 100 can be reduced while optimizing the breakdown voltage and on-resistance of the semiconductor device 100, so that the semiconductor device 100 can be widely applied and is advantageous for integration with Radio Frequency (RF) Integrated Circuits (ICs).
Fig. 2 is a perspective schematic diagram illustrating a semiconductor device 200 according to some embodiments. Fig. 1A to 1E illustrate a cross-sectional view of the semiconductor device 100, which is a cross-section taken along line a-a in fig. 2. Fig. 2 and fig. 1A to 1E describe the same elements with the same symbols, and the forming manner and materials of these elements are as described above, so the description is omitted.
As shown in FIG. 2, line segment B-B extends along a first direction D1, and line segment A-A extends along a second direction D2, wherein the first direction D1 and the second direction D2 are different. As shown in fig. 2, the first doped regions 112 and the second doped regions 120 extend along the first direction D1 and are staggered along the second direction D2. In addition, the substrate 102, the charge absorption structure 130, the insulating layer 104, and the semiconductor layer 106 are stacked along the third direction D3. In some embodiments, the first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular. In some embodiments, the included angles between the first direction D1, the second direction D2, and the third direction D3 are each independently in the range of about 80 ° to about 95 °, for example the included angle between the first direction D1 and the second direction D2 is about 85 ° to about 90 °.
According to some embodiments, as shown in fig. 2, a source 122, a drain 124, and a gate are disposed in a semiconductor device 200, wherein the gate includes a gate dielectric 126 and a gate electrode 128 over the gate dielectric 126. The source electrode 122 and the drain electrode 124 are respectively disposed on two sides of the first doped region 112 and the second doped region 120 which are staggered and extend along the second direction D2. The gate dielectric 126 and the gate electrode 128 are disposed on the first doped region 112 and the second doped region 120, and extend along the second direction D2.
In some embodiments, the source electrode 122 and the drain electrode 124 may be formed by an ion implantation process in combination with a mask layer (not shown). In some embodiments, the masking layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the masking layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, similar materials, or combinations thereof. In some embodiments, the forming of the mask layer may include spin-on coating (spin-on), chemical vapor deposition (cvd), atomic layer deposition (ald), similar deposition processes, or combinations thereof, and the mask layer may be patterned using suitable lithography techniques.
The source 122 and drain 124 have the same conductivity type. In embodiments where the metal oxide semiconductor device is p-type (PMOS), the source 122 and drain 124 are p-type. In embodiments where the metal oxide semiconductor device is n-type (NMOS), the source 122 and drain 124 are n-type. In some embodiments, the source electrode 122 and the drain electrode 124 may be formed simultaneously by one ion implantation process. In other embodiments, the source electrode 122 and the drain electrode 124 may be formed by different ion implantation processes.
The doping concentration of the source 122 and the drain 124 may be greater than or equal to the doping concentration of the first doped region 112 and the second doped region 120 in some embodiments, the source 122 and the drain 124 may each independently have about 1 × 1014cm-3To about 5 × 1017cm-3The doping concentration of (a); or may be formed together during ion implantation of the first doped region 112 or the second doped region 120.
At one endIn some embodiments, the material of the gate dielectric 126 may comprise an oxide, such as silicon dioxide. In some embodiments, the material of the gate dielectric 126 may comprise a high-k dielectric material, i.e., a dielectric material having a dielectric constant higher than 3.9. For example, the material of the gate dielectric 126 may include HfO2、LaO2、TiO2、ZrO2、Al2O3、Ta2O3、HfZrO、ZrSiO2、HfSiO4A similar high dielectric constant material, or a combination of the foregoing. The gate dielectric 126 may be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, similar deposition processes, or combinations of the foregoing.
A gate electrode 128 is then formed over the gate dielectric 126. In some embodiments, the formation of the gate electrode 128 may comprise physical Vapor deposition, chemical Vapor deposition, atomic layer deposition, Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), similar fabrication processes, or a combination of the foregoing. In some embodiments, the material of the gate electrode 128 may comprise a conductive material, such as a metal, a metal nitride, a metal oxide, a metal silicide (silicide), a semiconductor material, a similar conductive material, or a combination of the foregoing. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys thereof, multi-layered structures thereof, or combinations thereof, and the semiconductor material may include polysilicon (poly-Si), poly-germanium (poly-Ge), poly-silicon germanium (poly-SiGe), similar semiconductor materials, or combinations thereof.
Although the formation sequence of the source 122, drain 124, gate dielectric 126 and gate electrode 128 is described above, the present invention is not limited thereto, and other formation sequences may be used for these elements. In addition, the source 122, the drain 124, the gate dielectric 126 and the gate electrode 128 may be formed after the first doped region 112 and the second doped region 120 are formed, but the invention is not limited thereto, and these elements may be formed in other sequences.
In addition, the shapes of the source 122, the drain 124, the gate dielectric 126 and the gate electrode 128 are not limited to the vertical sidewalls in the drawings, and may be sloped sidewalls or sidewalls having other features. In addition, as shown in FIG. 2, the sidewalls of the gate dielectric 126 and the sidewalls of the gate electrode 128 are substantially coplanar, and these sidewalls are substantially coplanar with the sidewalls of the source 122, but the invention is not limited thereto. For example, the sidewalls of the source 122 may be between two sidewalls of the gate dielectric 126.
The substrate 102 and the charge absorbing structure 130 of the present invention may have other configurations to improve the reliability of the semiconductor device. Other example configurations of the substrate 102 and the charge absorbing structure 130 are described below according to some embodiments. For simplicity, like elements will be described with like reference numerals, and the manner and materials of formation of these elements are as described above and thus will not be described again.
Fig. 3-5 are cross-sectional schematic diagrams illustrating semiconductor devices 300, 400, and 500, according to some embodiments. Fig. 3-5 illustrate cross-sectional views of semiconductor devices 300, 400, and 500, which are cross-sections taken along line B-B of fig. 2.
According to some embodiments, as shown in fig. 3, the substrate 102 of the semiconductor device 300 includes a buffer layer 132 encapsulating the entire substrate 102. According to some embodiments, the buffer layer 132 disposed on the semiconductor device 300 may alleviate lattice difference between the substrate 102 and other layers to avoid stress induced defects due to the lattice difference. For example, the buffer layer 132 may be used to mitigate lattice differences between the substrate 102 and the charge absorbing structure 130. In addition, the buffer layer 132 may also be used to repair defects on the surface of the substrate 102, such as filling the wire holes on the surface of the substrate 102, so as to improve the crystalline quality of the surface of the substrate 102.
In some embodiments, the material of the buffer layer 132 comprises an oxide, a nitride, a similar material, or a combination of the foregoing. For example, the buffer layer 132 may include silicon oxide. According to some embodiments, the buffer layer 132 may be formed by a deposition manufacturing process, such as a low pressure chemical vapor deposition manufacturing process, prior to forming the charge absorbing structure 130. In some embodiments, the thickness of the buffer layer 132 may be in the range of about 500 angstroms to about 2000 angstroms, such as about 1000 angstroms to about 1200 angstroms. The buffer layer 132 with such a thickness range can alleviate the lattice difference between different films, improve the crystallization quality, and avoid the stress defect caused by the thickness thereof.
According to some embodiments, as shown in fig. 4, the charge absorbing structure 130 of the semiconductor device 400 encapsulates the entire substrate 102. Compared to the single-layer charge absorption structure 130 shown in fig. 1A to 1E, fig. 2 and fig. 3, the semiconductor device 400 having the charge absorption structure 130 covering the entire substrate 102 is more favorable for reducing the scattering phenomenon of carrier parasitics, and thus improves the reliability of the semiconductor device 400.
In some embodiments, the charge absorbing structure 130 may be formed by a deposition manufacturing process, such as a low pressure chemical vapor deposition manufacturing process. Although the thickness of the vertical portion and the thickness of the horizontal portion of the charge absorbing structure 130 are substantially the same in the drawings, the present invention is not limited thereto, and the thickness of the vertical portion may be greater or less than the thickness of the horizontal portion. In some embodiments, the thickness of the vertical portion and the thickness of the horizontal portion of the charge absorbing structure 130 may each independently range from about 100 nanometers to about 1000 nanometers. For example, the vertical portion has a thickness of about 250 nanometers to about 450 nanometers, and the horizontal portion has a thickness of about 300 nanometers to about 500 nanometers.
In addition, a buffer layer 132 may be disposed between the substrate 102 and the charge absorbing structure 130 to alleviate a lattice difference between the substrate 102 and the charge absorbing structure 130 and repair surface defects of the substrate 102. In addition, an additional buffer layer 134 may be disposed on the surface of the charge absorbing structure 130 to alleviate lattice differences between the charge absorbing structure 130 and other film layers and to repair surface defects of the charge absorbing structure 130. The material and formation method of the buffer layer 134 may be selected from those of the buffer layer 132, but other materials and formation methods may be used. It should be noted that the semiconductor device 400 having the buffer layer 132 and the buffer layer 134 is only an illustrative example and is not limited thereto, and for example, only one of the buffer layer 132 and the buffer layer 134 may be provided.
According to some embodiments, as shown in fig. 5, the semiconductor device 500 includes an additional pair of charge absorbing structures 136, the pair of charge absorbing structures 136 passing through the insulating layer 104 to contact the charge absorbing structure 130. The material of the charge absorbing structure 136 may be selected from the materials of the charge absorbing structure 130, but other materials may be used. In some embodiments, the width of the pair of charge absorbing structures 136 may each independently range from about 0.5 microns to about 2 microns, such as from about 1 micron to about 1.5 microns.
According to some embodiments, as shown in fig. 5, a pair of isolation structures 138 is disposed on two sides of the first doping region 112 (refer to fig. 1A to 1E and fig. 2) and the second doping region 120 which are staggered. In some embodiments, the isolation structure 138 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, similar materials, or combinations of the foregoing. The isolation structure 138 may be a Shallow Trench Isolation (STI) structure. In some embodiments, the isolation structure 138 may be formed by disposing a mask layer (not shown) to expose a predetermined position of the isolation structure 138, etching a trench (not shown) in the semiconductor layer 106 (see fig. 1A to 1E and fig. 2) by an etching process, and depositing an insulating material in the trench by a deposition process. The materials and formation of the mask layer are as described above, and thus are not described in detail. As shown in fig. 5, the charge absorbing structure 136 passes through the isolation structure 138.
According to some embodiments, a dielectric layer 140 is disposed over the semiconductor layer 106, as shown in fig. 5. In some embodiments, the dielectric layer 140 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, similar materials, or combinations thereof, and the formation of the dielectric layer 140 may comprise a Deposition process, such as a physical Vapor Deposition process, a Chemical Vapor Deposition process, an atomic layer Deposition process, a spin-on-glass process, a Flowable Chemical Vapor Deposition process (FCVD), a similar Deposition process, or combinations thereof.
According to some embodiments, as shown in fig. 5, interconnect structures 142, 144, and 146 are formed through the dielectric layer 140 to electrically connect the source 122, the gate electrode 128, and the drain 124, respectively. In some embodiments, the material of the interconnect structures 142, 144, and 146 may include a conductive material, such as a metal, a metal nitride, a metal oxide, a metal silicide, a semiconductor material, a similar conductive material, or a combination thereof. In some embodiments, a mask layer (not shown) may be formed over the dielectric layer 140 to expose predetermined positions of the interconnect structures 142, 144, and 146, and the dielectric layer 140 may be etched by an etching process to form trenches (not shown), and then a conductive material may be deposited in the trenches by a deposition process to form the interconnect structures 142, 144, and 146. The materials and formation of the mask layer are as described above, and thus are not described in detail.
In some embodiments, the trenches for forming the interconnect structures 142, 144, and 146 and the trenches for forming the charge absorbing structure 136 may be etched simultaneously by one patterning process, but the invention is not limited thereto. In other embodiments, the trenches for forming the interconnect structures 142, 144, and 146 and the trenches for forming the charge absorbing structure 136 may be etched separately by different patterning processes, and the charge absorbing structure 136 may be formed before or after the interconnect structures 142, 144, and 146 are formed.
Since the first doped regions 112 (see fig. 1A to 1E and fig. 2) and the second doped regions 120 are alternately disposed between the pair of charge absorbing structures 136, the semiconductor device 500 can more effectively reduce the scattering phenomenon due to carrier parasitics and improve the reliability of the semiconductor device 500 compared to the single-layer charge absorbing structure 130 shown in fig. 1A to 1E, fig. 2 and fig. 3 and the charge absorbing structure 130 surrounding the substrate 102 shown in fig. 4.
According to some embodiments of the present invention, the mask layer and the field oxide are used in conjunction with an ion implantation process to form the semiconductor device having the super junction structure, so that the ion implantation region can be precisely controlled in a self-aligned manner to form the first doped region and the second doped region in a staggered arrangement, thereby avoiding offset regions due to lithography shift and improving the yield of the semiconductor device. In addition, due to the precision of the method, the channel length of the semiconductor device can be reduced, and the breakdown voltage and the on-resistance can be optimized, so that the method is particularly suitable for the semiconductor device with the SOI substrate.
In addition, according to some embodiments of the present invention, a charge absorption structure is disposed in a semiconductor device to reduce the parasitic scattering of carriers and improve the reliability of the semiconductor device when the soi substrate is applied to high frequency operation.
While the invention has been described above in terms of several embodiments, these embodiments are not intended to limit the invention. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for modifying or replacing various features and advantages of the present disclosure to achieve various objectives and/or advantages similar to those achieved through the use of the present disclosure. It will also be appreciated by those skilled in the art that such modifications or arrangements do not depart from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims (20)

1. A semiconductor device, comprising:
a charge absorption structure disposed above a substrate;
an insulating layer disposed over the charge absorbing structure;
a semiconductor layer disposed over the insulating layer;
a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and the second doped regions extend along a first direction and are staggered along a second direction, the second direction is different from the first direction, and the first doped regions and the second doped regions have different conductive types;
the source electrode and the drain electrode are respectively arranged at two sides of the first doped regions and the second doped regions which are arranged in a staggered mode and extend along the second direction; and
and the grid electrode is arranged on the plurality of first doping regions and the plurality of second doping regions which are arranged in a staggered mode and extends along the second direction.
2. The semiconductor device of claim 1, wherein said charge absorbing structure comprises polysilicon.
3. The semiconductor device according to claim 1, wherein the thickness of the charge absorbing structure is in the range of 100 nm to 1000 nm.
4. The semiconductor device of claim 1, further comprising a buffer layer covering the entire substrate.
5. The semiconductor device according to claim 4, wherein the buffer layer comprises an oxide, a nitride, or a combination of an oxide and a nitride.
6. The semiconductor device according to claim 4, wherein the charge absorbing structure covers the entire substrate, and the buffer layer covers the charge absorbing structure.
7. The semiconductor device according to claim 4, wherein the charge absorbing structure covers the entire substrate, and the buffer layer is located between the substrate and the charge absorbing structure.
8. The semiconductor device of claim 7, further comprising an additional buffer layer encapsulating the charge absorbing structure.
9. The semiconductor device of claim 1, further comprising a pair of additional charge absorbing structures through the insulating layer to contact the charge absorbing structures.
10. The semiconductor device of claim 9, wherein the width of the pair of additional charge absorbing structures is independently in the range of 0.5 microns to 2 microns.
11. A method of manufacturing a semiconductor device, comprising:
forming a charge absorption structure on a substrate;
forming an insulating layer over the charge absorbing structure and a semiconductor layer over the insulating layer;
forming a mask layer having a plurality of openings over the semiconductor layer;
implanting a portion of the semiconductor layer through the plurality of openings to form a plurality of first doped regions having a first conductivity type, wherein the plurality of first doped regions extend along a first direction;
forming a plurality of field oxides through the plurality of openings to respectively cover the plurality of first doped regions;
removing the mask layer after forming the plurality of field oxides;
implanting another portion of the semiconductor layer using the plurality of field oxides as a mask to form a plurality of second doped regions having a second conductivity type, wherein the second conductivity type is different from the first conductivity type, and wherein the plurality of second doped regions extend along the first direction and are staggered with the first doped regions along a second direction, wherein the second direction is different from the first direction; and
removing the plurality of field oxides after forming the plurality of second doped regions.
12. The method of claim 11, wherein a material of the field oxides and a material of the mask layer are different.
13. The method of claim 11, wherein a ratio of a thickness of the mask layer to a thickness of the field oxides is in a range of 5: 1 to 10: 1, in the above range.
14. The method of manufacturing a semiconductor device according to claim 11, further comprising:
forming a source and a drain along the second direction on two sides of the first doped regions and the second doped regions which are staggered; and
a gate is formed on the semiconductor layer and along the second direction.
15. The method of claim 11, further comprising forming a buffer layer over the substrate.
16. The method of claim 15, wherein said forming of said buffer layer comprises depositing an oxide, a nitride, or a combination of an oxide and a nitride.
17. The method of claim 15, wherein the charge absorbing structure covers the entire substrate, and the buffer layer covers the entire charge absorbing structure.
18. The method of claim 15, wherein the charge absorbing structure covers the entire substrate, and the buffer layer is between the charge absorbing structure and the substrate.
19. The method of claim 18, further comprising forming an additional buffer layer to cover the entire charge absorbing structure.
20. The method of claim 11, further comprising forming a pair of additional charge absorbing structures, wherein the pair of additional charge absorbing structures penetrate through the insulating layer to contact the charge absorbing structure.
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