CN111639038B - Memory control method, device, storage medium and equipment of DMA controller - Google Patents

Memory control method, device, storage medium and equipment of DMA controller Download PDF

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CN111639038B
CN111639038B CN202010448196.6A CN202010448196A CN111639038B CN 111639038 B CN111639038 B CN 111639038B CN 202010448196 A CN202010448196 A CN 202010448196A CN 111639038 B CN111639038 B CN 111639038B
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address space
dma
address
memory
kernel
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CN111639038A (en
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王小军
薛兆井
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Beijing Armyfly Technology Co Ltd
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Beijing Armyfly Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a memory control method, a memory control device, a memory medium and a memory control device of a DMA controller. The method comprises the following steps: acquiring a DMA address space applied by a CPU (Central processing Unit) for the DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list. Through the technical scheme, the consistency of the cache data and the memory data can be effectively ensured, the conflict between the DMA memory and the address space of other memories is avoided, and the accuracy and the safety in the process of data transmission through the DMA are effectively ensured.

Description

Memory control method, device, storage medium and equipment of DMA controller
Technical Field
Embodiments of the present invention relate to the field of data processing, and in particular, to a memory control method, apparatus, storage medium, and device for a DMA controller.
Background
DMA (Direct Memory Access ) is an ideal way of high-speed data transfer, and DMA operation refers to data transfer between peripheral devices and system memory directly by using a DMA controller, which greatly saves the load of a CPU (Central Processing Unit ), greatly improves the utilization rate of the CPU, and is widely used in a system with a large amount of data transfer.
The DMA controller is two parallel units with the CPU. In the prior art, the CPU always accesses the data in the memory through the data cache, while the DMA controller directly accesses the memory. If the data in the memory is updated by the DMA controller and the data in the data cache is not yet updated, the value of some addresses obtained by the CPU may not be the true value in the memory, which easily causes inconsistency between the cache data and the memory data, and also easily causes overlapping address spaces of the DMA memory and the non-DMA memory, thereby causing errors in DMA operations.
Disclosure of Invention
The invention provides a memory control method, a device, a storage medium and equipment of a DMA controller, which not only can effectively ensure the consistency of cache data and memory data, but also avoid the conflict between the address space of a DMA memory and other memories, and effectively ensure the accuracy and the safety when data transmission is carried out through the DMA.
In a first aspect, an embodiment of the present invention provides a memory control method of a DMA controller, including:
acquiring a DMA address space applied by a CPU (Central processing Unit) for the DMA controller;
when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
In the above embodiment, when the DMA address space belongs to the kernel address space, converting the DMA address space into the user address space includes:
when the DMA address space belongs to the kernel address space, acquiring an address conversion rule between the kernel address space and a user address space;
and converting the DMA address space into a user address space according to the address conversion rule.
In the above embodiment, the address conversion rule includes:
the most significant bits of the starting core address of the core address space correspond to the most significant bits of the starting user address of the user address space, the other bits of the starting core address remain unchanged, wherein the other bits of the starting core address include address bits other than the most significant bits of the starting core address;
converting the DMA address space to a user address space according to the address conversion rule, comprising:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
In the above embodiment, obtaining the DMA address space applied by the central processing unit CPU for the DMA controller includes:
acquiring DMA memory configuration information;
and distributing the DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
In the above embodiment, the DMA memory configuration information includes a memory block size and a memory block number.
In a second aspect, an embodiment of the present invention further provides a memory control device of a DMA controller, including:
the DMA address space acquisition module is used for acquiring a DMA address space applied by the CPU for the DMA controller;
the address space conversion module is used for converting the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
and the address space writing module is used for writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
In the above embodiment, the address space conversion module includes:
an address conversion rule obtaining unit, configured to obtain an address conversion rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
and the address space conversion unit is used for converting the DMA address space into a user address space according to the address conversion rule.
In the above embodiment, the address conversion rule includes:
the most significant bit of the starting kernel address of the kernel address space is converted correspondingly with the most significant bit of the starting user address of the user address space, and other bits of the starting kernel address are kept unchanged, wherein the other bits of the starting kernel address comprise address bits except the most significant bit of the starting kernel address;
the address space conversion unit is used for:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
In the above embodiment, the DMA address space acquisition module is configured to:
acquiring DMA memory configuration information;
and distributing the DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
In the above embodiment, the DMA memory configuration information includes a memory block size and a memory block number.
In a third aspect, an embodiment of the present invention further provides a computer storage medium, where a computer program is stored, where the program when executed by a processor implements the memory control method of the DMA controller provided in any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, where the processor implements a memory control method of a DMA controller according to the embodiment of the present invention when the processor executes the computer program.
The memory control scheme of the DMA controller provided by the invention comprises the following steps: acquiring a DMA address space applied by a CPU (Central processing Unit) for the DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, so that the memory applied by the DMA controller and the address space of the memory applied by the CPU for other applications cannot collide, DMA operation errors are avoided, and the accuracy and the safety in data transmission through the DMA are effectively ensured. Meanwhile, because the user address space is a non-cache address space which is not mapped by the data cache, the CPU can directly access the data in the DMA memory without data cache, and the inconsistency between the cache data and the memory data is effectively avoided.
Drawings
FIG. 1 is a flow chart of a memory control method of a DMA controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure for performing data transmission between a CPU and an interaction chip based on a DMA controller according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of DMA address space distribution according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating another method for controlling a memory of a DMA controller according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating a memory control device of a DMA controller according to an embodiment of the present invention;
fig. 6 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Typical DMA operations require the processor to support a mapping of memory decode caches, also referred to as memory lookup caches (Translate Lookaside Buffers, TLB), to MMUs (Memory Management Unit, memory management units). MMU is generally a hardware circuit in CPU, or can be an independent integrated circuit, and has the main function of converting virtual address into physical address, and converting is generally completed through segment mechanism and page mechanism. A TLB, commonly known as a fast table, is part of the MMU and caches recently used page table entries (virtual to physical address mappings) of data. His appearance is to speed up access to data (memory) and reduce duplicate page table lookups.
Illustratively, the TLB entry and exit entries for the MIPS CPU of the R4000 family are shown in the following table:
entry item
VPN PageMask ASID G
Outlet item
Figure BDA0002506559820000061
Wherein, in the TLB entry, VPN represents the high order bits of the virtual address (i.e., virtual page address); the PageMask uses it to control how many bits of the virtual address are used to compare with the VPN and how many bits are passed before adding to the physical address; the decoding process of ASID for marking virtual address to physical address belongs to a specific process space; if bit G is set to 1, then the ASID match is turned off, which makes the decode entry available for all process spaces. In the entry of the TLB, the PFN (Physical Frame Number, physical page number) and some useful flags C, D, V are output. Where PFN means that the physical address matching the VPN is found by TLB, where typically the lower 12 bits are removed, i.e. 4K page aligned. The C bit is a cache control bit, indicating that there is a cache when the C bit is set to 0, and indicating that there is no cache when the C bit is set to 1. The D bit is a write control bit, the D bit is set to 1, which indicates that data is allowed to be written into the corresponding page, and the D bit is set to 0, which indicates "dirty" that data is not allowed to be written into the corresponding page; when the V position is set to 0, it indicates that the corresponding entry is not available. Obviously, in the prior art, the consistency of cache data and memory data is realized when the CPU reads and writes data by controlling the C valid bit in the TLB table entry. When a bug is designed in the C bit of the TLB table, inconsistency between the cache data and the memory data is easily caused.
Fig. 1 is a flow chart of a memory control method of a DMA controller according to an embodiment of the present invention, which may be executed by a memory control device of the DMA controller, wherein the device may be implemented by software and/or hardware, and may be generally integrated in an electronic device. As shown in fig. 1, the method includes:
and step 101, acquiring a DMA address space applied by a Central Processing Unit (CPU) for the DMA controller.
In the embodiment of the invention, before data transmission is performed through DMA, a CPU is required to apply a DMA linked list and a DMA data storage area corresponding to the DMA linked list for a DMA controller, wherein the DMA data storage area is also referred to as a DMA address space and is used for storing read-write operation data in the data transmission process through DMA. And acquiring a DMA address space applied by the CPU for the DMA controller.
102, when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache.
In the embodiment of the invention, the program address space of the CPU can be divided into a plurality of address areas, and one address space has different attributes when being in different address areas. For example, the program address space of a 32-bit CPU may be divided into a plurality of address areas of Ku, K0, K1, K2, and the like, wherein:
k1: the CPU does not access the address in the K1 through the cache, namely, the CPU does not access the data in the K1 through the cache, but directly accesses the data in the K1 through a non-cache uncache mode. K1 is also the only address space that can function properly at system restart.
K2: this address space can only be used in the core state and is translated by the MMU and is not accessed until the MMU is configured.
In the embodiment of the invention, the address area K2 may be used as a kernel address space, and the address area K1 may be used as a user address space, where the kernel address space is a cache address space mapped by a data cache, that is, an address space that needs to be indirectly accessed by a CPU through a cache, and it is understood that the kernel address space needs to be indirectly accessed by the CPU through the cache, and the CPU cannot directly access the kernel address space. The user address space is a non-cache address space which is not mapped by the data cache, namely, the CPU does not need to directly access the address space through the cache, and it is understood that the user address space does not need to be directly accessed by the CPU through the cache, and the CPU can directly access the user address space.
Illustratively, after acquiring the DMA address space applied by the CPU for the DMA controller, determining whether the DMA address space belongs to the kernel address space, and if so, converting the DMA address space from the kernel address space to the user address space.
Optionally, when the DMA address space belongs to a kernel address space, converting the DMA address space into a user address space includes: when the DMA address space belongs to the kernel address space, acquiring an address conversion rule between the kernel address space and a user address space; and converting the DMA address space into a user address space according to the address conversion rule. Optionally, the address conversion rule includes: the most significant bit of the starting kernel address of the kernel address space is converted correspondingly with the most significant bit of the starting user address of the user address space, and other bits of the starting kernel address are kept unchanged, wherein the other bits of the starting kernel address comprise address bits except the most significant bit of the starting kernel address; converting the DMA address space to a user address space according to the address conversion rule, comprising: determining an address offset between a starting DMA address of a DMA address space and the starting kernel address; and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
Illustratively, the DMA address space (i.e., DMA data memory area) applied by the CPU for the DMA controller through the malloc function is 0xC0504000-0xD0504000, and the DMA address space belongs to the kernel address space (i.e., K2 address area), and then the DMA address space is converted from the kernel address space to the user address space according to the address conversion rule between the kernel address space and the user address space. Wherein, the address conversion rule between the kernel address space and the user address space may include: the most significant bits of the starting kernel address of the kernel address space correspond to the most significant bits of the starting user address of the user address space, and the other bits of the starting kernel address remain unchanged, wherein the other bits of the starting kernel address include address bits other than the most significant bits of the starting kernel address. Taking the kernel address space as the K2 address area and the user address space as the K1 address area as an example, that is, the kernel address space is 0xC 0000000-0 xFFFFFFFF, the user address space is 0xA 0000000-0 xBFFFFFFFF, the highest bit C in the initial kernel address 0xC0000000 of the kernel address space is converted with the highest bit A in the initial user address 0xA0000000 of the user address space, other bits are kept unchanged, that is, the initial kernel address 0xC0000000 is converted into 0xA0000000, and similarly, other addresses in the kernel address space only mutually convert the highest bit with the highest bit of the address corresponding to the user address space, and other bits are kept unchanged. After the DMA address space is acquired, determining the address offset between the starting DMA address and the starting kernel address of the DMA address space, and then converting the DMA address space into the user address space according to the address offset and the address conversion rule. For example, the starting DMA address of the obtained DMA address space 0xC0504000-0xD0504000 is 0xC0504000, the address offset between the starting DMA address and the core address space is 0000504000, and the starting DMA address is converted into 0xA0504000 according to the address offset and the address conversion rule, and similarly, the ending DMA address 0xD0504000 can be converted into 0xB0504000, that is, the DMA address space 0xC0504000-0xD0504000 is converted into 0xA0504000-0xB0504000, that is, the DMA address space is converted from belonging to the core address space into the user address space.
And step 103, writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
In the embodiment of the invention, the DMA chain table can be pre-generated by the CPU according to the information such as the external storage address, the data size and the like of the data to be transmitted. The DMA linked list may be a unidirectional structure or a ring structure, and the DMA linked list may include a data source address and a destination address. Writing the converted DMA address space into a DMA linked list, so that the DMA controller performs data transmission according to the DMA linked list, namely, when the DMA controller performs data transmission, the data of the read-write operation is stored in the DMA address space stored in the DMA linked list, namely, the converted DMA address space. Because the converted DMA address space belongs to the user address space, namely the non-cache address space which is not mapped by the data cache, the CPU can directly access the data in the DMA memory without data cache, thereby not only effectively ensuring the consistency of the cache data and the memory data, but also avoiding the conflict between the DMA memory and the address space of other memories, and effectively ensuring the accuracy and the safety when the data transmission is carried out through the DMA.
The DMA linked list also includes, for example, control words such as Valid, start, end, a length Len of read and write data, and a space address Addr of a read and write operation. When Valid is set to 1, the DMA linked list is Valid, and the DMA controller can determine whether data can be written into the address space Addr according to the start flag bit or read from the address space Addr by scanning the DMA linked list, wherein the length of the read data is controlled by Len. Start is used to indicate Start of data frame transmission, end is used to indicate End of data frame transmission, wherein if the Start flag is not set to 1, data transmission is not triggered. Len represents the length of data read and written through the DMA linked list. Addr represents the address of the DMA controller for direct read and write operations. In the embodiment of the invention, when the converted DMA address space is written into the DMA chain table, the converted DMA address space is written into the Addr in the DMA chain table.
Fig. 2 is a schematic diagram of a structure for performing data transmission between a CPU and an interaction chip based on a DMA controller according to an embodiment of the present invention. As shown in fig. 2, the CPU manages the switch chip through a PCIe (Peripheral Component Interconnect Express, fast external device interconnect) interface, in which a DMA controller is provided on the switch chip, and transfer of a large amount of data between the CPU and the switch chip is realized through the DMA controller. In the embodiment of the present invention, after writing the converted DMA address space into the DMA linked list, the DMA linked list is stored in an external memory, where the external memory may be a DDR (Double Data Rate) synchronous dynamic random access memory) (as shown in fig. 2), and of course, the external memory may also be an SDRAM (Synchronous Dynamic Random Access Memory ). Alternatively, the storage space of the external memory may be divided into two parts, one part storing the DMA linked list and the other part storing the data to be transferred to the DMA memory, and the addresses of the two parts of storage space may be preset. After the DMA controller obtains the bus control right from the CPU, the DMA linked list can be read through the bus, and the data stored in the external memory is transferred to the DMA memory (i.e. the converted DMA address space) according to the DMA linked list. The bus may be a PCIE bus, or may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus. Optionally, after completing the data transmission corresponding to the DMA linked list, the DMA controller may release the bus control right to the CPU.
The memory control method of the DMA controller provided by the invention comprises the following steps: acquiring a DMA address space applied by a CPU (Central processing Unit) for a DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and the user address space is the non-cache address space which is not mapped by the data cache, so that the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency between the cache data and the memory data, but also solving the technical problem that the DMA memory conflicts with the address space of the memory applied by the CPU for other applications, and effectively ensuring the correctness and the safety when the data transmission is carried out through the DMA.
In some embodiments, obtaining the DMA address space applied by the central processing unit CPU for the DMA controller includes: acquiring DMA memory configuration information; and distributing the DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information. The arrangement has the advantage that the problem of a large amount of memory fragments caused by frequent operation in dynamic allocation of the DMA memory can be effectively avoided.
In the embodiment of the invention, the application of the DMA address space and the application of the non-DMA address space are random, namely the application of the DMA memory and the non-DMA memory are random, the situation that the DMA memory and the non-DMA memory cross occurs easily, and the situation that the CPU cross accesses the DMA memory and the non-DMA memory easily occurs when the CPU reads the data in the DMA memory. In particular, when the technical scheme provided by the embodiment of the invention takes the non-cache address space as the DMA memory, if the CPU reads the non-DMA memory data through the cache, the data in the non-cache address space is easily destroyed when the DMA memory crosses the non-DMA memory. And if DMA memory is dynamically allocated frequently, memory fragmentation may also result. Therefore, when the CPU applies for the DMA address space for the DMA controller, the CPU acquires the DMA memory configuration information, and allocates the DMA address space matched with the DMA memory configuration information for the DMA controller at one time according to the DMA memory configuration information. The DMA memory configuration information includes a memory block size and a memory block number. It can be appreciated that the DMA controller is allocated DMA memory matching the size and number at a time according to the number of blocks and the block size in the DMA memory configuration information, wherein the DMA memory is a large continuous address space.
Exemplary, fig. 3 is a schematic diagram of DMA address space distribution according to an embodiment of the present invention. In fig. 3, the left diagram is a memory distribution diagram of random application of DMA memory and non-DMA memory, and the right diagram is a memory distribution diagram of centralized application of DMA memory. As shown in fig. 3, the memory 2 and the memory 5 are DMA memories that require DMA operations, the memory 1, the memory 4 and the memory 6 are normal memories, i.e., non-DMA memories, and the memory 3 is a memory fragment. Obviously, based on the technical scheme provided by the embodiment of the invention, the DMA memory can be applied to the continuous address space in a one-time centralized manner, so that the problem of a large amount of memory fragments caused by frequent operation during dynamic allocation of the DMA memory can be effectively avoided, and the situation that a CPU (Central processing Unit) cross accesses the DMA memory and the non-DMA memory can be greatly reduced.
Of course, after the DMA controller is allocated with the DMA address space matched with the DMA memory configuration information at one time according to the DMA memory configuration information, whether the continuous DMA address space applied in the centralized way belongs to the kernel address space can be further judged, if yes, the DMA address space can be converted into the user address space, that is, the DMA address space applied by the DMA controller is the continuous non-cache address space which is allocated in the centralized way at one time. The method not only can effectively ensure the consistency of the cache data and the memory data, but also solves the technical problem that the data in the non-cache address space is easily damaged when the CPU reads the non-DMA memory data through the cache and the DMA memory is crossed with the non-DMA memory.
Fig. 4 is a flow chart of another memory control method of a DMA controller according to an embodiment of the present invention, as shown in fig. 4, the method includes the following steps:
step 401, obtaining DMA memory configuration information.
The DMA memory configuration information includes a memory block size and a memory block number.
Step 402, a DMA address space matched with the DMA memory configuration information is allocated to the DMA controller at one time according to the DMA memory configuration information.
Step 403, when the DMA address space belongs to the kernel address space, obtaining an address conversion rule between the kernel address space and the user address space.
Wherein the address translation rule includes: the most significant bits of the starting core address of the core address space correspond to the most significant bits of the starting user address of the user address space, and the other bits of the starting core address remain unchanged, wherein the other bits of the starting core address include address bits other than the most significant bits of the starting core address.
Step 404, determining an address offset between the starting DMA address of the DMA address space and the starting kernel address.
Step 405, converting the DMA address space to a user address space according to the address offset and the address conversion rule.
The kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache.
Step 406, writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
The memory control method of the DMA controller provided by the invention further judges whether the continuous DMA address space applied in the centralized way belongs to the kernel address space after the DMA address space matched with the DMA memory configuration information is allocated for the DMA controller at one time according to the DMA memory configuration information, and if so, the DMA address space can be converted into the user address space, namely the DMA address space applied by the DMA controller is the continuous non-cache address space allocated in the centralized way at one time. The method not only can effectively ensure the consistency of the cache data and the memory data, solves the technical problem that the DMA memory conflicts with the address space of the memory applied by the CPU for other applications, effectively ensures the correctness and the safety when the data transmission is carried out through the DMA, but also solves the technical problem that the CPU reads the non-DMA memory data through the cache, and the data in the non-cache address space is easily damaged when the DMA memory and the non-DMA memory cross each other, and simultaneously effectively avoids the problem of a large amount of memory fragments caused by frequent operation when the DMA memory is dynamically allocated.
Fig. 5 is a block diagram of a memory control device of a DMA controller according to an embodiment of the present invention, where the device may be implemented by software and/or hardware, and is generally integrated in an electronic device, and may perform DMA memory control by executing a memory control method of the DMA controller. As shown in fig. 5, the apparatus includes:
a DMA address space obtaining module 501, configured to obtain a DMA address space applied by a CPU for the DMA controller;
an address space conversion module 502, configured to convert the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
and the address space writing module 503 is configured to write the converted DMA address space into a DMA linked list, so that the DMA controller performs data transmission according to the DMA linked list.
The invention provides a memory control device of a DMA controller, which acquires a DMA address space applied by a CPU (central processing unit) for the DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and because the user address space is a non-cache address space which is not mapped by the data cache, the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency between the cache data and the memory data, but also solving the technical problem that the DMA memory conflicts with the address space of the memory applied by the CPU for other applications, and effectively ensuring the correctness and the safety when the data transmission is carried out through the DMA.
Optionally, the address space conversion module includes:
an address conversion rule obtaining unit, configured to obtain an address conversion rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
and the address space conversion unit is used for converting the DMA address space into a user address space according to the address conversion rule.
Optionally, the address conversion rule includes:
the most significant bit of the starting kernel address of the kernel address space is converted correspondingly with the most significant bit of the starting user address of the user address space, and other bits of the starting kernel address are kept unchanged, wherein the other bits of the starting kernel address comprise address bits except the most significant bit of the starting kernel address;
the address space conversion unit is used for:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
Optionally, the DMA address space acquisition module is configured to:
acquiring DMA memory configuration information;
and distributing the DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
Optionally, the DMA memory configuration information includes a memory block size and a memory block number.
Embodiments of the present invention also provide a storage medium containing computer-executable instructions, which when executed by a computer processor, are for performing a memory control method of a DMA controller, the method comprising:
acquiring a DMA address space applied by a CPU (Central processing Unit) for the DMA controller;
when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list.
Storage media-any of various types of memory devices or storage devices. The term "storage medium" is intended to include: mounting media such as CD-ROM, floppy disk or tape devices; computer system memory or random access memory, such as DRAM, DDRRAM, SRAM, EDORAM, rambus (Rambus) RAM, etc.; nonvolatile memory such as flash memory, magnetic media (e.g., hard disk or optical storage); registers or other similar types of memory elements, etc. The storage medium may also include other types of memory or combinations thereof. In addition, the storage medium may be located in a first computer system in which the program is executed, or may be located in a second, different computer system connected to the first computer system through a network such as the internet. The second computer system may provide program instructions to the first computer for execution. The term "storage medium" may include two or more storage media that may reside in different locations (e.g., in different computer systems connected by a network). The storage medium may store program instructions (e.g., embodied as a computer program) executable by one or more processors.
Of course, the storage medium containing the computer executable instructions provided in the embodiments of the present invention is not limited to the memory control operation of the DMA controller described above, and may also perform the related operations in the memory control method of the DMA controller provided in any embodiment of the present invention.
The embodiment of the invention provides an electronic device, and the memory control device of the DMA controller provided by the embodiment of the invention can be integrated in the electronic device. Fig. 6 is a block diagram of an electronic device according to an embodiment of the present invention. The electronic device 600 may include: the memory 601, the processor 602 and the computer program stored in the memory 601 and capable of being executed by the processor, the processor 602 implements the memory control method of the DMA controller according to the embodiment of the invention when executing the computer program. The electronic equipment provided by the embodiment of the invention acquires the DMA address space applied by the CPU as the DMA controller; when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache; and writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list. In the technical scheme provided by the embodiment of the invention, when the DMA address space applied by the CPU for the DMA controller belongs to the kernel address space, the DMA address space is converted into the user address space from the kernel address space, and because the user address space is a non-cache address space which is not mapped by the data cache, the CPU can directly access the data in the DMA memory without the data cache, thereby not only effectively avoiding the inconsistency between the cache data and the memory data, but also solving the technical problem that the DMA memory conflicts with the address space of the memory applied by the CPU for other applications, and effectively ensuring the correctness and the safety when the data transmission is carried out through the DMA.
The memory control device, the storage medium and the equipment of the DMA controller provided in the above embodiments can execute the memory control method of the DMA controller provided in any embodiment of the present invention, and have the corresponding functional modules and beneficial effects of executing the method. Technical details not described in detail in the above embodiments may be referred to the memory control method of the DMA controller according to any embodiment of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (6)

1. A memory control method of a DMA controller, comprising:
acquiring a DMA address space applied by a CPU (Central processing Unit) for the DMA controller;
when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list;
when the DMA address space belongs to the kernel address space, converting the DMA address space into a user address space comprises the following steps:
when the DMA address space belongs to the kernel address space, acquiring an address conversion rule between the kernel address space and a user address space;
converting the DMA address space into a user address space according to the address conversion rule;
the address translation rule includes:
the most significant bit of the starting kernel address of the kernel address space is converted correspondingly with the most significant bit of the starting user address of the user address space, and other bits of the starting kernel address are kept unchanged, wherein the other bits of the starting kernel address comprise address bits except the most significant bit of the starting kernel address;
converting the DMA address space to a user address space according to the address conversion rule, comprising:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
2. The method of claim 1, wherein obtaining a DMA address space that a central processing unit CPU applies for the DMA controller, comprises:
acquiring DMA memory configuration information;
and distributing the DMA address space matched with the DMA memory configuration information to the DMA controller at one time according to the DMA memory configuration information.
3. The method of claim 2, wherein the DMA memory configuration information includes a memory block size and a memory block number.
4. A memory control device of a DMA controller, comprising:
the DMA address space acquisition module is used for acquiring a DMA address space applied by the CPU for the DMA controller;
the address space conversion module is used for converting the DMA address space into a user address space when the DMA address space belongs to a kernel address space; the kernel address space is a cache address space mapped by the data cache, and the user address space is a non-cache address space not mapped by the data cache;
the address space writing module is used for writing the converted DMA address space into a DMA linked list so that the DMA controller performs data transmission according to the DMA linked list;
wherein, the address space conversion module includes:
an address conversion rule obtaining unit, configured to obtain an address conversion rule between a kernel address space and a user address space when the DMA address space belongs to the kernel address space;
an address space conversion unit for converting the DMA address space into a user address space according to the address conversion rule;
the address translation rule includes:
the most significant bit of the starting kernel address of the kernel address space is converted correspondingly with the most significant bit of the starting user address of the user address space, and other bits of the starting kernel address are kept unchanged, wherein the other bits of the starting kernel address comprise address bits except the most significant bit of the starting kernel address;
the address space conversion unit is used for:
determining an address offset between a starting DMA address of a DMA address space and the starting kernel address;
and converting the DMA address space into a user address space according to the address offset and the address conversion rule.
5. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a memory control method of a DMA controller according to any of claims 1-3.
6. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable by the processor, the processor implementing a memory control method for a DMA controller according to any of claims 1-3 when executing the computer program.
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CN101446931A (en) * 2008-12-03 2009-06-03 中国科学院计算技术研究所 System and method for realizing consistency of input/output data
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