CN111638899A

CN111638899A - Method for upgrading FPGA program through DSP serial port

Info

Publication number: CN111638899A
Application number: CN202010368447.XA
Authority: CN
Inventors: 龚健; 刘钊; 余婕; 陆一言; 丁力
Original assignee: Nanjing University of Science and Technology
Current assignee: Nanjing University of Science and Technology
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-09-08

Abstract

The invention discloses a method for upgrading an FPGA program through a DSP serial port.A host computer reads a programming file and extracts useful information in the programming file; the upper computer sends useful information to the DSP through the serial port; the DSP processes the received content and identifies the information such as address, data and the like contained in the content; and the DSP writes the FLASH in the FPGA in an SPI communication mode according to the read-write rule of the FLASH chip. The invention can realize the program update of the FPGA only by a single serial port without accessing a simulator, provides a simple, convenient and reliable upgrading scheme for closed equipment which is inconvenient to disassemble, and has important application value.

Description

Method for upgrading FPGA program through DSP serial port

Technical Field

The invention relates to an FPGA program updating technology, in particular to a method for upgrading an FPGA program through a DSP serial port.

Background

In recent years, DSP digital signal processing chips are applied to various fields with the characteristics of fast speed, high precision, etc., but in some large and complex application scenarios, on-chip resources of the DSP cannot meet the requirements of practical application. The application of a Field Programmable Gate Array (FPGA) makes up the defect, the FPGA is matched with the DSP for use, the functions of the DSP are greatly expanded, and the practical application is more flexible and richer. In power electronic equipment, a digital hardware system of DSP + FPGA has been widely used due to its superiority.

As technology develops and user demands increase, early developed software has some disadvantages and shortcomings, and needs to update or modify device programs. Under the condition that the hardware platform meets the existing application requirements, the equipment program is upgraded, so that the actual requirements are met, and the cost can be saved.

The DSP program upgrading mode has various SCI, SPI, CAN and other modes, and when the DSP program is upgraded, the DSP program CAN be upgraded only by reserving the interfaces outside the equipment and switching to the guide mode. However, for FPGA, the update program can only be programmed through the JTAG port of the emulator connecting the PC and the control board. If the equipment needs to be disassembled under a closed condition, the workload is large, the operation is complex, and the traditional program upgrading method has great limitation. Therefore, a method for upgrading the FPGA program on line is needed.

Disclosure of Invention

The invention aims to provide a method for upgrading an FPGA program through a DSP serial port.

The technical solution for realizing the purpose of the invention is as follows: a method for upgrading an FPGA program through a DSP serial port comprises the following steps:

(1) reading the programming file and extracting useful information from the programming file by the upper computer;

(2) the upper computer sends useful information to the DSP through the serial port;

(3) the DSP processes the received content and identifies the information such as address, data and the like contained in the content;

(4) and the DSP writes the FLASH in the FPGA in an SPI communication mode according to the read-write rule of the FLASH chip.

In the step (1), programming software of the FPGA generates a programming file after the program is successfully compiled, the content of the programming file is composed of a plurality of 16-system data, each data segment is ended by a semicolon, and each data segment contains information such as data type, address, data length, data content, check code and the like.

The upper computer reads the content of the programming file, the read data is in an ASCII code form and is reduced into 16-bit numbers, two adjacent 16-bit numbers form an 8-bit binary number, the binary number is sequentially stored in an array, and the length of the array is recorded. The semicolon and the line feed symbol exist between each segment of data, the semicolon and the line feed symbol are used as the termination symbols of each segment of data, and the useless information is only used as the marks for separating the data and is not stored in an array.

And (3) in the step (2), a serial port communication mode and an RS-485 bus protocol are adopted between the upper computer and the DSP. The DSP completes the configuration of the SCI module, and the upper computer configures the corresponding baud rate and the COM port distributed by the PC. Before starting data transmission, the upper computer sends a group of self-defined data, and the DSP judges that the data are received and then enters a program upgrading mode and responds to the upper computer. After the handshake is finished, the upper computer starts to transmit an upgrading program, and the DSP responds to the upper computer when receiving a group of data until the data transmission is finished.

And (4) in the step (3), the DSP identifies the array sent from the upper computer, and judges the array type according to the key frame in the array. If the group of data belongs to the segment address code, the DSP extracts the segment address information; if the data code belongs to the data code, the DSP extracts the address in the segment and the information of the data content; if the code belongs to the end code, the DSP returns an upgrade end instruction to the upper computer. Wherein the segment address and the address within the segment are combined into a complete data storage address.

In the step (4), the DSP and the FLASH chip of the FPGA adopt an SPI communication mode, and the FPGA is closed before the FLASH chip is operated, so that the phenomenon of 'putting the shelf' caused by the fact that the DSP and the FPGA operate the FLASH simultaneously is prevented. The DSP needs to erase the original data stored in the FLASH chip, and then writes the corresponding data content into the designated address according to the read-write rule of the FLASH chip. And after the data writing is finished, the FPGA is restarted to finish the program upgrading. The on and off of the FPGA can be controlled by an IO port of the DSP which is connected with an enabling pin of a chip of the FPGA.

Compared with the prior art, the invention can realize the program updating of the FPGA only by a single serial port without accessing a simulator, provides a simple, convenient and reliable upgrading scheme for closed equipment which is inconvenient to disassemble, occupies less resources and has important application value.

Drawings

Fig. 1 is a schematic view of the communication structure between the upper computer and the lower computer and the internal communication structure of the lower computer.

Fig. 2 is a schematic diagram of a structure of a communication frame.

FIG. 3 is a flowchart illustrating a software upgrading method according to the present invention.

Detailed Description

In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and specific embodiments.

The online upgrade scheme for upgrading the FPGA program through the DSP serial port in the embodiment is described with reference to fig. 1, taking a combination platform of the DSP chip TMS320F28335, the FPGA chip XC3S250E, and the FLASH chip M25P16 matched with the combination platform as an example. It should be understood that the description of the specific embodiments is intended to be illustrative of the invention and not to limit the invention.

Fig. 2 is a flow chart of a software upgrading method, and the main upgrading scheme includes the following steps:

(1) connecting the external serial port of the lower computer with the PC, opening the upper computer, configuring the Baud rate and the COM port distributed by the PC, and selecting the file to be programmed. The programming file is obtained by successfully compiling the program compiling software of the FPGA, the FPGA of the saint corporation is used in the embodiment, the compiling software is ISE, and the format of the obtained programming file is mcs. The content is multi-segment data code, each segment of data code is ended by a semicolon and a line-feed symbol, and each segment of data contains information such as segment address, data length, data content, check code and the like.

The upper computer is used for reading the information in the mcs file, storing the useful information in an array and removing useless information, such as a line feed symbol and a semicolon between each group of data. When the mcs file is read by the upper computer, the read ASCII code is in an ASCII code form, the upper computer converts the ASCII code into 16-system numbers, and two adjacent 16-system numbers form data of one byte and store the data in an array. Each array can be regarded as a group of communication frames, and the format of the communication frames is shown in fig. 3, and the communication frames sequentially have the length of 1 byte, the address of 2 bytes, the type of 1 byte, the data of 0-255 bytes and the CRC check of 1 byte. In the type information, "00H" indicates a data code, "01H" indicates an end code, and "04H" indicates a segment address code.

(2) Before starting to transmit the upgrading program, the upper computer sends a section of custom data of 10 bytes to the DSP, and the DSP receives and verifies the section of custom data. If the DSP does not receive or accept error data, exiting the programming program; and if the DSP judges that the section of instruction is completely received, entering an FPGA program programming mode, and returning 'HANDSHAKE _ OK' to the upper computer.

After the handshake is finished, the upper computer sends an erasing instruction, after the DSP receives the erasing instruction, the FPGA is closed, the FLASH chip is erased, and the ERASE _ OK is returned after the erasing is successful; if the erasure fails, the erasure instruction is executed again, the counter is increased by one, if the erasure fails for more than three times, the programming program is quitted, and the erasure error is reported.

After the successful erasing, the upper computer sends an upgrading program, and the DSP receives the group of data to judge the zone bit. If the fourth byte is '04H', the fourth byte is a segment address code, segment address information in the segment address code is extracted, and the fourth byte returns 'TX _ ELA' to the upper computer; if the fourth byte is '00H', the fourth byte is represented as a data code, the DSP extracts the address and data information in the data code, takes the obtained address as a low bit, takes the section address obtained before as a high bit, forms a complete data address and sends 'TX _ PROG _ OK' to the upper computer; if the fourth byte is '01H', the DSP returns to the upper computer 'TX _ PROG _ COMPETE'. And after receiving the TX _ ELA and the TX _ PROG _ OK, the upper computer continues to send the next group of data, and after receiving the TX _ PROG _ COMPETE, the upper computer displays that the upgrading is finished.

The above "HANDSHAKE _ OK", "ERASE _ OK", "TX _ PROG _ complete", etc. are macro definitions and can be represented by one byte of different data.

(3) The DSP needs to refer to the read-write rule of the chip for the FLASH operation. According to the FLASH chip M25P16 used in this embodiment, the following commands WREN (06H) write enable, PP (02H) write, SE (D8H) area erase, READ (03H) READ are used for the DSP operation on the FLASH chip. Wherein, before each SE (D8H) area erasing and PP (02H) writing operation, a WREN (06H) writing enabling instruction is needed to set a writing enabling bit (WEL).

Before writing new data into the FLASH chip, the original data needs to be erased, and the SE (D8H) area erasing is called to complete. After the chip selection signal of the FLASH chip is pulled down, the DSP writes the region erasing instruction and the segment address into the FLASH chip in sequence through the SPI to complete the erasing operation of the FLASH. The SE (D8H) area erasing command can complete the erasing of one segment, and the program in the FLASH occupies three segments, and the erasing command needs to be called three times.

The erase operation is completed and the PP (02H) write operation is invoked to write the new data. After the chip selection type is pulled down, the write command, the data address and the data content are written, and the chip selection signal is pulled up after the completion. After the entire PP (02H) write operation is completed, the write enable bit (WEL) is cleared. After PP (02H) write operation, READ (03H) READ operation is called, new data is READ from a data address for comparison, one-time verification is carried out, and the accuracy of programming is guaranteed. If the verification is failed, the data is written again, and the programming program is quitted after three times of writing failures.

And after all new data are written into the FLASH chip and are verified, the DSP enables the FPGA again, and the FPGA runs a new program in the FLASH chip to finish the program upgrading work.

Claims

1. A method for upgrading an FPGA program through a DSP serial port comprises the following steps:

2. The method for upgrading the FPGA program through the DSP serial port as recited in claim 1, wherein the programming file is generated by programming software of the FPGA after the program is successfully compiled, the content of the programming file is composed of a plurality of sections of 16-system data, each section of data is terminated by a semicolon, and each section of data comprises data type, address, data length, data content and check code information.

3. The method for upgrading the FPGA program through the DSP serial port as recited in claim 1, wherein the upper computer reads the contents of the programming file, the read data is in an ASCII code form and is restored to 16-system numbers, two adjacent 16-system numbers form an 8-bit binary number, the binary number is sequentially stored in the array, and the length of the array is recorded; the semicolon and the line feed symbol exist between each segment of data, the semicolon and the line feed symbol are used as the termination symbols of each segment of data, and the useless information is only used as the marks for separating the data and is not stored in an array.

4. The method for upgrading the FPGA program through the DSP serial port according to claim 1, wherein a serial port communication mode and an RS-485 bus protocol are adopted between the upper computer and the DSP, the DSP completes the configuration of the SCI module, and the upper computer configures the corresponding Baud rate and the COM port distributed by the PC; before starting data transmission, the upper computer sends a group of self-defined data, and the DSP judges that the data is received and then enters a program upgrading mode and responds to the upper computer; after the handshake is finished, the upper computer starts to transmit an upgrading program, and the DSP responds to the upper computer when receiving a group of data until the data transmission is finished.

5. The method for upgrading the FPGA program through the DSP serial port as claimed in claim 1, wherein the DSP identifies an array sent from the upper computer, judges the array type according to a key frame therein, and extracts segment address information therein if the array belongs to a segment address code; if the data code belongs to the data code, the DSP extracts the address in the segment and the information of the data content; if the address belongs to the end code, the DSP returns an upgrade end instruction to the upper computer, wherein the segment address and the address in the segment are combined into a complete data storage address.

6. The method for upgrading the FPGA program through the DSP serial port according to claim 1 or is characterized in that an SPI communication mode is adopted between the DSP and a FLASH chip of the FPGA, and the FPGA is closed before the FLASH chip is operated, so that the phenomenon of 'putting the shelf' caused by the fact that the DSP and the FPGA operate FLASH at the same time is prevented; the DSP operates the FLASH chip, the original data stored in the FLASH chip needs to be erased firstly, and then the corresponding data content is written in the designated address according to the read-write rule of the FLASH chip; after the data writing is finished, the FPGA is restarted to finish the program upgrading; the on and off of the FPGA is controlled by an IO port of the DSP which is connected with an enabling pin of a chip of the FPGA.