CN111634882B - Silicon-based solid-state nanopore, preparation method thereof and silicon-based solid-state nanopore sequencer - Google Patents
Silicon-based solid-state nanopore, preparation method thereof and silicon-based solid-state nanopore sequencer Download PDFInfo
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00119—Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y15/00—Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- C—CHEMISTRY; METALLURGY
- C12—BIOCHEMISTRY; BEER; SPIRITS; WINE; VINEGAR; MICROBIOLOGY; ENZYMOLOGY; MUTATION OR GENETIC ENGINEERING
- C12Q—MEASURING OR TESTING PROCESSES INVOLVING ENZYMES, NUCLEIC ACIDS OR MICROORGANISMS; COMPOSITIONS OR TEST PAPERS THEREFOR; PROCESSES OF PREPARING SUCH COMPOSITIONS; CONDITION-RESPONSIVE CONTROL IN MICROBIOLOGICAL OR ENZYMOLOGICAL PROCESSES
- C12Q1/00—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions
- C12Q1/68—Measuring or testing processes involving enzymes, nucleic acids or microorganisms; Compositions therefor; Processes of preparing such compositions involving nucleic acids
- C12Q1/6869—Methods for sequencing
Abstract
The invention discloses a silicon-based solid nanopore, a preparation method and a silicon-based solid nanopore sequencer, wherein the method comprises the following steps: forming a sandwich structure of a polycrystalline silicon layer and a dielectric layer on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel. According to the embodiment of the invention, a silicon-based semiconductor wafer manufacturing technology is used as a support, so that the preparation of the silicon-based solid nano-hole can be compatible with a CMOS integrated circuit manufacturing technology, and a manufacturing technology is provided for the integration of batch CMOS and solid nano-holes; in addition, the solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
Description
Technical Field
The invention relates to the field of gene detection, in particular to a silicon-based solid nanopore, a preparation method thereof and a silicon-based solid nanopore sequencer.
Background
Nanopore sequencing is the use of electrophoresis to transport an unknown sample through a pore with a diameter on the order of nanometers, in an electrolyte solution. The current in the nanopore sequencer was observed when a constant electric field was applied across the nanopore. The current density at the surface of the silicon-based solid-state nanopore depends on the size of the nanopore and the composition of DNA (deoxyribose nucleic Acid) or RNA (Ribonucleic Acid) occupying the nanopore. When DNA or RNA passes through the solid-state nanopore, the current flowing through the silicon-based solid-state nanopore changes in current density according to the blocking degree of the nanopore by the DNA or RNA, so that the DNA or RNA sequencing is performed according to the current density.
The current nanopore and its DNA sequencing technology are: biological nanopores (e.g., alpha-soluble nanopores, mycobacterial sporozoite a nanopores). However, such a biological nanopore incorporates proteins when in use, and the biological nanopore cannot be further precisely adjusted to control the size and consistency of the nanopore, so that DNA or RNA sequencing accuracy is inaccurate, and DNA or RNA sequencing accuracy and accuracy are affected. The success rate of nanopore sequencing is influenced, and the time for DNA or RNA sequencing is increased.
Disclosure of Invention
In view of this, the embodiment of the invention provides a silicon-based solid-state nanopore and a preparation method thereof, and a silicon-based solid-state nanopore sequencer, which rely on a silicon-based semiconductor wafer manufacturing technology, so that the preparation of the silicon-based solid-state nanopore can be compatible with a CMOS integrated circuit manufacturing technology, and a manufacturing technology is provided for batch CMOS and solid-state nanopore integration; in addition, the solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
The technical scheme adopted by the invention for solving the technical problems is as follows:
according to an aspect of an embodiment of the present invention, there is provided a method for preparing a silicon-based solid-state nanopore, the method including:
forming a sandwich structure of a polycrystalline silicon layer and a dielectric layer on a silicon substrate by adopting a silicon-based thin film growth etching technology;
forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology;
forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD;
and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel.
In one possible design, the forming a sandwich structure of a polysilicon layer and a dielectric layer on a silicon substrate by using a silicon-based thin film growth etching technology includes:
carrying out first polycrystalline silicon deposition on a silicon substrate of a wafer to form a first polycrystalline silicon layer;
performing oxide deposition on the first polysilicon layer to form a dielectric layer;
and carrying out second-time polycrystalline silicon deposition on the dielectric layer to form a second polycrystalline silicon layer, thereby forming a sandwich structure of the first polycrystalline silicon layer, the dielectric layer and the second polycrystalline silicon layer.
In one possible design, the micro fluid channels are formed on the wafer by using a Through Silicon Via (TSV) technology; the method comprises the following steps:
carrying out TSV imaging and etching on the back of the wafer;
oxide etching and two-sided He+Ion implantation;
carrying out titanium Ti deposition on the back of the wafer;
carrying out titanium deposition and titanium silicification on the front surface of the wafer to form titanium silicide;
through the above operation, a microfluidic channel is formed on the wafer.
In one possible design, micro-fluidic channels may also be formed on the wafer using micro-electro-mechanical systems (MEMS) technology.
In one possible design, the forming a dielectric layer pinhole in a dielectric layer using ESD includes:
applying electrostatic discharge ESD in the dielectric layer;
and performing oxide breakdown in the dielectric layer to form a dielectric layer pinhole.
In one possible design, a high voltage ultrashort pulse may also be used to form a dielectric layer pinhole in the dielectric layer.
In one possible design, the forming a suspended nano-scale pinhole penetrating through the dielectric layer to the microfluidic channel by performing the wet etching on the dielectric layer pinhole includes:
carrying out titanium silicide etching to remove the titanium silicide formed on the wafer;
TMAH etching is carried out on the dielectric layer pinholes to form suspended nanometer-scale pinholes which penetrate through the dielectric layer to the micro fluid channel.
In one possible design, the method further includes: a pad oxide layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology and is used for reducing the leakage current between an upper electrode and a lower electrode of a nanopore when the silicon-based solid nanopore is subjected to gene sequencing.
In one possible design, the method further includes: and depositing a layer of pinhole size adjusting film on the nano-scale pinholes of the dielectric layer, wherein the adjusting film is used for further adjusting the size of the nano-scale pinholes.
According to another aspect of the embodiments of the present invention, there is provided a silicon-based solid-state nanopore, which is prepared by applying the method for preparing a silicon-based solid-state nanopore according to any one of the embodiments of the present invention, the silicon-based solid-state nanopore including: a silicon substrate, a polysilicon layer and a dielectric layer; wherein:
the polycrystalline silicon layer is formed on the silicon substrate by adopting a silicon-based thin film growth etching technology, and the dielectric layer is formed on the polycrystalline silicon layer by adopting the silicon-based thin film growth etching technology, so that a sandwich structure of the polycrystalline silicon layer and the dielectric layer is formed on the silicon substrate; further, forming a microfluidic channel on the wafer by using a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel.
According to another aspect of the embodiments of the present invention, there is provided a silicon-based solid-state nanopore sequencer including the silicon-based solid-state nanopore according to any one of the embodiments of the present invention, the silicon-based solid-state nanopore sequencer being configured to perform DNA and/or RNA sequencing.
Compared with the related art, the silicon-based solid-state nanopore and the preparation method thereof and the silicon-based solid-state nanopore sequencer provided by the embodiment of the invention comprise the following steps: forming a sandwich structure of a polycrystalline silicon layer and a dielectric layer on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel. According to the embodiment of the invention, a silicon-based semiconductor wafer manufacturing technology is used as a support, and a sandwich structure of a polycrystalline silicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel; thereby making the preparation of the silicon-based solid state nanopore compatible with CMOS integrated circuit manufacturing technology and providing manufacturing technology for batch CMOS and solid state nanopore integration. And, through the control to the breakdown voltage and current of the electrostatic discharge ESD, can control the size and uniformity of the solid-state nanopore accurately. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
Drawings
Fig. 1 is a schematic flow chart of a method for preparing a silicon-based solid nanopore according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a silicon-based solid-state nanopore according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a silicon-based solid-state nanopore sequencer according to an embodiment of the present invention;
fig. 4 is a schematic flow chart of a method for preparing a silicon-based solid-state nanopore according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In one embodiment, as shown in fig. 1, 2 and 4, the present invention provides a method for preparing a silicon-based solid-state nanopore, the method comprising:
and S1, forming a sandwich structure of the polycrystalline silicon layer and the dielectric layer on the silicon substrate by adopting a silicon-based thin film growth etching technology.
And S2, forming a micro fluid channel on the wafer by adopting a Through Silicon Via (TSV) technology.
S3, forming a dielectric pinhole in the dielectric layer by electrostatic Discharge (ESD).
And S4, etching the dielectric layer pinhole by wet etching to form a suspended nanometer pinhole penetrating through the dielectric layer to the microfluidic channel.
In the embodiment, a silicon-based semiconductor wafer manufacturing technology is used as a support, and a sandwich structure of a polycrystalline silicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel; thereby making the preparation of the silicon-based solid state nanopore compatible with CMOS integrated circuit manufacturing technology and providing manufacturing technology for batch CMOS and solid state nanopore integration. And, through the control to the breakdown voltage and current of the electrostatic discharge ESD, can control the size and uniformity of the solid-state nanopore accurately. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
In one embodiment, in step S1, the forming a sandwich structure of a polysilicon layer and a dielectric layer on a silicon substrate by using a silicon-based thin film growth etching technique includes:
B. carrying out first polycrystalline silicon deposition on a silicon substrate of a wafer to form a first polycrystalline silicon layer;
C. performing oxide deposition on the first polysilicon layer to form a dielectric layer;
D. and carrying out second-time polycrystalline silicon deposition on the dielectric layer to form a second polycrystalline silicon layer, thereby forming a sandwich structure of the first polycrystalline silicon layer, the dielectric layer and the second polycrystalline silicon layer.
In the embodiment, a silicon-based thin film growth etching technology is adopted to perform first polysilicon deposition, oxide deposition and second polysilicon deposition on a silicon substrate, so that a sandwich structure of a first polysilicon layer, a dielectric layer and a second polysilicon layer is formed. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
In one embodiment, in the step S2, the forming of the microfluidic channels on the wafer by using the through silicon via TSV technology; the method comprises the following steps:
E. carrying out TSV imaging and etching on the back of the wafer;
F. oxide etching and two-sided He+Ion implantation;
G. carrying out titanium (Ti) deposition on the back of the wafer;
H. and performing titanium deposition and titanium silicification on the front surface of the wafer to form titanium silicide.
Through the above operations, microfluidic channels are formed on the wafer.
Optionally, in step S2, a Micro-Electro-Mechanical System (MEMS) technology may be further used to form the microfluidic channels on the wafer, and the preparation method thereof is similar to the method of forming the microfluidic channels on the wafer by using the TSV technology, and is not described herein again.
In the embodiment, the micro fluid channel is formed on the wafer by adopting the TSV technology, so that the preparation of the silicon-based solid nano hole is compatible with the CMOS integrated circuit manufacturing technology, and the manufacturing technology is provided for batch CMOS and nano hole integration.
In one embodiment, in step S3, the forming a dielectric layer pinhole in a dielectric layer by using ESD includes:
I. applying electrostatic discharge (ESD) in the dielectric layer;
J. and performing Oxide Breakdown (Oxide Breakdown) in the dielectric layer to form a dielectric layer pinhole.
Optionally, in step S3, a dielectric layer pinhole may be formed in the dielectric layer by using a high-voltage ultrashort pulse, and the preparation method thereof is similar to the method for forming a dielectric layer pinhole in the dielectric layer by using ESD, and is not described herein again.
In the embodiment, the electrostatic discharge ESD is adopted to form the dielectric layer pin hole in the dielectric layer, so that the preparation of the silicon-based solid-state nanopore is compatible with the CMOS integrated circuit manufacturing technology, and the manufacturing technology is provided for batch CMOS and nanopore integration. And, through the control to the breakdown voltage and current of the electrostatic discharge ESD, can control the size and uniformity of the solid-state nanopore accurately. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
In one embodiment, in step S4, the performing the wet etching on the dielectric layer to form a suspended nano-scale pinhole penetrating through the dielectric layer to the microfluidic channel includes:
K. carrying out titanium silicide etching to remove the titanium silicide formed on the wafer;
and L, performing TMAH (tetramethylammonium hydroxide) etching on the dielectric layer pinhole to form a suspended nano-scale pinhole penetrating through the dielectric layer to the micro fluid channel.
In this embodiment, the dielectric layer is etched to form suspended nano-scale pinholes that penetrate through the dielectric layer to the microfluidic channels by wet etching. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
Preferably, the material of the dielectric layer includes at least one of: SiO2, SiNx, HfOx, or other dielectric material.
Preferably, the polysilicon electrode may be replaced with other conductive materials such as metal, semiconductor, or metal oxide.
In one embodiment, the method further comprises: and forming a pad oxide layer on the silicon substrate by adopting a silicon-based thin film growth etching technology, wherein the pad oxide layer is arranged below the polycrystalline silicon layer and is used for reducing the leakage current between an upper electrode and a lower electrode of the nanopore during gene sequencing of the silicon-based solid nanopore.
In this embodiment, a pad oxide layer is formed on a silicon substrate by using a silicon-based thin film growth etching technique to reduce leakage current between upper and lower electrodes of a nanopore during gene sequencing of a silicon-based solid nanopore. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
In one embodiment, the method further comprises: and depositing a layer of pinhole size adjusting film on the nano-scale pinholes of the dielectric layer, wherein the pinhole size adjusting film is used for further adjusting the size of the nano-scale pinholes. The pinhole size adjusting film comprises at least one of the following: dielectric film, metal film.
In this embodiment, the size of the nano-scale pinhole can be further adjusted by depositing a pinhole size adjusting film on the nano-scale pinhole of the dielectric layer, so that the size and consistency of the nano-scale pinhole can be accurately controlled. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
In one embodiment, as shown in fig. 2, the present invention provides a silicon-based solid state nanopore 100 comprising: a silicon substrate 10, a polysilicon layer 20 and a dielectric layer 30; wherein:
the polysilicon layer 20 is formed on the silicon substrate 10 by adopting a silicon-based thin film growth etching technology, and the dielectric layer 30 is formed on the polysilicon layer 20 by adopting the silicon-based thin film growth etching technology, so that a sandwich structure of the polysilicon layer 20 and the dielectric layer 30 is formed on the silicon substrate 10; further, a Through Silicon Via (TSV) technology is adopted to form a microfluidic channel 40 on the wafer; forming a dielectric layer pinhole in the dielectric layer 30 by electrostatic discharge (ESD); and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole 50 penetrating through the dielectric layer to the microfluidic channel.
In the embodiment, a silicon-based semiconductor wafer manufacturing technology is used as a support, and a sandwich structure of a polycrystalline silicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel; thereby making the preparation of the silicon-based solid state nanopore compatible with CMOS integrated circuit manufacturing technology and providing manufacturing technology for batch CMOS and solid state nanopore integration. And, through the control to the breakdown voltage and current of the electrostatic discharge ESD, can control the size and uniformity of the solid-state nanopore accurately. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
In one embodiment, the forming a sandwich structure of a polysilicon layer and a dielectric layer on a silicon substrate includes:
B. carrying out first polycrystalline silicon deposition on a silicon substrate of a wafer to form a first polycrystalline silicon layer;
C. performing oxide deposition on the first polysilicon layer to form a dielectric layer;
D. and carrying out second-time polycrystalline silicon deposition on the dielectric layer to form a second polycrystalline silicon layer, thereby forming a sandwich structure of the first polycrystalline silicon layer, the dielectric layer and the second polycrystalline silicon layer.
In the embodiment, a silicon-based thin film growth etching technology is adopted to perform first polysilicon deposition, oxide deposition and second polysilicon deposition on a silicon substrate, so that a sandwich structure of a first polysilicon layer, a dielectric layer and a second polysilicon layer is formed. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
In one embodiment, the forming of the microfluidic channel on the wafer by using the Through Silicon Via (TSV) technology is performed; the method comprises the following steps:
E. carrying out TSV imaging and etching on the back of the wafer;
F. oxide etching and two-sided He+Ion implantation;
G. carrying out titanium (Ti) deposition on the back of the wafer;
H. and performing titanium deposition and titanium silicification on the front surface of the wafer to form titanium silicide.
Through the above operations, microfluidic channels are formed on the wafer.
Optionally, a Micro-Electro-Mechanical System (MEMS) technology may be used to form the microfluidic channels on the wafer, and the preparation method is similar to the method for forming the microfluidic channels on the wafer by the TSV technology, and is not described herein again.
In the embodiment, the micro fluid channel is formed on the wafer by adopting the TSV technology, so that the preparation of the silicon-based solid nano hole is compatible with the CMOS integrated circuit manufacturing technology, and the manufacturing technology is provided for batch CMOS and nano hole integration.
In one embodiment, the forming a dielectric layer pinhole in a dielectric layer by using ESD includes:
I. applying electrostatic discharge (ESD) in the dielectric layer;
J. and performing Oxide Breakdown (Oxide Breakdown) in the dielectric layer to form a dielectric layer pinhole.
Optionally, a dielectric layer pinhole may be formed in the dielectric layer by using a high-voltage ultrashort pulse, and the preparation method thereof is similar to the method for forming a dielectric layer pinhole in the dielectric layer by using ESD, and is not described herein again.
In the embodiment, the electrostatic discharge ESD is adopted to form the dielectric layer pin hole in the dielectric layer, so that the preparation of the silicon-based solid-state nanopore is compatible with the CMOS integrated circuit manufacturing technology, and the manufacturing technology is provided for batch CMOS and nanopore integration. And, through the control to the breakdown voltage and current of the electrostatic discharge ESD, can control the size and uniformity of the solid-state nanopore accurately. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
In one embodiment, the forming of the suspended nano-scale pinhole penetrating through the dielectric layer to the microfluidic channel by performing pinhole etching on the dielectric layer by wet etching includes:
K. carrying out titanium silicide etching to remove the titanium silicide formed on the wafer;
and L, performing TMAH (tetramethylammonium hydroxide) etching on the dielectric layer pinhole to form a suspended nano-scale pinhole penetrating through the dielectric layer to the micro fluid channel.
In this embodiment, the dielectric layer is etched to form suspended nano-scale pinholes that penetrate through the dielectric layer to the microfluidic channels by wet etching. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
Preferably, the material of the dielectric layer includes at least one of: SiO2, SiNx, HfOx, or other dielectric material.
Preferably, the polysilicon electrode may be replaced with other conductive materials such as metal, semiconductor, or metal oxide.
In one embodiment, the silicon-based solid nanopore 100 further comprises a pad oxide layer 60 formed on a silicon substrate by using a silicon-based thin film growth etching technique, the pad oxide layer being below the polysilicon layer for reducing leakage current between upper and lower electrodes of the silicon-based solid nanopore during gene sequencing.
In this embodiment, a pad oxide layer is formed on a silicon substrate by using a silicon-based thin film growth etching technique to reduce leakage current between upper and lower electrodes of a nanopore during gene sequencing of a silicon-based solid nanopore. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
In one embodiment, the silicon-based solid state nanopore 100 further comprises a pinhole size adjusting film 70 deposited on the nano-scale pinholes of the dielectric layer for further adjusting the size of the nano-scale pinholes. The pinhole size adjusting film comprises at least one of the following: dielectric film, metal film.
In this embodiment, the size of the nano-scale pinhole can be further adjusted by depositing a pinhole size adjusting film on the nano-scale pinhole of the dielectric layer, so that the size and consistency of the nano-scale pinhole can be accurately controlled. Thereby making the preparation of silicon-based solid-state nanopores compatible with CMOS integrated circuit fabrication techniques and providing fabrication techniques for batch CMOS and nanopore integration.
It should be noted that the above embodiment of the silicon-based solid-state nanopore and the embodiment of the method for preparing the silicon-based solid-state nanopore belong to the same concept, and specific implementation processes thereof are described in detail in the embodiment of the method for preparing the silicon-based solid-state nanopore, and technical features in the embodiment of the method for preparing the silicon-based solid-state nanopore are applicable to the embodiment of the silicon-based solid-state nanopore, and are not described herein again.
In one embodiment, as shown in fig. 2 and 3, the present invention provides a silicon-based solid-state nanopore sequencer comprising a silicon-based solid-state nanopore 100 as described in any of the above embodiments for performing DNA and/or RNA sequencing.
The embodiment of the silicon-based solid-state nanopore sequencer and the embodiment of the silicon-based solid-state nanopore belong to the same concept, specific implementation processes are detailed in the embodiment of the silicon-based solid-state nanopore, and technical features in the embodiment of the silicon-based solid-state nanopore are correspondingly applicable in the embodiment of the silicon-based solid-state nanopore sequencer, and are not described herein again.
In the sequencing of DNA or RNA using the silicon-based solid-state nanopore sequencer, an unknown sample is transported through the silicon-based solid-state nanopore of the silicon-based solid-state nanopore sequencer in an electrolyte solution using electrophoresis. And applying a constant electric field at two ends of the silicon-based solid nanopore, and observing the current in the silicon-based solid nanopore sequencer. The current density at the surface of a silicon-based solid-state nanopore depends on the size of the nanopore and the composition of the DNA or RNA occupying the nanopore. When DNA or RNA passes through the silicon-based solid-state nanopore, the current flowing through the silicon-based solid-state nanopore changes in current density according to the blocking degree of the nanopore by the DNA or RNA, so that the DNA or RNA sequencing is performed according to the current density.
In this embodiment, the preparation of the silicon-based solid-state nanopore sequencer is based on a silicon-based semiconductor wafer manufacturing technology, and a sandwich structure of a polysilicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel; thereby making the preparation of the silicon-based solid state nanopore compatible with CMOS integrated circuit manufacturing technology and providing manufacturing technology for batch CMOS and solid state nanopore integration. And the size and consistency of the solid-state nanometer hole can be further accurately adjusted and controlled by controlling the breakdown voltage and current of the electrostatic discharge ESD and depositing a layer of pinhole size adjusting film on the nanometer pinhole of the dielectric layer. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
The technical solution of the present invention is further described below with a specific example.
In one embodiment, as shown in fig. 4, the present invention provides a method for preparing a silicon-based solid-state nanopore, the method comprising:
s501, forming a pad oxide layer on a silicon substrate by adopting a silicon-based thin film growth etching technology to reduce leakage current between an upper electrode and a lower electrode of a silicon-based solid nanopore during gene sequencing.
S502, performing first polycrystalline silicon deposition on the pad oxide layer by adopting a silicon-based thin film growth etching technology to form a first polycrystalline silicon layer.
S503, performing oxide deposition on the first polycrystalline silicon layer to form a dielectric layer.
S504, performing second polycrystalline silicon deposition on the dielectric layer to form a second polycrystalline silicon layer, so that a sandwich structure of the first polycrystalline silicon layer, the dielectric layer and the second polycrystalline silicon layer is formed.
And S505, carrying out TSV patterning and etching on the back side of the wafer by adopting a TSV technology.
S506, oxide etching and two-side He are carried out+And (5) ion implantation.
And S507, performing titanium (Ti) deposition on the back surface of the wafer.
And S508, performing titanium deposition and titanium silicification on the front surface of the wafer to form titanium silicide, so that the microfluidic channel is formed through the operation.
S509, applying electrostatic discharge (esd) to the dielectric layer.
And S510, performing Oxide Breakdown (Oxide Breakdown) in the dielectric layer to form a dielectric layer pinhole.
And S511, carrying out titanium silicide etching to remove the titanium silicide formed on the wafer.
S512, performing TMAH etching on the dielectric layer pinholes to form suspended nano-scale pinholes which penetrate through the dielectric layer to the microfluidic channel.
S513, depositing a layer of pinhole size adjusting film on the nano-scale pinholes of the dielectric layer, and further adjusting the size of the nano-scale pinholes. The pinhole size adjusting film comprises at least one of the following: dielectric film, metal film.
In the embodiment, a silicon-based semiconductor wafer manufacturing technology is used as a support, and a sandwich structure of a polycrystalline silicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology; forming a microfluidic channel on the wafer by adopting a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by adopting electrostatic discharge ESD; etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel; thereby making the preparation of the silicon-based solid state nanopore compatible with CMOS integrated circuit manufacturing technology and providing manufacturing technology for batch CMOS and solid state nanopore integration. And the size and consistency of the solid-state nanometer hole can be further accurately adjusted and controlled by controlling the breakdown voltage and current of the electrostatic discharge ESD and depositing a layer of pinhole size adjusting film on the nanometer pinhole of the dielectric layer. The solid-state nanopore is used for DNA and/or RNA sequencing, so that the success rate of nanopore sequencing can be greatly improved, and the sequencing time can be greatly shortened.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A method for preparing a silicon-based solid state nanopore, the method comprising:
a sandwich structure of a polycrystalline silicon layer and a dielectric layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology, and the sandwich structure comprises the following components: carrying out first polycrystalline silicon deposition on a silicon substrate of a wafer to form a first polycrystalline silicon layer; performing oxide deposition on the first polysilicon layer to form a dielectric layer; performing second polycrystalline silicon deposition on the dielectric layer to form a second polycrystalline silicon layer, thereby forming a sandwich structure of the first polycrystalline silicon layer, the dielectric layer and the second polycrystalline silicon layer;
forming a microfluidic channel on a wafer by using a Through Silicon Via (TSV) technique, comprising: patterning and etching a Through Silicon Via (TSV) on the back surface of the wafer; oxide etch and two-sided helium ion (He) are performed+) Injecting; carrying out titanium (Ti) deposition on the back of the wafer; carrying out titanium deposition and titanium silicification on the front surface of the wafer to form titanium silicide; forming a microfluidic channel on the wafer through the operation;
forming a dielectric layer pinhole in the dielectric layer by electrostatic discharge (ESD);
and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel.
2. The method of claim 1, wherein forming a dielectric layer pinhole in a dielectric layer using electrostatic discharge (ESD) comprises:
applying electrostatic discharge (ESD) in the dielectric layer;
and performing oxide breakdown in the dielectric layer to form a dielectric layer pinhole.
3. The method of claim 1, wherein the dielectric layer pinholes are also formed in the dielectric layer using high voltage ultrashort pulses.
4. The method of claim 1, wherein the step of forming suspended nano-scale pinholes through the dielectric layer to the microfluidic channel by wet etching comprises:
carrying out titanium silicide etching to remove the titanium silicide formed on the wafer;
and performing tetramethylammonium hydroxide (TMAH) etching on the dielectric layer pinholes to form suspended nano-scale pinholes which penetrate through the dielectric layer to the microfluidic channels.
5. The method of claim 1, wherein the method further comprises: a pad oxide layer is formed on a silicon substrate by adopting a silicon-based thin film growth etching technology and is used for reducing the leakage current between an upper electrode and a lower electrode of a nanopore when the silicon-based solid nanopore is subjected to gene sequencing.
6. The method of claim 1, wherein the method further comprises: and depositing a layer of pinhole size adjusting film on the nano-scale pinholes of the dielectric layer, wherein the adjusting film is used for further adjusting the size of the nano-scale pinholes.
7. A silicon-based solid-state nanopore, characterized in that it is prepared using a method of preparation of a silicon-based solid-state nanopore according to any of claims 1 to 6, comprising: a silicon substrate, a polysilicon layer and a dielectric layer; wherein:
the polycrystalline silicon layer is formed on the silicon substrate by adopting a silicon-based thin film growth etching technology, and the dielectric layer is formed on the polycrystalline silicon layer by adopting the silicon-based thin film growth etching technology, so that a sandwich structure of the polycrystalline silicon layer and the dielectric layer is formed on the silicon substrate; further, forming a micro fluid channel on the wafer by using a Through Silicon Via (TSV) technology; forming a dielectric layer pinhole in the dielectric layer by electrostatic discharge (ESD); and etching the dielectric layer pinhole by adopting wet etching to form a suspended nano-scale pinhole which penetrates through the dielectric layer to the microfluidic channel.
8. A silicon-based solid state nanopore sequencer comprising a silicon-based solid state nanopore according to claim 7, for performing deoxyribonucleic acid (DNA) and/or ribonucleic acid (RNA) sequencing.
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Denomination of invention: A silicon-based solid-state nanopore and its preparation method, silicon-based solid-state nanopore sequencer Effective date of registration: 20231219 Granted publication date: 20210423 Pledgee: Shenzhen Rural Commercial Bank Co.,Ltd. Futian Sub branch Pledgor: Shenzhen Ruhan Technology Co.,Ltd. Registration number: Y2023980072695 |